# =============================================================================
# ____ _ _ ____ _ _
# _ __ _ _ / ___| | | | _ \| | __| | ___ _ __ ___
# | '_ \| | | | | _| |_| | | | | | / _` |/ _ \| '_ ` _ \
# | |_) | |_| | |_| | _ | |_| | |___ | (_| | (_) | | | | | |
# | .__/ \__, |\____|_| |_|____/|_____(_)__,_|\___/|_| |_| |_|
# |_| |___/
# =============================================================================
# Authors:
# Patrick Lehmann
#
# Package module: DOM: Sequential statements.
#
# License:
# ============================================================================
# Copyright (C) 2019-2021 Tristan Gingold
#
# This program is free software: you can redistribute it and/or modify
# it under the terms of the GNU General Public License as published by
# the Free Software Foundation, either version 2 of the License, or
# (at your option) any later version.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
# You should have received a copy of the GNU General Public License
# along with this program. If not, see <gnu.org/licenses>.
#
# SPDX-License-Identifier: GPL-2.0-or-later
# ============================================================================
"""
This module implements derived sequential statement classes from :mod:`pyVHDLModel.Sequential`.
"""
from typing import Iterable
from pyTooling.Decorators import export, InheritDocString
from pyVHDLModel.Base import ExpressionUnion, Range
from pyVHDLModel.Symbol import Symbol
from pyVHDLModel.Sequential import SequentialStatement, SequentialChoice, SequentialCase
from pyVHDLModel.Sequential import IfBranch as VHDLModel_IfBranch
from pyVHDLModel.Sequential import ElsifBranch as VHDLModel_ElsifBranch
from pyVHDLModel.Sequential import ElseBranch as VHDLModel_ElseBranch
from pyVHDLModel.Sequential import IndexedChoice as VHDLModel_IndexedChoice
from pyVHDLModel.Sequential import RangedChoice as VHDLModel_RangedChoice
from pyVHDLModel.Sequential import Case as VHDLModel_Case
from pyVHDLModel.Sequential import OthersCase as VHDLModel_OthersCase
from pyVHDLModel.Sequential import IfStatement as VHDLModel_IfStatement
from pyVHDLModel.Sequential import CaseStatement as VHDLModel_CaseStatement
from pyVHDLModel.Sequential import ForLoopStatement as VHDLModel_ForLoopStatement
from pyVHDLModel.Sequential import WhileLoopStatement as VHDLModel_WhileLoopStatement
from pyVHDLModel.Sequential import NullStatement as VHDLModel_NullStatement
from pyVHDLModel.Sequential import ReturnStatement as VHDLModel_ReturnStatement
from pyVHDLModel.Sequential import WaitStatement as VHDLModel_WaitStatement
from pyVHDLModel.Sequential import NextStatement as VHDLModel_NextStatement
from pyVHDLModel.Sequential import ExitStatement as VHDLModel_ExitStatement
from pyVHDLModel.Sequential import SequentialProcedureCall as VHDLModel_SequentialProcedureCall
from pyVHDLModel.Sequential import SequentialSimpleSignalAssignment as VHDLModel_SequentialSimpleSignalAssignment
from pyVHDLModel.Sequential import SequentialVariableAssignment as VHDLModel_SequentialVariableAssignment
from pyVHDLModel.Sequential import (
SequentialConditionalVariableAssignment as VHDLModel_SequentialConditionalVariableAssignment,
)
from pyVHDLModel.Sequential import (
SequentialConditionalSignalAssignment as VHDLModel_SequentialConditionalSignalAssignment,
)
from pyVHDLModel.Sequential import (
SequentialSelectedVariableAssignment as VHDLModel_SequentialSelectedVariableAssignment,
)
from pyVHDLModel.Sequential import SequentialSelectedSignalAssignment as VHDLModel_SequentialSelectedSignalAssignment
from pyVHDLModel.Sequential import SignalForceAssignment as VHDLModel_SignalForceAssignment
from pyVHDLModel.Sequential import SignalReleaseAssignment as VHDLModel_SignalReleaseAssignment
from pyVHDLModel.Common import ConditionalExpression as VHDLModel_ConditionalExpression
from pyVHDLModel.Common import SelectedExpression as VHDLModel_SelectedExpression
from pyVHDLModel.Common import OthersSelectedExpression as VHDLModel_OthersSelectedExpression
from pyVHDLModel.Sequential import SequentialReportStatement as VHDLModel_SequentialReportStatement
from pyVHDLModel.Sequential import SequentialAssertStatement as VHDLModel_SequentialAssertStatement
from pyGHDL.libghdl import Iir, utils
from pyGHDL.libghdl.vhdl import nodes
from pyGHDL.dom import DOMMixin, Position, DOMException
from pyGHDL.dom.Concurrent import WaveformElement, ParameterAssociationItem # TODO: move out from concurrent?
from pyGHDL.dom.Concurrent import GetWaveformElementsFromChainedNodes
from pyGHDL.dom.Symbol import SignalSymbol, VariableSymbol
from pyGHDL.dom.Concurrent import GetConditionalWaveformsFromChainedNodes, GetSelectedWaveformsFromChainedNodes
[docs]
@export
@InheritDocString(VHDLModel_IfBranch, merge=True)
class IfBranch(VHDLModel_IfBranch, DOMMixin):
"""
This class implements a :mod:`pyGHDL.dom` object derived from :class:`pyVHDLModel.Sequential.IfBranch`.
"""
[docs]
def __init__(
self,
branchNode: Iir,
condition: ExpressionUnion,
statements: Iterable[SequentialStatement] = None,
) -> None:
"""
Initializes an :vhdlkw:`if` branch.
:param branchNode: The IIR node of the branch this object represents.
:param condition: The condition under which this branch's statements are executed.
:param statements: List of all sequential statements in this construct.
"""
super().__init__(condition, statements)
DOMMixin.__init__(self, branchNode)
[docs]
@classmethod
def parse(cls, branchNode: Iir, label: str) -> "IfBranch":
"""
Translates the IIR node of the branch to an :class:`IfBranch`.
:param branchNode: The IIR node of the branch.
:param label: The statement's label, or ``None`` if it has none.
:returns: The translated branch.
"""
from pyGHDL.dom._Translate import (
GetSequentialStatementsFromChainedNodes,
GetExpressionFromNode,
)
condition = GetExpressionFromNode(nodes.Get_Condition(branchNode))
statementChain = nodes.Get_Sequential_Statement_Chain(branchNode)
statements = GetSequentialStatementsFromChainedNodes(statementChain, "if branch", label)
return cls(branchNode, condition, statements)
[docs]
@export
@InheritDocString(VHDLModel_ElsifBranch, merge=True)
class ElsifBranch(VHDLModel_ElsifBranch, DOMMixin):
"""
This class implements a :mod:`pyGHDL.dom` object derived from :class:`pyVHDLModel.Sequential.ElsifBranch`.
"""
[docs]
def __init__(
self,
branchNode: Iir,
condition: ExpressionUnion,
statements: Iterable[SequentialStatement] = None,
) -> None:
"""
Initializes an :vhdlkw:`elsif` branch of an :vhdlkw:`if` statement.
:param branchNode: The IIR node of the branch this object represents.
:param condition: The condition under which this branch's statements are executed.
:param statements: List of all sequential statements in this construct.
"""
super().__init__(condition, statements)
DOMMixin.__init__(self, branchNode)
[docs]
@classmethod
def parse(cls, branchNode: Iir, condition: Iir, label: str) -> "ElsifBranch":
"""
Translates the IIR node of the branch to an :class:`ElsifBranch`.
:param branchNode: The IIR node of the branch.
:param condition: The condition guarding the branch.
:param label: The statement's label, or ``None`` if it has none.
:returns: The translated branch.
"""
from pyGHDL.dom._Translate import (
GetSequentialStatementsFromChainedNodes,
GetExpressionFromNode,
)
condition = GetExpressionFromNode(condition)
statementChain = nodes.Get_Sequential_Statement_Chain(branchNode)
statements = GetSequentialStatementsFromChainedNodes(statementChain, "elsif branch", label)
return cls(branchNode, condition, statements)
[docs]
@export
@InheritDocString(VHDLModel_ElseBranch, merge=True)
class ElseBranch(VHDLModel_ElseBranch, DOMMixin):
"""
This class implements a :mod:`pyGHDL.dom` object derived from :class:`pyVHDLModel.Sequential.ElseBranch`.
"""
[docs]
def __init__(
self,
branchNode: Iir,
statements: Iterable[SequentialStatement] = None,
) -> None:
"""
Initializes an else branch.
:param branchNode: The IIR node of the branch this object represents.
:param statements: List of all sequential statements in this construct.
"""
super().__init__(statements)
DOMMixin.__init__(self, branchNode)
[docs]
@classmethod
def parse(cls, branchNode: Iir, label: str) -> "ElseBranch":
"""
Translates the IIR node of the branch to an :class:`ElseBranch`.
:param branchNode: The IIR node of the branch.
:param label: The statement's label, or ``None`` if it has none.
:returns: The translated branch.
"""
from pyGHDL.dom._Translate import (
GetSequentialStatementsFromChainedNodes,
)
statementChain = nodes.Get_Sequential_Statement_Chain(branchNode)
statements = GetSequentialStatementsFromChainedNodes(statementChain, "else branch", label)
return cls(branchNode, statements)
[docs]
@export
@InheritDocString(VHDLModel_IfStatement, merge=True)
class IfStatement(VHDLModel_IfStatement, DOMMixin):
"""
This class implements a :mod:`pyGHDL.dom` object derived from :class:`pyVHDLModel.Sequential.IfStatement`.
"""
[docs]
def __init__(
self,
ifNode: Iir,
ifBranch: IfBranch,
elsifBranches: Iterable[ElsifBranch] = None,
elseBranch: ElseBranch = None,
label: str = None,
) -> None:
"""
Initializes an :vhdlkw:`if` statement.
:param ifNode: The IIR node of the :vhdlkw:`if` statement.
:param ifBranch: The mandatory :vhdlkw:`if` branch.
:param elsifBranches: List of all :vhdlkw:`elsif` branches, in the order they were written.
:param elseBranch: The optional :vhdlkw:`else` branch, or ``None`` if none was given.
:param label: The label of the :vhdlkw:`if` statement, or ``None`` if it has none.
"""
super().__init__(ifBranch, elsifBranches, elseBranch, label)
DOMMixin.__init__(self, ifNode)
[docs]
@classmethod
def parse(cls, ifNode: Iir, label: str) -> "IfStatement":
"""
Translates the IIR node of the :vhdlkw:`if` statement to an :class:`IfStatement`.
:param ifNode: The IIR node of the :vhdlkw:`if` statement.
:param label: The statement's label, or ``None`` if it has none.
:returns: The translated :vhdlkw:`if` statement.
"""
ifBranch = IfBranch.parse(ifNode, label)
elsifBranches = []
elseBranch = None
# WORKAROUND: Python 3.8 syntax
# elseClause = generateNode
# while (elseClause := nodes.Get_Generate_Else_Clause(elseClause)) != nodes.Null_Iir:
elseClause = nodes.Get_Else_Clause(ifNode)
while elseClause != nodes.Null_Iir:
condition = nodes.Get_Condition(elseClause)
if condition != nodes.Null_Iir:
elsifBranches.append(ElsifBranch.parse(elseClause, condition, label))
else:
elseBranch = ElseBranch.parse(elseClause, label)
break
elseClause = nodes.Get_Else_Clause(elseClause)
return cls(ifNode, ifBranch, elsifBranches, elseBranch, label)
[docs]
@export
@InheritDocString(VHDLModel_IndexedChoice, merge=True)
class IndexedChoice(VHDLModel_IndexedChoice, DOMMixin):
"""
This class implements a :mod:`pyGHDL.dom` object derived from :class:`pyVHDLModel.Sequential.IndexedChoice`.
"""
[docs]
def __init__(self, node: Iir, expression: ExpressionUnion) -> None:
"""
Initializes a case choice given by a single value.
:param node: The IIR node this object was translated from.
:param expression: The expression this choice selects on.
"""
super().__init__(expression)
DOMMixin.__init__(self, node)
[docs]
@export
@InheritDocString(VHDLModel_RangedChoice, merge=True)
class RangedChoice(VHDLModel_RangedChoice, DOMMixin):
"""
This class implements a :mod:`pyGHDL.dom` object derived from :class:`pyVHDLModel.Sequential.RangedChoice`.
"""
[docs]
def __init__(self, node: Iir, rng: Range) -> None:
"""
Initializes a case choice given by a range.
:param node: The IIR node this object was translated from.
:param rng: The range this choice selects on.
"""
super().__init__(rng)
DOMMixin.__init__(self, node)
[docs]
@export
@InheritDocString(VHDLModel_Case, merge=True)
class Case(VHDLModel_Case, DOMMixin):
"""
This class implements a :mod:`pyGHDL.dom` object derived from :class:`pyVHDLModel.Sequential.Case`.
"""
[docs]
def __init__(
self,
node: Iir,
choices: Iterable[SequentialChoice],
statements: Iterable[SequentialStatement] = None,
) -> None:
"""
Initializes a case.
:param node: The IIR node this object was translated from.
:param choices: List of all choices selecting this alternative.
:param statements: List of all sequential statements in this construct.
"""
super().__init__(choices, statements)
DOMMixin.__init__(self, node)
[docs]
@classmethod
def parse(cls, caseNode: Iir, choices: Iterable[SequentialChoice], label: str) -> "Case":
"""
Translates the IIR node of the alternative to a :class:`Case`.
:param caseNode: The IIR node of the alternative.
:param choices: List of all choices selecting this alternative.
:param label: The statement's label, or ``None`` if it has none.
:returns: The translated alternative.
"""
from pyGHDL.dom._Translate import GetSequentialStatementsFromChainedNodes
statementChain = nodes.Get_Associated_Chain(caseNode)
statements = GetSequentialStatementsFromChainedNodes(statementChain, "case", label)
return cls(caseNode, choices, statements)
[docs]
@export
@InheritDocString(VHDLModel_OthersCase, merge=True)
class OthersCase(VHDLModel_OthersCase, DOMMixin):
"""
This class implements a :mod:`pyGHDL.dom` object derived from :class:`pyVHDLModel.Sequential.OthersCase`.
"""
[docs]
def __init__(
self,
caseNode: Iir,
statements: Iterable[SequentialStatement] = None,
) -> None:
"""
Initializes an :vhdlkw:`others` alternative.
:param caseNode: The IIR node of the :vhdlkw:`case` statement.
:param statements: List of all sequential statements in this construct.
"""
super().__init__(statements)
DOMMixin.__init__(self, caseNode)
[docs]
@classmethod
def parse(cls, caseNode: Iir, label: str = None) -> "OthersCase":
"""
Translates the IIR node of the alternative to an :class:`OthersCase`.
:param caseNode: The IIR node of the alternative.
:param label: The statement's label, or ``None`` if it has none.
:returns: The translated alternative.
"""
from pyGHDL.dom._Translate import GetSequentialStatementsFromChainedNodes
body = nodes.Get_Associated_Block(caseNode)
if body is nodes.Null_Iir:
return cls(caseNode)
statementChain = nodes.Get_Concurrent_Statement_Chain(body)
statements = GetSequentialStatementsFromChainedNodes(statementChain, "case others", label)
return cls(caseNode, statements)
[docs]
@export
@InheritDocString(VHDLModel_CaseStatement, merge=True)
class CaseStatement(VHDLModel_CaseStatement, DOMMixin):
"""
This class implements a :mod:`pyGHDL.dom` object derived from :class:`pyVHDLModel.Sequential.CaseStatement`.
"""
[docs]
def __init__(
self,
caseNode: Iir,
label: str,
expression: ExpressionUnion,
cases: Iterable[SequentialCase],
) -> None:
"""
Initializes a :vhdlkw:`case` statement.
:param caseNode: The IIR node of the :vhdlkw:`case` statement.
:param label: The label of the :vhdlkw:`case` statement, or ``None`` if it has none.
:param expression: The expression being tested.
:param cases: List of all alternatives, in the order they were written.
"""
super().__init__(expression, cases, label)
DOMMixin.__init__(self, caseNode)
[docs]
@classmethod
def parse(cls, caseNode: Iir, label: str) -> "CaseStatement":
"""
Translates the IIR node of the alternative to a :class:`CaseStatement`.
:param caseNode: The IIR node of the alternative.
:param label: The statement's label, or ``None`` if it has none.
:returns: The translated alternative.
"""
from pyGHDL.dom._Utils import GetIirKindOfNode
from pyGHDL.dom._Translate import (
GetExpressionFromNode,
GetRangeFromNode,
GetName,
)
expression = GetExpressionFromNode(nodes.Get_Expression(caseNode))
cases = []
choices = None
alternative = nodes.Get_Case_Statement_Alternative_Chain(caseNode)
cNode = alternative
while alternative != nodes.Null_Iir:
choiceKind = GetIirKindOfNode(alternative)
sameAlternative = nodes.Get_Same_Alternative_Flag(alternative)
if choiceKind in (
nodes.Iir_Kind.Choice_By_Name,
nodes.Iir_Kind.Choice_By_Expression,
):
choiceExpression = GetExpressionFromNode(nodes.Get_Choice_Expression(alternative))
choice = IndexedChoice(alternative, choiceExpression)
if sameAlternative:
choices.append(choice)
alternative = nodes.Get_Chain(alternative)
continue
elif choiceKind is nodes.Iir_Kind.Choice_By_Range:
choiceRange = nodes.Get_Choice_Range(alternative)
choiceRangeKind = GetIirKindOfNode(choiceRange)
if choiceRangeKind == nodes.Iir_Kind.Range_Expression:
rng = GetRangeFromNode(choiceRange)
elif choiceRangeKind in (
nodes.Iir_Kind.Attribute_Name,
nodes.Iir_Kind.Parenthesis_Name,
):
rng = GetName(choiceRange)
else:
pos = Position.parse(alternative)
raise DOMException(
f"Unknown choice range kind '{choiceRangeKind.name}' in case statement at line {pos.Line}."
)
choice = RangedChoice(alternative, rng)
if sameAlternative:
choices.append(choice)
alternative = nodes.Get_Chain(alternative)
continue
elif choiceKind is nodes.Iir_Kind.Choice_By_Others:
if choices is not None:
cases.append(Case.parse(alternative, choices, label))
choices = None
cases.append(OthersCase.parse(alternative, label))
alternative = nodes.Get_Chain(alternative)
cNode = alternative
continue
else:
pos = Position.parse(alternative)
raise DOMException(f"Unknown choice kind '{choiceKind.name}' in case statement at line {pos.Line}.")
if choices is not None:
cases.append(Case.parse(cNode, choices, label))
cNode = alternative
choices = [
choice,
]
alternative = nodes.Get_Chain(alternative)
if choices is not None:
cases.append(Case.parse(cNode, choices, label))
return cls(caseNode, label, expression, cases)
[docs]
@export
@InheritDocString(VHDLModel_ForLoopStatement, merge=True)
class ForLoopStatement(VHDLModel_ForLoopStatement, DOMMixin):
"""
This class implements a :mod:`pyGHDL.dom` object derived from :class:`pyVHDLModel.Sequential.ForLoopStatement`.
"""
[docs]
def __init__(
self,
loopNode: Iir,
loopIndex: str,
rng: Range,
statements: Iterable[SequentialStatement] = None,
label: str = None,
) -> None:
"""
Initializes a :vhdlkw:`for..loop` statement.
:param loopNode: The IIR node of the :vhdlkw:`loop` statement.
:param loopIndex: The name of the loop's index.
:param rng: The range the loop iterates over.
:param statements: List of all sequential statements in this construct.
:param label: The label of the :vhdlkw:`for..loop` statement, or ``None`` if it has none.
"""
super().__init__(loopIndex, rng, statements, label)
DOMMixin.__init__(self, loopNode)
[docs]
@classmethod
def parse(cls, loopNode: Iir, label: str) -> "ForLoopStatement":
"""
Translates the IIR node of the loop statement to a :class:`ForLoopStatement`.
:param loopNode: The IIR node of the loop statement.
:param label: The statement's label, or ``None`` if it has none.
:returns: The translated loop statement.
"""
from pyGHDL.dom._Utils import GetNameOfNode
from pyGHDL.dom._Translate import (
GetSequentialStatementsFromChainedNodes,
GetDiscreteRangeFromNode,
)
spec = nodes.Get_Parameter_Specification(loopNode)
loopIndex = GetNameOfNode(spec)
rng = GetDiscreteRangeFromNode(nodes.Get_Discrete_Range(spec), "for...loop statement")
statementChain = nodes.Get_Sequential_Statement_Chain(loopNode)
statements = GetSequentialStatementsFromChainedNodes(statementChain, "for", label)
return cls(loopNode, loopIndex, rng, statements, label)
[docs]
@export
@InheritDocString(VHDLModel_WhileLoopStatement, merge=True)
class WhileLoopStatement(VHDLModel_WhileLoopStatement, DOMMixin):
"""
This class implements a :mod:`pyGHDL.dom` object derived from :class:`pyVHDLModel.Sequential.WhileLoopStatement`.
"""
[docs]
def __init__(
self,
loopNode: Iir,
condition: ExpressionUnion,
statements: Iterable[SequentialStatement] = None,
label: str = None,
) -> None:
"""
Initializes a :vhdlkw:`while..loop` statement.
:param loopNode: The IIR node of the :vhdlkw:`loop` statement.
:param condition: The condition tested before each iteration; the loop ends when it is false.
:param statements: List of all sequential statements in this construct.
:param label: The label of the :vhdlkw:`while..loop` statement, or ``None`` if it has none.
"""
super().__init__(condition, statements, label)
DOMMixin.__init__(self, loopNode)
[docs]
@classmethod
def parse(cls, loopNode: Iir, label: str) -> "WhileLoopStatement":
"""
Translates the IIR node of the loop statement to a :class:`WhileLoopStatement`.
:param loopNode: The IIR node of the loop statement.
:param label: The statement's label, or ``None`` if it has none.
:returns: The translated loop statement.
"""
from pyGHDL.dom._Utils import GetNameOfNode, GetIirKindOfNode
from pyGHDL.dom._Translate import (
GetSequentialStatementsFromChainedNodes,
GetRangeFromNode,
GetName,
GetOptionalExpressionFromNode,
)
# spec = nodes.Get_Parameter_Specification(loopNode)
# loopIndex = GetNameOfNode(spec)
#
# discreteRange = nodes.Get_Discrete_Range(spec)
# rangeKind = GetIirKindOfNode(discreteRange)
# if rangeKind == nodes.Iir_Kind.Range_Expression:
# rng = GetRangeFromNode(discreteRange)
# elif rangeKind in (
# nodes.Iir_Kind.Attribute_Name,
# nodes.Iir_Kind.Parenthesis_Name,
# ):
# rng = GetName(discreteRange)
# else:
# pos = Position.parse(loopNode)
# raise DOMException(
# f"Unknown discrete range kind '{rangeKind.name}' in for...loop statement at line {pos.Line}."
# )
condition = GetOptionalExpressionFromNode(nodes.Get_Condition(loopNode))
statementChain = nodes.Get_Sequential_Statement_Chain(loopNode)
statements = GetSequentialStatementsFromChainedNodes(statementChain, "while", label)
return cls(loopNode, condition, statements, label)
[docs]
@export
@InheritDocString(VHDLModel_SequentialSimpleSignalAssignment, merge=True)
class SequentialSimpleSignalAssignment(VHDLModel_SequentialSimpleSignalAssignment, DOMMixin):
"""
This class implements a :mod:`pyGHDL.dom` object derived from :class:`pyVHDLModel.Sequential.SequentialSimpleSignalAssignment`.
"""
[docs]
def __init__(
self,
assignmentNode: Iir,
target: SignalSymbol,
waveform: Iterable[WaveformElement],
label: str = None,
) -> None:
"""
Initializes a simple sequential signal assignment.
:param assignmentNode: The IIR node of the assignment statement.
:param target: Reference to the assignment's destination.
:param waveform: List of all waveform elements, in the order they were written.
:param label: The label of the sequential signal assignment, or ``None`` if it has none.
"""
super().__init__(target, waveform, label)
DOMMixin.__init__(self, assignmentNode)
[docs]
@classmethod
def parse(cls, assignmentNode: Iir, label: str = None) -> "SequentialSimpleSignalAssignment":
"""
Translates the IIR node of the assignment statement to a :class:`SequentialSimpleSignalAssignment`.
:param assignmentNode: The IIR node of the assignment statement.
:param label: The statement's label, or ``None`` if it has none.
:returns: The translated assignment statement.
"""
from pyGHDL.dom._Translate import GetName
targetNode = nodes.Get_Target(assignmentNode)
targetName = SignalSymbol(targetNode, GetName(targetNode))
waveform = GetWaveformElementsFromChainedNodes(nodes.Get_Waveform_Chain(assignmentNode))
return cls(assignmentNode, targetName, waveform, label)
def GetConditionalExpressionsFromChainedNodes(nodeChain: Iir) -> Iterable["ConditionalExpression"]:
"""
Translates a chain of ``Conditional_Expression`` nodes into a sequence of :class:`ConditionalExpression`.
:param nodeChain: The IIR node starting the chain of conditional expressions.
:returns: The translated conditional expressions, in source order.
"""
return [ConditionalExpression.parse(node) for node in utils.chain_iter(nodeChain)]
def GetSelectedExpressionsFromChainedNodes(nodeChain: Iir) -> Iterable:
"""
Translates a chain of choices into a sequence of :class:`SelectedExpression`/
:class:`OthersSelectedExpression`. Same grouping algorithm as
:func:`pyGHDL.dom.Concurrent.GetSelectedWaveformsFromChainedNodes`, but the associated content is
a plain expression (``Get_Associated_Expr``) instead of a waveform chain.
:param nodeChain: The IIR node starting the chain of choices.
:returns: The translated selected expressions, in source order.
:raises DOMException: If a choice's kind is not handled.
"""
from pyGHDL.dom._Utils import GetIirKindOfNode
from pyGHDL.dom._Translate import GetExpressionFromNode, GetRangeFromNode
alternatives = []
choices = None
ownerNode = None
choice = nodeChain
while choice != nodes.Null_Iir:
kind = GetIirKindOfNode(choice)
sameAlternative = nodes.Get_Same_Alternative_Flag(choice)
if kind == nodes.Iir_Kind.Choice_By_Expression:
choiceValue = IndexedChoice(choice, GetExpressionFromNode(nodes.Get_Choice_Expression(choice)))
if sameAlternative:
choices.append(choiceValue)
choice = nodes.Get_Chain(choice)
continue
elif kind == nodes.Iir_Kind.Choice_By_Range:
choiceValue = RangedChoice(choice, GetRangeFromNode(nodes.Get_Choice_Range(choice)))
if sameAlternative:
choices.append(choiceValue)
choice = nodes.Get_Chain(choice)
continue
elif kind == nodes.Iir_Kind.Choice_By_Others:
if choices is not None:
expression = GetExpressionFromNode(nodes.Get_Associated_Expr(ownerNode))
alternatives.append(SelectedExpression(ownerNode, choices, expression))
choices = None
othersExpression = GetExpressionFromNode(nodes.Get_Associated_Expr(choice))
alternatives.append(OthersSelectedExpression(choice, othersExpression))
choice = nodes.Get_Chain(choice)
continue
else:
position = Position.parse(choice)
raise DOMException(f"Unknown choice kind '{kind.name}' in selected expression at {position}.")
if choices is not None:
expression = GetExpressionFromNode(nodes.Get_Associated_Expr(ownerNode))
alternatives.append(SelectedExpression(ownerNode, choices, expression))
ownerNode = choice
choices = [choiceValue]
choice = nodes.Get_Chain(choice)
if choices is not None:
expression = GetExpressionFromNode(nodes.Get_Associated_Expr(ownerNode))
alternatives.append(SelectedExpression(ownerNode, choices, expression))
return alternatives
[docs]
@export
@InheritDocString(VHDLModel_ConditionalExpression, merge=True)
class ConditionalExpression(VHDLModel_ConditionalExpression, DOMMixin):
"""
This class implements a :mod:`pyGHDL.dom` object derived from :class:`pyVHDLModel.Common.ConditionalExpression`.
"""
[docs]
def __init__(self, node: Iir, expression: ExpressionUnion, condition: ExpressionUnion = None) -> None:
"""
Initializes a conditional expression.
:param node: The IIR node this object was translated from.
:param expression: The value assigned when the condition holds.
:param condition: The condition selecting this alternative.
"""
super().__init__(expression, condition)
DOMMixin.__init__(self, node)
[docs]
@classmethod
def parse(cls, node: Iir) -> "ConditionalExpression":
"""
Translates an IIR node to a :class:`ConditionalExpression`.
:param node: The IIR node this object is translated from.
:returns: The translated object.
"""
from pyGHDL.dom._Translate import GetExpressionFromNode, GetOptionalExpressionFromNode
expression = GetExpressionFromNode(nodes.Get_Expression(node))
condition = GetOptionalExpressionFromNode(nodes.Get_Condition(node))
return cls(node, expression, condition)
[docs]
@export
@InheritDocString(VHDLModel_SelectedExpression, merge=True)
class SelectedExpression(VHDLModel_SelectedExpression, DOMMixin):
"""
This class implements a :mod:`pyGHDL.dom` object derived from :class:`pyVHDLModel.Common.SelectedExpression`.
"""
[docs]
def __init__(self, node: Iir, choices: Iterable, expression: ExpressionUnion) -> None:
"""
Initializes a selected expression.
:param node: The IIR node this object was translated from.
:param choices: List of all choices selecting this alternative.
:param expression: The value assigned for the matching choices.
"""
super().__init__(choices, expression)
DOMMixin.__init__(self, node)
[docs]
@export
@InheritDocString(VHDLModel_SequentialVariableAssignment, merge=True)
class SequentialVariableAssignment(VHDLModel_SequentialVariableAssignment, DOMMixin):
"""
This class implements a :mod:`pyGHDL.dom` object derived from :class:`pyVHDLModel.Sequential.SequentialVariableAssignment`.
"""
[docs]
def __init__(
self,
assignmentNode: Iir,
target: VariableSymbol,
expression: ExpressionUnion,
label: str = None,
) -> None:
"""
Initializes a simple sequential variable assignment.
:param assignmentNode: The IIR node of the assignment statement.
:param target: Reference to the assignment's destination.
:param expression: The assigned expression.
:param label: The label of the variable assignment, or ``None`` if it has none.
"""
super().__init__(target, expression, label)
DOMMixin.__init__(self, assignmentNode)
[docs]
@classmethod
def parse(cls, assignmentNode: Iir, label: str = None) -> "SequentialVariableAssignment":
"""
Translates the IIR node of the assignment statement to a :class:`SequentialVariableAssignment`.
:param assignmentNode: The IIR node of the assignment statement.
:param label: The statement's label, or ``None`` if it has none.
:returns: The translated assignment statement.
"""
from pyGHDL.dom._Translate import GetName, GetExpressionFromNode
targetNode = nodes.Get_Target(assignmentNode)
targetName = VariableSymbol(targetNode, GetName(targetNode))
expression = GetExpressionFromNode(nodes.Get_Expression(assignmentNode))
return cls(assignmentNode, targetName, expression, label)
[docs]
@export
@InheritDocString(VHDLModel_SequentialConditionalVariableAssignment, merge=True)
class SequentialConditionalVariableAssignment(VHDLModel_SequentialConditionalVariableAssignment, DOMMixin):
"""
This class implements a :mod:`pyGHDL.dom` object derived from :class:`pyVHDLModel.Sequential.SequentialConditionalVariableAssignment`.
"""
[docs]
def __init__(
self,
assignmentNode: Iir,
target: VariableSymbol,
conditionalExpressions: Iterable[ConditionalExpression],
label: str = None,
) -> None:
"""
Initializes a conditional sequential variable assignment.
:param assignmentNode: The IIR node of the assignment statement.
:param target: Reference to the assignment's destination.
:param conditionalExpressions: List of all alternatives, in the order they were written.
:param label: The label of the conditional variable assignment, or ``None`` if it has none.
"""
super().__init__(target, conditionalExpressions, label)
DOMMixin.__init__(self, assignmentNode)
[docs]
@classmethod
def parse(cls, assignmentNode: Iir, label: str = None) -> "SequentialConditionalVariableAssignment":
"""
Translates the IIR node of the assignment statement to a :class:`SequentialConditionalVariableAssignment`.
:param assignmentNode: The IIR node of the assignment statement.
:param label: The statement's label, or ``None`` if it has none.
:returns: The translated assignment statement.
"""
from pyGHDL.dom._Translate import GetName
targetNode = nodes.Get_Target(assignmentNode)
targetName = VariableSymbol(targetNode, GetName(targetNode))
conditionalExpressions = GetConditionalExpressionsFromChainedNodes(
nodes.Get_Conditional_Expression_Chain(assignmentNode)
)
return cls(assignmentNode, targetName, conditionalExpressions, label)
[docs]
@export
@InheritDocString(VHDLModel_SequentialConditionalSignalAssignment, merge=True)
class SequentialConditionalSignalAssignment(VHDLModel_SequentialConditionalSignalAssignment, DOMMixin):
"""
This class implements a :mod:`pyGHDL.dom` object derived from :class:`pyVHDLModel.Sequential.SequentialConditionalSignalAssignment`.
"""
[docs]
def __init__(
self,
assignmentNode: Iir,
target: SignalSymbol,
conditionalWaveforms: Iterable,
label: str = None,
) -> None:
"""
Initializes a conditional sequential signal assignment.
:param assignmentNode: The IIR node of the assignment statement.
:param target: Reference to the assignment's destination.
:param conditionalWaveforms: All alternatives, in order.
:param label: The label of the conditional sequential signal assignment, or ``None`` if it has none.
"""
super().__init__(target, conditionalWaveforms, label)
DOMMixin.__init__(self, assignmentNode)
[docs]
@classmethod
def parse(cls, assignmentNode: Iir, label: str = None) -> "SequentialConditionalSignalAssignment":
"""
Translates the IIR node of the assignment statement to a :class:`SequentialConditionalSignalAssignment`.
:param assignmentNode: The IIR node of the assignment statement.
:param label: The statement's label, or ``None`` if it has none.
:returns: The translated assignment statement.
"""
from pyGHDL.dom._Translate import GetName
targetNode = nodes.Get_Target(assignmentNode)
targetName = SignalSymbol(targetNode, GetName(targetNode))
conditionalWaveforms = GetConditionalWaveformsFromChainedNodes(
nodes.Get_Conditional_Waveform_Chain(assignmentNode)
)
return cls(assignmentNode, targetName, conditionalWaveforms, label)
[docs]
@export
@InheritDocString(VHDLModel_SequentialSelectedVariableAssignment, merge=True)
class SequentialSelectedVariableAssignment(VHDLModel_SequentialSelectedVariableAssignment, DOMMixin):
"""
This class implements a :mod:`pyGHDL.dom` object derived from :class:`pyVHDLModel.Sequential.SequentialSelectedVariableAssignment`.
"""
[docs]
def __init__(
self,
assignmentNode: Iir,
target: VariableSymbol,
expression: ExpressionUnion,
selectedExpressions: Iterable,
label: str = None,
) -> None:
"""
Initializes a selected sequential variable assignment.
:param assignmentNode: The IIR node of the assignment statement.
:param target: Reference to the assignment's destination.
:param expression: The selector expression.
:param selectedExpressions: All alternatives, in order.
:param label: The label of the selected variable assignment, or ``None`` if it has none.
"""
super().__init__(target, expression, selectedExpressions, label)
DOMMixin.__init__(self, assignmentNode)
[docs]
@classmethod
def parse(cls, assignmentNode: Iir, label: str = None) -> "SequentialSelectedVariableAssignment":
"""
Translates the IIR node of the assignment statement to a :class:`SequentialSelectedVariableAssignment`.
:param assignmentNode: The IIR node of the assignment statement.
:param label: The statement's label, or ``None`` if it has none.
:returns: The translated assignment statement.
"""
from pyGHDL.dom._Translate import GetName, GetExpressionFromNode
targetNode = nodes.Get_Target(assignmentNode)
targetName = VariableSymbol(targetNode, GetName(targetNode))
expression = GetExpressionFromNode(nodes.Get_Expression(assignmentNode))
selectedExpressions = GetSelectedExpressionsFromChainedNodes(
nodes.Get_Selected_Expressions_Chain(assignmentNode)
)
return cls(assignmentNode, targetName, expression, selectedExpressions, label)
[docs]
@export
@InheritDocString(VHDLModel_SequentialSelectedSignalAssignment, merge=True)
class SequentialSelectedSignalAssignment(VHDLModel_SequentialSelectedSignalAssignment, DOMMixin):
"""
This class implements a :mod:`pyGHDL.dom` object derived from :class:`pyVHDLModel.Sequential.SequentialSelectedSignalAssignment`.
"""
[docs]
def __init__(
self,
assignmentNode: Iir,
target: SignalSymbol,
expression: ExpressionUnion,
selectedWaveforms: Iterable,
label: str = None,
) -> None:
"""
Initializes a selected sequential signal assignment.
:param assignmentNode: The IIR node of the assignment statement.
:param target: Reference to the assignment's destination.
:param expression: The selector expression.
:param selectedWaveforms: All alternatives, in order.
:param label: The label of the selected sequential signal assignment, or ``None`` if it has none.
"""
super().__init__(target, expression, selectedWaveforms, label)
DOMMixin.__init__(self, assignmentNode)
[docs]
@classmethod
def parse(cls, assignmentNode: Iir, label: str = None) -> "SequentialSelectedSignalAssignment":
"""
Translates the IIR node of the assignment statement to a :class:`SequentialSelectedSignalAssignment`.
:param assignmentNode: The IIR node of the assignment statement.
:param label: The statement's label, or ``None`` if it has none.
:returns: The translated assignment statement.
"""
from pyGHDL.dom._Translate import GetName, GetExpressionFromNode
targetNode = nodes.Get_Target(assignmentNode)
targetName = SignalSymbol(targetNode, GetName(targetNode))
expression = GetExpressionFromNode(nodes.Get_Expression(assignmentNode))
selectedWaveforms = GetSelectedWaveformsFromChainedNodes(nodes.Get_Selected_Waveform_Chain(assignmentNode))
return cls(assignmentNode, targetName, expression, selectedWaveforms, label)
[docs]
@export
@InheritDocString(VHDLModel_SignalForceAssignment, merge=True)
class SignalForceAssignment(VHDLModel_SignalForceAssignment, DOMMixin):
"""
This class implements a :mod:`pyGHDL.dom` object derived from :class:`pyVHDLModel.Sequential.SignalForceAssignment`.
"""
[docs]
def __init__(
self,
assignmentNode: Iir,
target: SignalSymbol,
expression: ExpressionUnion,
label: str = None,
) -> None:
"""
Initializes a signal force assignment.
:param assignmentNode: The IIR node of the assignment statement.
:param target: Reference to the assignment's destination.
:param expression: The value forced onto the signal.
:param label: The label of the signal force assignment, or ``None`` if it has none.
"""
super().__init__(target, expression, label)
DOMMixin.__init__(self, assignmentNode)
[docs]
@classmethod
def parse(cls, assignmentNode: Iir, label: str = None) -> "SignalForceAssignment":
"""
Translates the IIR node of the assignment statement to a :class:`SignalForceAssignment`.
:param assignmentNode: The IIR node of the assignment statement.
:param label: The statement's label, or ``None`` if it has none.
:returns: The translated assignment statement.
"""
from pyGHDL.dom._Translate import GetName, GetExpressionFromNode
targetNode = nodes.Get_Target(assignmentNode)
targetName = SignalSymbol(targetNode, GetName(targetNode))
expression = GetExpressionFromNode(nodes.Get_Expression(assignmentNode))
return cls(assignmentNode, targetName, expression, label)
[docs]
@export
@InheritDocString(VHDLModel_SignalReleaseAssignment, merge=True)
class SignalReleaseAssignment(VHDLModel_SignalReleaseAssignment, DOMMixin):
"""
This class implements a :mod:`pyGHDL.dom` object derived from :class:`pyVHDLModel.Sequential.SignalReleaseAssignment`.
"""
[docs]
def __init__(self, assignmentNode: Iir, target: SignalSymbol, label: str = None) -> None:
"""
Initializes a signal release assignment.
:param assignmentNode: The IIR node of the assignment statement.
:param target: Reference to the assignment's destination.
:param label: The label of the signal release assignment, or ``None`` if it has none.
"""
super().__init__(target, label)
DOMMixin.__init__(self, assignmentNode)
[docs]
@classmethod
def parse(cls, assignmentNode: Iir, label: str = None) -> "SignalReleaseAssignment":
"""
Translates the IIR node of the assignment statement to a :class:`SignalReleaseAssignment`.
:param assignmentNode: The IIR node of the assignment statement.
:param label: The statement's label, or ``None`` if it has none.
:returns: The translated assignment statement.
"""
from pyGHDL.dom._Translate import GetName
targetNode = nodes.Get_Target(assignmentNode)
targetName = SignalSymbol(targetNode, GetName(targetNode))
return cls(assignmentNode, targetName, label)
[docs]
@export
@InheritDocString(VHDLModel_SequentialProcedureCall, merge=True)
class SequentialProcedureCall(VHDLModel_SequentialProcedureCall, DOMMixin):
"""
This class implements a :mod:`pyGHDL.dom` object derived from :class:`pyVHDLModel.Sequential.SequentialProcedureCall`.
"""
[docs]
def __init__(
self,
callNode: Iir,
procedureName: Symbol,
parameterAssociationItems: Iterable[ParameterAssociationItem],
label: str = None,
) -> None:
"""
Initializes a procedure call as a sequential statement.
:param callNode: The IIR node of the subprogram call.
:param procedureName: Reference to the called procedure.
:param parameterAssociationItems: List of all parameter associations of the call.
:param label: The label of the procedure call, or ``None`` if it has none.
"""
super().__init__(procedureName, parameterAssociationItems, label)
DOMMixin.__init__(self, callNode)
[docs]
@classmethod
def parse(cls, callNode: Iir, label: str) -> "SequentialProcedureCall":
"""
Translates the IIR node of the procedure call to a :class:`SequentialProcedureCall`.
:param callNode: The IIR node of the procedure call.
:param label: The statement's label, or ``None`` if it has none.
:returns: The translated procedure call.
"""
from pyGHDL.dom._Translate import GetName, GetParameterMapAspect
cNode = nodes.Get_Procedure_Call(callNode)
prefix = nodes.Get_Prefix(cNode)
procedureName = GetName(prefix)
parameterAssociations = GetParameterMapAspect(nodes.Get_Parameter_Association_Chain(cNode))
return cls(callNode, procedureName, parameterAssociations, label)
[docs]
@export
@InheritDocString(VHDLModel_SequentialAssertStatement, merge=True)
class SequentialAssertStatement(VHDLModel_SequentialAssertStatement, DOMMixin):
"""
This class implements a :mod:`pyGHDL.dom` object derived from :class:`pyVHDLModel.Sequential.SequentialAssertStatement`.
"""
[docs]
def __init__(
self,
assertNode: Iir,
condition: ExpressionUnion,
message: ExpressionUnion = None,
severity: ExpressionUnion = None,
label: str = None,
) -> None:
"""
Initializes a sequential assertion statement.
:param assertNode: The IIR node of the assertion.
:param condition: The condition that must hold; the report is issued when it is false.
:param message: The reported message, or ``None`` if none was given.
:param severity: The reported severity level, or ``None`` if none was given.
:param label: The label of the assertion statement, or ``None`` if it has none.
"""
super().__init__(condition, message, severity, label)
DOMMixin.__init__(self, assertNode)
[docs]
@classmethod
def parse(cls, assertNode: Iir, label: str) -> "SequentialAssertStatement":
"""
Translates the IIR node of the assertion to a :class:`SequentialAssertStatement`.
:param assertNode: The IIR node of the assertion.
:param label: The statement's label, or ``None`` if it has none.
:returns: The translated assertion.
"""
from pyGHDL.dom._Translate import GetExpressionFromNode, GetOptionalExpressionFromNode
condition = GetExpressionFromNode(nodes.Get_Assertion_Condition(assertNode))
message = GetOptionalExpressionFromNode(nodes.Get_Report_Expression(assertNode))
severity = GetOptionalExpressionFromNode(nodes.Get_Severity_Expression(assertNode))
return cls(assertNode, condition, message, severity, label)
[docs]
@export
@InheritDocString(VHDLModel_SequentialReportStatement, merge=True)
class SequentialReportStatement(VHDLModel_SequentialReportStatement, DOMMixin):
"""
This class implements a :mod:`pyGHDL.dom` object derived from :class:`pyVHDLModel.Sequential.SequentialReportStatement`.
"""
[docs]
def __init__(
self,
reportNode: Iir,
message: ExpressionUnion,
severity: ExpressionUnion = None,
label: str = None,
) -> None:
"""
Initializes a sequential :vhdlkw:`report` statement.
:param reportNode: The IIR node of the :vhdlkw:`report` statement.
:param message: The reported message, or ``None`` if none was given.
:param severity: The reported severity level, or ``None`` if none was given.
:param label: The label of the :vhdlkw:`report` statement, or ``None`` if it has none.
"""
super().__init__(message, severity, label)
DOMMixin.__init__(self, reportNode)
[docs]
@classmethod
def parse(cls, reportNode: Iir, label: str) -> "SequentialReportStatement":
"""
Translates the IIR node of the :vhdlkw:`report` statement to a :class:`SequentialReportStatement`.
:param reportNode: The IIR node of the :vhdlkw:`report` statement.
:param label: The statement's label, or ``None`` if it has none.
:returns: The translated :vhdlkw:`report` statement.
"""
from pyGHDL.dom._Translate import GetExpressionFromNode, GetOptionalExpressionFromNode
message = GetExpressionFromNode(nodes.Get_Report_Expression(reportNode))
severity = GetOptionalExpressionFromNode(nodes.Get_Severity_Expression(reportNode))
return cls(reportNode, message, severity, label)
[docs]
@export
@InheritDocString(VHDLModel_ReturnStatement, merge=True)
class ReturnStatement(VHDLModel_ReturnStatement, DOMMixin):
"""
This class implements a :mod:`pyGHDL.dom` object derived from :class:`pyVHDLModel.Sequential.ReturnStatement`.
"""
[docs]
def __init__(
self,
returnNode: Iir,
returnValue: ExpressionUnion = None,
label: str = None,
) -> None:
"""
Initializes a :vhdlkw:`return` statement.
:param returnNode: The IIR node of the :vhdlkw:`return` statement.
:param returnValue: The returned expression, or ``None`` for a procedure.
:param label: The label of the :vhdlkw:`return` statement, or ``None`` if it has none.
"""
super().__init__(returnValue, label)
DOMMixin.__init__(self, returnNode)
[docs]
@classmethod
def parse(cls, returnNode: Iir, label: str) -> "ReturnStatement":
"""
Translates the IIR node of the :vhdlkw:`return` statement to a :class:`ReturnStatement`.
:param returnNode: The IIR node of the :vhdlkw:`return` statement.
:param label: The statement's label, or ``None`` if it has none.
:returns: The translated :vhdlkw:`return` statement.
"""
from pyGHDL.dom._Translate import GetOptionalExpressionFromNode
returnValue = GetOptionalExpressionFromNode(nodes.Get_Expression(returnNode))
return cls(returnNode, returnValue, label)
[docs]
@export
@InheritDocString(VHDLModel_NullStatement, merge=True)
class NullStatement(VHDLModel_NullStatement, DOMMixin):
"""
This class implements a :mod:`pyGHDL.dom` object derived from :class:`pyVHDLModel.Sequential.NullStatement`.
"""
[docs]
def __init__(
self,
waitNode: Iir,
label: str = None,
) -> None:
"""
Initializes a :vhdlkw:`null` statement.
:param waitNode: The IIR node of the :vhdlkw:`wait` statement.
:param label: The label of the :vhdlkw:`null` statement, or ``None`` if it has none.
"""
super().__init__(label)
DOMMixin.__init__(self, waitNode)
[docs]
@export
@InheritDocString(VHDLModel_NextStatement, merge=True)
class NextStatement(VHDLModel_NextStatement, DOMMixin):
"""
This class implements a :mod:`pyGHDL.dom` object derived from :class:`pyVHDLModel.Sequential.NextStatement`.
"""
[docs]
def __init__(
self,
exitNode: Iir,
condition: ExpressionUnion = None,
label: str = None,
) -> None:
"""
Initializes a :vhdlkw:`next` statement.
:param exitNode: The IIR node of the :vhdlkw:`exit` statement.
:param condition: The condition under which the iteration is skipped, or ``None`` if unconditional.
:param label: The label of the loop this statement applies to, or ``None`` for the enclosing loop.
"""
super().__init__(condition, loopLabel=label)
DOMMixin.__init__(self, exitNode)
[docs]
@classmethod
def parse(cls, exitNode: Iir, label: str) -> "NextStatement":
"""
Translates the IIR node of the exit statement to a :class:`NextStatement`.
:param exitNode: The IIR node of the exit statement.
:param label: The statement's label, or ``None`` if it has none.
:returns: The translated exit statement.
"""
from pyGHDL.dom._Translate import GetOptionalExpressionFromNode
condition = GetOptionalExpressionFromNode(nodes.Get_Condition(exitNode))
return cls(exitNode, condition, label)
[docs]
@export
@InheritDocString(VHDLModel_ExitStatement, merge=True)
class ExitStatement(VHDLModel_ExitStatement, DOMMixin):
"""
This class implements a :mod:`pyGHDL.dom` object derived from :class:`pyVHDLModel.Sequential.ExitStatement`.
"""
[docs]
def __init__(
self,
exitNode: Iir,
condition: ExpressionUnion = None,
label: str = None,
) -> None:
"""
Initializes an :vhdlkw:`exit` statement.
:param exitNode: The IIR node of the :vhdlkw:`exit` statement.
:param condition: The condition under which the loop is left, or ``None`` if unconditional.
:param label: The label of the loop this statement applies to, or ``None`` for the enclosing loop.
"""
super().__init__(condition, loopLabel=label)
DOMMixin.__init__(self, exitNode)
[docs]
@classmethod
def parse(cls, exitNode: Iir, label: str) -> "ExitStatement":
"""
Translates the IIR node of the exit statement to an :class:`ExitStatement`.
:param exitNode: The IIR node of the exit statement.
:param label: The statement's label, or ``None`` if it has none.
:returns: The translated exit statement.
"""
from pyGHDL.dom._Translate import GetOptionalExpressionFromNode
condition = GetOptionalExpressionFromNode(nodes.Get_Condition(exitNode))
return cls(exitNode, condition, label)
[docs]
@export
@InheritDocString(VHDLModel_WaitStatement, merge=True)
class WaitStatement(VHDLModel_WaitStatement, DOMMixin):
"""
This class implements a :mod:`pyGHDL.dom` object derived from :class:`pyVHDLModel.Sequential.WaitStatement`.
"""
[docs]
def __init__(
self,
waitNode: Iir,
sensitivityList: Iterable[Symbol] = None,
condition: ExpressionUnion = None,
timeout: ExpressionUnion = None,
label: str = None,
) -> None:
"""
Initializes a :vhdlkw:`wait` statement.
:param waitNode: The IIR node of the :vhdlkw:`wait` statement.
:param sensitivityList: List of all signal names of the :vhdlkw:`on` clause, or ``None`` if none was given.
:param condition: The condition of the :vhdlkw:`until` clause, or ``None`` if none was given.
:param timeout: The timeout expression of the :vhdlkw:`for` clause, or ``None`` if none was given.
:param label: The label of the :vhdlkw:`wait` statement, or ``None`` if it has none.
"""
super().__init__(sensitivityList, condition, timeout, label)
DOMMixin.__init__(self, waitNode)
[docs]
@classmethod
def parse(cls, waitNode: Iir, label: str) -> "WaitStatement":
"""
Translates the IIR node of the :vhdlkw:`wait` statement to a :class:`WaitStatement`.
:param waitNode: The IIR node of the :vhdlkw:`wait` statement.
:param label: The statement's label, or ``None`` if it has none.
:returns: The translated :vhdlkw:`wait` statement.
"""
from pyGHDL.dom._Utils import GetIirKindOfNode
from pyGHDL.dom._Translate import GetOptionalExpressionFromNode
sensitivityList = None
sensitivityListNode = nodes.Get_Sensitivity_List(waitNode)
if sensitivityListNode is not nodes.Null_Iir:
pass
# print(f"WaitStatement: wait on {GetIirKindOfNode(sensitivityListNode)}")
condition = GetOptionalExpressionFromNode(nodes.Get_Condition_Clause(waitNode))
timeout = GetOptionalExpressionFromNode(nodes.Get_Timeout_Clause(waitNode))
return cls(waitNode, sensitivityList, condition, timeout, label)