As explained in What is GHDL?, GHDL is a compiler which translates VHDL files to machine code. Hence, the regular workflow is composed of three steps:
Analysis [-a]: convert design units (VHDL sources) to an internal representation.
Elaboration [-e]: generate executable machine code for a target module (top-level entity).
Run [-r]: execute the design to test the behaviour, generate output/waveforms, etc.
The following tips might be useful:
--ieee=synopsysif your design depends on a non-standard implementation of the IEEE library.
-frelaxed-rulesif needed. For instance, if you would like to use VHDL 2008 and also use shared variables with an ordinary type (deprecated in VHDL 2000), you can use
Use the same options for analysis and elaboration. E.g., first analyse with
ghdl -a --std=08 --work=mylib myfile.vhdl; and then elaborate and run with
ghdl --elab-run --std=08 top.
Due to the fact that VHDL is processed as a general purpose language (instead of an HDL), all the language features are to be supported. I.e., VHDL sources do not need to be limited to the synthesisable subset. However, distinction between synthesisable and non-synthesisable (simulation-only) subsets is often misleading for users who are new to the language. Different examples are provided, in the hope of helping understand the different use cases: