This is experimental and work in progress! If you find crashes or unsupported features, please report them!

Since v0.37, GHDL features a built-in (experimental) synthesis kernel with two backends: synth and yosys-plugin. Currently, synthesis is supported as a front-end of other synthesis and technology mapping tools. Hence, the netlists generated by GHDL are not optimised.

Synthesis [--synth]#

This command is useful for checking that a design can be synthesized, before actually running a complete synthesis tool. In fact, because this is expected to be much faster, it can be used as a frequent check.

Moreover, since GHDL’s front-end supports multiple versions of the standard, but the synthesised netlists are generated using a subset of VHDL 1993, GHDL’s synthesis features can be used as a preprocessor with tools that do support older versions of the standard, but which don’t provide the most recent features.

Currently, the default output is a generic netlist using a (very simple) subset of VHDL 1993. See --out and #1174 for on-going discussion about other output formats.

--synth <[options...] [library.]top_unit [arch]>#

Elaborates for synthesis the design whose top unit is indicated by [library.]top_unit [arch].


All the units must have been analyzed; that is, the artifacts of previously executed -a calls must exist.

--synth <[options...] file... -e [top_unit [arch]]>#

Analyses and elaborates for synthesis the files present on the command line only. Elaboration starts from the top unit indicated by [top_unit [arch]]. If no top unit is specified, GHDL will try guessing it and a note will be printed.


Files can be provided in any order, but -e must be provided after them. That is, --synth <[options...] files...> is NOT supported. This is because we want to unambiguously tell files and the unit specification apart. We don’t want to rely on parsing the items and guessing whether we are dealing with files or a top unit name. In corner cases, a filename might exist which matches the name of a primary unit: ghdl synth name.

Synthesis options#


Multiple pragmas are supported for preventing blocks of code from being synthesized:

-- pragma|synopsys|synthesis (synthesis|translate)( |_)(on|off)

For example:

  • -- pragma translate off

  • -- synthesis translate_on

  • -- synopsys synthesis_off

Due to GHDL’s modular architecture (see Overview), the synthesis kernel shares the VHDL parsing front-end with the simulation back-ends. Hence, available options for synthesis are the same as for analysis and/or simulation elaboration (see Options). In addition to those options, there are some synthesis specific options.


Furthermore there are lot of debug options available. Beware: these debug options should only used for debugging purposes as they aren’t guaranteed to be stable during development of GHDL’s synthesis feature. You can find them in the file ghdlsynth.adb in the procedure Decode_Option().


Override top unit generic NAME with value VALUE. Similar to the run-time option -gGENERIC.


$ ghdl --synth --std=08 -gDEPTH=12 [library.]top_unit [arch]
  • vhdl (default): equivalent to raw-vhdl, but the original top-level unit is preserved unmodified, so the synthesized design can be simulated with the same testbench.

  • raw-vhdl: all statements are converted to a simple VHDL 1993 netlist, for allowing instantiation in other synthesis tools without modern VHDL support.

  • verilog: generate a verilog netlist.

  • dot: generate a graphviz dot diagram of the netlist AST.

  • none: perform the synthesis, but do not generate any output; useful for frequent checks.

  • raw: print the internal representation of the design, for debugging purposes.

  • dump: similar to raw, with even more internal details for debugging.


Any unit from library NAME is a black box.


$ ghdl --synth --std=08 --vendor-library=vendorlib [library.]top_unit [arch]

Assertions, PSL and formal verification#


Neither synthesize assert nor PSL.


$ ghdl --synth --std=08 --no-formal [library.]top_unit [arch]

Disable automatic cover PSL assertion activation. If this option isn’t used, GHDL generates cover directives for each assert directive (with an implication operator) automatically during synthesis.


$ ghdl --synth --std=08 --no-assert-cover [library.]top_unit [arch]

Treat all PSL asserts like PSL assumes. If this option is used, GHDL generates an assume directive for each assert directive during synthesis. This is similar to the -assert-assumes option of Yosys’ read_verilog command.


$ ghdl --synth --std=08 --assert-assumes [library.]top_unit [arch]

As all PSL asserts are treated like PSL assumes, no cover directives are automatically generated for them, regardless of using the --no-assert-cover or not.


Treat all PSL assumes like PSL asserts. If this option is used, GHDL generates an assert directive for each assume directive during synthesis. This is similar to the -assume-asserts option of Yosys’ read_verilog command.


$ ghdl --synth --std=08 --assume-asserts [library.]top_unit [arch]

cover directives are automatically generated for the resulting asserts (with an implication operator) if --no-assert-cover isn’t used.

Yosys plugin#

ghdl-yosys-plugin is a module to use GHDL as a VHDL front-end for Yosys Open Synthesis Suite, a framework for optimised synthesis and technology mapping. Artifacts generated by Yosys can be used in multiple open source and vendor tools to achieve P&R, formal verification, etc. A relevant feature of combining GHDL and Yosys is that mixed-language (VHDL-Verilog) synthesis with open source tools is possible.

The command line syntax for this plugin is the same as for --synth, except that the command name (--synth) is neither required nor supported. Instead, yosys, yosys -m ghdl or yosys -m path/to/ need to be used, depending of how is the plugin built. See ghdl/ghdl-yosys-plugin: README for building and installation guidelines.


ghdl-yosys-plugin is a thin layer that converts the internal representation of --synth to Yosys’ C API. Hence, it is suggested to check the designs with --synth before running synthesis with Yosys.

Convert (V)HDL to other formats#

Yosys provides write_* commands for generating output netlists in different formats. Therefore, VHDL and/or Verilog sources can be converted to EDIF, SMT, BTOR2, etc.


For a comprehensive list of supported output formats (AIGER, BLIF, ILANG, JSON…), check out the Yosys documentation.

To Verilog#

yosys -m ghdl -p 'ghdl filename.vhdl -e top_unit [arch]; write_verilog filename.v'


yosys -m ghdl -p 'ghdl filename.vhdl -e top_unit [arch]; write_edif filename.edif'


yosys -m ghdl -p 'ghdl filename.vhdl -e top_unit [arch]; write_smt2 filename.smt2'


yosys -m ghdl -p 'ghdl filename.vhdl -e top_unit [arch]; write_btor filename.btor'


yosys -m ghdl -p 'ghdl filename.vhdl -e top_unit [arch]; write_firrtl filename.firrtl'


There is work in progress in ghdl/ghdl-yosys-plugin#122 for adding a write_vhdl command to Yosys. That is the complement of what ghdl-yosys-plugin provides.