pyGHDL.dom.NonStandard

This module implements the non-standard classes Design, Library and Document.

These three are not VHDL language constructs, but the entry points of pyGHDL.dom: a document reads and parses a source file through libghdl, a library groups documents, and a design owns the libraries.

Classes

Design: A Design represents set of VHDL libraries as well as all loaded and analysed source files (see Document).
Library: A Library represents a VHDL library. It contains all primary and secondary design units.
Document: A Document represents a sourcefile. It contains primary and secondary design units.

Classes

class pyGHDL.dom.NonStandard.Design(name=None, vhdlVersion=2008)[source]

A Design represents set of VHDL libraries as well as all loaded and analysed source files (see Document).

It’s the root of this code document-object-model (CodeDOM). It contains at least one VHDL library (see Library). When the design is analysed (see Analyze()), multiple graph data structures will be created and populated with vertices and edges. As a first result, the design’s compile order and hierarchy can be iterated. As a second result, the design’s top-level is identified and referenced from the design (see TopLevel).

The design contains references to the following graphs:

DependencyGraph
CompileOrderGraph
HierarchyGraph
ObjectGraph

This class implements a pyGHDL.dom object derived from pyVHDLModel.Design.

Inheritance

Parameters:

name (str)
vhdlVersion (<pyTooling.Decorators.readonly object at 0x7d2df0d61e50>)

_SUPPORTED_VHDL_VERSIONS = (2008, 2019): VHDL versions currently supported by this class. Older revisions (87, 93, 2000, 2002) are not planned to be supported for now.

_VHDL_VERSION_TO_STD_OPTION = {2008: '08', 2019: '19'}: Mapping from a supported VHDLVersion to GHDL’s ‘–std=’ option value.

__init__(name=None, vhdlVersion=2008)[source]

Initialize a VHDL design.

Parameters:

name (str) – Name of the design.
vhdlVersion (readonly) – The VHDL version used to analyze this design.

Return type:

None

_vhdlVersion: <pyTooling.Decorators.readonly object at 0x7d2df0d61e50>: The VHDL version this design is analyzed with.

_loadDefaultLibraryTime: float | None: LoadDefaultLibraries() duration in seconds, None if unused.

_analyzeTime: float | None: Analyze() duration in seconds, None if not called.

_warnings: List: Warnings collected from libghdl while the design’s documents are analyzed.

property VHDLVersion: <pyTooling.Decorators.readonly object at 0x7d2df0d61e50>

Read-only property to access the VHDL version this design is analyzed with (_vhdlVersion).

The version is checked against _SUPPORTED_VHDL_VERSIONS when the design is created and is translated to GHDL’s --std= option value via _VHDL_VERSION_TO_STD_OPTION.

Returns:: The design’s VHDL version.

__ghdl_init(): Initialization: set options and then load libraries.

LoadDefaultLibraries(flavor=None)[source]

Loads the std and ieee libraries into the design.

How long this took is measured and kept in _loadDefaultLibraryTime.

Parameters:: flavor (IEEEFlavor | None) – The IEEE library flavor to load, or None for the default.

Analyze()[source]

Analyzes all documents of this design.

How long this took is measured and kept in _analyzeTime, and the warnings libghdl raised during the analysis are collected in _warnings.

AddDocument(document, library)[source]

Add a document (VHDL source file) to the design and register all embedded design units to the given VHDL library.

Algorithm

Iterate all entities in the document
1. Check if entity name might exist in target library.
2. Add entity to library and update library membership.
Iterate all architectures in the document
1. Check if architecture name might exist in target library.
2. Add architecture to library and update library membership.
Iterate all packages in the document
1. Check if package name might exist in target library.
2. Add package to library and update library membership.
Iterate all package bodies in the document
1. Check if package body name might exist in target library.
2. Add package body to library and update library membership.
Iterate all configurations in the document
1. Check if configuration name might exist in target library.
2. Add configuration to library and update library membership.
Iterate all contexts in the document
1. Check if context name might exist in target library.
2. Add context to library and update library membership.

Parameters:

document (Document) – The VHDL source code file.
library (Library) – The VHDL library used to register the embedded design units to.

Raises:

LibraryNotRegisteredError – If the given VHDL library is not a library in the design.
EntityExistsInLibraryError – If the processed entity’s name is already existing in the VHDL library.
ArchitectureExistsInLibraryError – If the processed architecture’s name is already existing in the VHDL library.
PackageExistsInLibraryError – If the processed package’s name is already existing in the VHDL library.
PackageBodyExistsError – If the processed package body’s name is already existing in the VHDL library.
ConfigurationExistsInLibraryError – If the processed configuration’s name is already existing in the VHDL library.
ContextExistsInLibraryError – If the processed context’s name is already existing in the VHDL library.

Return type:

None

AddLibrary(library)[source]

Add a VHDL library to the design.

Ensure the libraries name doesn’t collide with existing libraries in the design.
If ok, set the libraries parent reference to the design.

Parameters:

library (Library) – Library object to loaded.

Raises:

LibraryExistsInDesignError – If the library already exists in the design.
LibraryRegisteredToForeignDesignError – If library is already used by a different design.

Return type:

None

property AllowBlackbox: bool

Property to return whether a design supports blackboxes, inherited from the parent if not set locally (_allowBlackbox).

Algorithm

If allow blackbox property is locally set, return the local value,
Otherwise, return allow blackbox value from parent object.

Returns:: True, if blackboxes are allowed.
Raises:: VHDLModelException – If neither a local value is set nor a parent object is available to inherit the value from.

AnalyzeDependencies()[source]

Analyze the dependencies of design units.

Return type:: None

Algorithm

Create all vertices of the dependency graph by iterating all design units in all libraries.
→ CreateDependencyGraph()
Create the compile order graph.
→ CreateCompileOrderGraph()
Index all packages.
→ IndexPackages()
Index all architectures.
→ IndexArchitectures()
Link all contexts
→ LinkContexts()
Link all architectures.
→ LinkArchitectures()
Link all package bodies.
→ LinkPackageBodies()
Link all package instances.
→ LinkPackageInstances()
Link all library references.
→ LinkLibraryReferences()
Link all package references.
→ LinkPackageReferences()
Link all context references.
→ LinkContextReferences()
Link all components.
→ LinkComponents()
Link all instantiations.
→ LinkInstantiations()
Create the hierarchy graph.
→ CreateHierarchyGraph()
Compute the compile order.
→ ComputeCompileOrder()

AnalyzeObjects()[source]

Analyze the dependencies of types and objects.

Return type:: None

Algorithm

Index all entities.
→ IndexEntities()
Index all package bodies.
→ IndexPackageBodies()
Import objects.
→ ImportObjects()
Create the type and object graph.
→ CreateTypeAndObjectGraph()

property CompileOrderGraph: Graph

Read-only property to access the compile-order graph (_compileOrderGraph).

Returns:: Reference to the compile-order graph.

CreateCompileOrderGraph()[source]

Create a compile-order graph with bidirectional references to the dependency graph.

Add vertices representing a document (VHDL source file) to the dependency graph. Each “document” vertex in dependency graph is copied into the compile-order graph and bidirectionally referenced.

In addition, each vertex of a corresponding design unit in a document is linked to the vertex representing that document to express the design unit in document relationship.

Each added vertex has the following properties:

The vertex’ ID is the document’s filename.
The vertex’ value references the document.
A key-value-pair called kind denotes the vertex’s kind as an enumeration value of type DependencyGraphVertexKind.
A key-value-pair called predefined does not exist.

Algorithm

Iterate all documents in the design.
- Create a vertex for that document and reference the document by the vertex’ value field.
  In return, set the documents’s _dependencyVertex field to reference the created vertex.
- Copy the vertex from dependency graph to compile-order graph and link both vertices bidirectionally.
  In addition, set the documents’s _dependencyVertex field to reference the copied vertex.
  - Add a key-value-pair called compileOrderVertex to the dependency graph’s vertex.
  - Add a key-value-pair called dependencyVertex to the compiler-order graph’s vertex.
1. Iterate the documents design units and create an edge from the design unit’s corresponding dependency vertex to the documents corresponding dependency vertex. This expresses a “design unit is located in document” relation.
  - Add a key-value-pair called kind` denoting the edge’s kind as an enumeration value of type DependencyGraphEdgeKind.

Return type:: None

CreateDependencyGraph()[source]

Create all vertices of the dependency graph by iterating all design units in all libraries.

This method will purely create a sea of vertices without any linking between vertices. The edges will be created later by other methods.
See AnalyzeDependencies() for these methods and their algorithmic order.

Each vertex has the following properties:

The vertex’ ID is the design unit’s identifier.
The vertex’ value references the design unit.
A key-value-pair called kind denotes the vertex’s kind as an enumeration value of type DependencyGraphVertexKind.
A key-value-pair called predefined denotes if the referenced design unit is a predefined language entity.

Algorithm

Iterate all libraries in the design.
- Create a vertex for that library and reference the library by the vertex’ value field.
  In return, set the library’s _dependencyVertex field to reference the created vertex.
1. Iterate all contexts in that library.
  - Create a vertex for that context and reference the context by the vertex’ value field.
    In return, set the context’s _dependencyVertex field to reference the created vertex.
2. Iterate all packages in that library.
  - Create a vertex for that package and reference the package by the vertex’ value field.
    In return, set the package’s _dependencyVertex field to reference the created vertex.
3. Iterate all package bodies in that library.
  - Create a vertex for that package body and reference the package body by the vertex’ value field.
    In return, set the package body’s _dependencyVertex field to reference the created vertex.
4. Iterate all entities in that library.
  - Create a vertex for that entity and reference the entity by the vertex’ value field.
    In return, set the entity’s _dependencyVertex field to reference the created vertex.
5. Iterate all architectures in that library.
  - Create a vertex for that architecture and reference the architecture by the vertex’ value field.
    In return, set the architecture’s _dependencyVertex field to reference the created vertex.
6. Iterate all configurations in that library.
  - Create a vertex for that configuration and reference the configuration by the vertex’ value field.
    In return, set the configuration’s _dependencyVertex field to reference the created vertex.

Return type:: None

CreateHierarchyGraph()[source]

Create the hierarchy graph from dependency graph.

Return type:: None

Algorithm

Iterate all vertices corresponding to entities and architectures in the dependency graph:
- Copy these vertices to the hierarchy graph and create a bidirectional linking.
  In addition, set the referenced design unit’s _hierarchyVertex field to reference the copied vertex.
  - Add a key-value-pair called hierarchyVertex to the dependency graph’s vertex.
  - Add a key-value-pair called dependencyVertex to the hierarchy graph’s vertex.
Iterate all architectures …

Todo

Design::CreateHierarchyGraph describe algorithm
1. Iterate all outbound edges
  
  Todo
  
  Design::CreateHierarchyGraph describe algorithm

property DependencyGraph: Graph

Read-only property to access the dependency graph (_dependencyGraph).

Returns:: Reference to the dependency graph.

property Documents: List[Document]

Read-only property to access the list of all documents (VHDL source files) loaded for this design (_documents).

Returns:: A list of all documents.

GetAncestor(type)

Return the closest ancestor of the given type found by walking the parent chain upwards.

Iterates the parent chain - starting at this model entity - upwards (toward the root of the model) until an ancestor of the requested type is found.

Parameters:: type (Type) – Class (type) of the ancestor to find.
Return type:: ModelEntity
Returns:: The closest ancestor of the requested type.
Raises:: VHDLModelException – If the root of the model is reached without finding an ancestor of the requested type.

GetLibrary(libraryName)[source]

Return an (existing) VHDL library object of name libraryName.

If the requested VHDL library doesn’t exist, a new VHDL library with that name will be created.

Parameters:: libraryName (str) – Name of the requested VHDL library.
Return type:: Library
Returns:: The VHDL library object.

classmethod GetMethodsWithAttributes(predicate: TAttr | Iterable[TAttr] | None = None) → Dict[Callable, Tuple[Attribute, ...]]

Parameters:

predicate (TypeVar(TAttr) | Iterable[TypeVar(TAttr)] | None) – An attribute class, an iterable of attribute classes, or None to accept every attribute.

Return type:

Dict[Callable, Tuple[Attribute, ...]]

Returns:

Dictionary of methods and the matching attributes attached to them.

Raises:

ValueError – If an element of parameter ‘predicate’ is not a sub-class of Attribute.
ValueError – If parameter ‘predicate’ is neither an attribute class nor an iterable of those.

property HierarchyGraph: Graph

Read-only property to access the hierarchy graph (_hierarchyGraph).

Returns:: Reference to the hierarchy graph.

IndexArchitectures()[source]

Index all declared items in all packages in all libraries.

Return type:: None

Algorithm

Iterate all libraries:
1. Iterate all packages
  → pyVHDLModel.Library.IndexArchitectures()
  - Index all declared items in that architecture.
    → pyVHDLModel.DesignUnit.Architecture.IndexDeclaredItems()

See also

IndexPackages(): Index all declared items in all packages in all libraries.
IndexPackageBodies(): Index all declared items in all package bodies in all libraries.
IndexEntities(): Index all declared items in all entities in all libraries.

IndexEntities()[source]

Index all declared items in all packages in all libraries.

Return type:: None

Algorithm

Iterate all libraries:
1. Iterate all packages
  → pyVHDLModel.Library.IndexEntities()
  - Index all declared items in that entity.
    → pyVHDLModel.DesignUnit.Entity.IndexDeclaredItems()

See also

IndexPackages(): Index all declared items in all packages in all libraries.
IndexPackageBodies(): Index all declared items in all package bodies in all libraries.
IndexArchitectures(): Index all declared items in all architectures in all libraries.

IndexPackageBodies()[source]

Index all declared items in all packages in all libraries.

Return type:: None

Algorithm

Iterate all libraries:
1. Iterate all packages
  → pyVHDLModel.Library.IndexPackageBodies()
  - Index all declared items in that package body.
    → pyVHDLModel.DesignUnit.PackageBody.IndexDeclaredItems()

See also

IndexPackages(): Index all declared items in all packages in all libraries.
IndexEntities(): Index all declared items in all entities in all libraries.
IndexArchitectures(): Index all declared items in all architectures in all libraries.

IndexPackages()[source]

Index all declared items in all packages in all libraries.

Return type:: None

Algorithm

Iterate all libraries:
1. Iterate all packages
  → pyVHDLModel.Library.IndexPackages()
  - Index all declared items in that package.
    → pyVHDLModel.DesignUnit.Package.IndexDeclaredItems()

See also

IndexPackageBodies(): Index all declared items in all package bodies in all libraries.
IndexEntities(): Index all declared items in all entities in all libraries.
IndexArchitectures(): Index all declared items in all architectures in all libraries.

IterateDesignUnits(filter=<DesignUnitKind.All: 63>)[source]

Iterate all design units in the design.

A union of DesignUnitKind values can be given to filter the returned result for suitable design units.

Algorithm

Iterate all VHDL libraries.
1. Iterate all contexts in that library.
2. Iterate all packages in that library.
3. Iterate all package bodies in that library.
4. Iterate all entites in that library.
5. Iterate all architectures in that library.
6. Iterate all configurations in that library.

Parameters:: filter (DesignUnitKind) – An enumeration with possibly multiple flags to filter the returned design units.
Return type:: Generator[DesignUnit, None, None]
Returns:: A generator to iterate all matched design units in the design.

See also

pyVHDLModel.Library.IterateDesignUnits(): Iterate all design units in the library.
pyVHDLModel.Document.IterateDesignUnits(): Iterate all design units in the document.

IterateDocumentsInCompileOrder()[source]

Iterate all document in compile-order.

Algorithm

Check if compile-order graph was populated with vertices and its vertices are linked by edges.

Iterate compile-order graph in topological order.
pyTooling.Graph.Graph.IterateTopologically()
- yield the compiler-order vertex’ referenced document.

Return type:: Generator[Document, None, None]
Returns:: A generator to iterate all documents in compile-order in the design.
Raises:: VHDLModelException – If compile-order was not computed.

See also

Todo

missing text

pyVHDLModel.Design.ComputeCompileOrder()

property Libraries: Dict[str, Library]

Read-only property to access the dictionary of library names and VHDL libraries (_libraries).

Returns:: A dictionary of library names and VHDL libraries.

LinkArchitectures()[source]

Link all architectures to corresponding entities in all libraries.

Return type:: None

Algorithm

Iterate all libraries:
1. Iterate all architecture groups (grouped per entity symbol’s name). → pyVHDLModel.Library.LinkArchitectures()
  - Check if entity symbol’s name exists as an entity in this library.
  1. For each architecture in the same architecture group:
    - Add architecture to entities architecture dictionary pyVHDLModel.DesignUnit.Entity._architectures.
    - Assign found entity to architecture’s entity symbol pyVHDLModel.DesignUnit.Architecture._entity
    - Set parent namespace of architecture’s namespace to the entitie’s namespace.
    - Add an edge in the dependency graph from the architecture’s corresponding dependency vertex to the entity’s corresponding dependency vertex.

See also

LinkPackageBodies(): Link all package bodies to corresponding packages in all libraries.
LinkPackageInstances(): Link all package instances to corresponding generic packages in all libraries.

LinkComponents()[source]

Link components to matching entities found in same VHDL library.

Return type:: None

Algorithm

Iterate all design units with component declarations (packages and architectures):
1. Iterate all component declarations in a package or architecture:
  - Check if an entity with matching name can be found in the VHDL library the package is declared within. If found, set the component’s entity reference to that entity, otherwise check if blackboxes are allowed for that component. If so, mark the component as a blackbox, otherwise, raise an exception.
2. Iterate concurrent statements with declaration regions (block statements, generate statements) if the design unit is an architecture:
  - If the statement is an IfGenerateStatement:
    1. Iterate declared components in the IfGenerateBranch.
    2. Iterate declared components in each ElIfGenerateBranch.
    3. Iterate declared components in the ElseGenerateBranch if it exists.
  - If the statement is an ForGenerateStatement:
    1. Iterate declared components.
  - If the statement is an CaseGenerateStatement:
    1. Iterate declared components.
    2. Iterate

See also

LinkInstantiations(): Link instantiations to components and entities.
AnalyzeDependencies(): Analyze dependencies in a design (calls this method).

LinkContextReferences()[source]

Link all context references (context clause) to the matching context.

Return type:: None

Algorithm

Iterate all design units:
- Iterate all context references in the design unit:
  - Iterate each context symbol within the context reference.
    1. Get the library identifier from the symbol.
    2. Get the context identifier from the symbol.
    3. Resolve library:
      - If library name is work, get library from design unit.
      - If library name is not in design unit’s _referencedLibraries, raise an exception.
      - Otherwise, lookup library by name in design.
    4. Resolve context:
      - Lookup context by name in library.
    5. Update design unit:
      - Update the context symbol’s target with the referenced context.
      - Add an entry in the design unit’s _referencedContexts dictionary referencing the referenced context.
      - Add an edge in the dependency graph from design unit to the referenced context.
Iterate all context vertices in the dependency graph (_dependencyGraph) in topological order:
- Get the context from the context vertex.
- Iterate all predecessor vertices (design unit vertices) of the context vertex:
  1. Get the design unit from design unit vertex.
  2. Iterate referenced libraries of the context:
    - Add an entry in the design unit’s _referencedLibraries dictionary referencing the referenced library.
    - Add an empty dictionary in the design unit’s _referencedPackages dictionary.
  3. Iterate referenced packages of the context:
    - Raise an exception if package name is already listed in _referencedPackages.
    - Add an entry in the design unit’s _referencedPackages dictionary referencing the referenced package.

See also

LinkLibraryReferences(): Link library clause.
LinkPackageReferences(): Link use clause.
AnalyzeDependencies(): Analyze dependencies and link relations.

LinkContexts()[source]

Resolves and links all items (library clauses, use clauses and nested context references) in contexts.

It iterates all contexts in the design. Therefore, the library of the context is used as the working library. By default, the working library is implicitly referenced in _referencedLibraries. In addition, a new empty dictionary is created in _referencedPackages and _referencedContexts for that working library.

At first, all library clauses are resolved (a library clause my have multiple library reference symbols). For each referenced library an entry in _referencedLibraries is generated and new empty dictionaries in _referencedPackages and _referencedContexts for that working library. In addition, a vertex in the dependency graph is added for that relationship.

At second, all use clauses are resolved (a use clause my have multiple package member reference symbols). For each referenced package,

Return type:: None

LinkLibraryReferences()[source]

Link all library references (library clause) to the matching VHDL library.

Return type:: None

Algorithm

Iterate all design units with contexts:
- If the design unit is a primary unit:
  1. Iterate all library identifiers in DEFAULT_LIBRARIES (std):
    - Get the referenced library by name from the design.
    - Add an entry in the design unit’s _referencedLibraries dictionary referencing the referenced library.
    - Add an empty dictionary in the design unit’s _referencedPackages dictionary.
    - Add an empty dictionary in the design unit’s _referencedContexts dictionary.
    - Add an edge in the dependency graph from design unit to the referenced library.
  2. Get the design unit’s library:
    - Add an entry in the design unit’s _referencedLibraries dictionary referencing the referenced library.
    - Add an empty dictionary in the design unit’s _referencedPackages dictionary.
    - Add an empty dictionary in the design unit’s _referencedContexts dictionary.
    - Add an edge in the dependency graph from design unit to the referenced library.
- If the design unit is a secondary unit:
  - If design unit is an architecture, get the corresponding entity’s referenced libraries.
  - If design unit is a package body, get the corresponding package’s referenced libraries.
  - Otherwise, raise an exception
  For every referenced library create new dictionary entries in the design unit’s _referencedLibraries.
Iterate every library reference (library clause) in the design unit:
- Iterate every library symbol within the library reference:
  - Get the library identifier from the symbol.
  - Continue the inner loop, if identifier is work.
  - Get the referenced library from the design or raise an exception.
  - Update the library symbol’s target with the referenced library.
  - Add an entry in the design unit’s _referencedLibraries dictionary referencing the referenced library.
  - Add an empty dictionary in the design unit’s _referencedPackages dictionary.
  - Add an empty dictionary in the design unit’s _referencedContexts dictionary.
  - Add an edge in the dependency graph from design unit to the referenced library.

See also

LinkPackageReferences(): Link use clause.
LinkContextReferences(): Link context clause.
AnalyzeDependencies(): Analyze dependencies and link relations.

LinkPackageBodies()[source]

Link all package bodies to corresponding packages in all libraries.

Return type:: None

Algorithm

Iterate all libraries:
1. Iterate all package bodies. → pyVHDLModel.Library.LinkPackageBodies()
  - Check if package body symbol’s name exists as a package in this library.
  - Add package body to package pyVHDLModel.DesignUnit.Package._packageBody.
  - Assign found package to package body’s package symbol pyVHDLModel.DesignUnit.PackageBody._package
  - Set parent namespace of package body’s namespace to the package’s namespace.
  - Add an edge in the dependency graph from the package body’s corresponding dependency vertex to the package’s corresponding dependency vertex.

See also

LinkArchitectures(): Link all architectures to corresponding entities in all libraries.
LinkPackageInstances(): Link all package instances to corresponding generic packages in all libraries.

LinkPackageInstances()[source]

Return type:

None

Link all package instances to corresponding generic packages in all libraries.

Algorithm

Iterate all libraries:
1. Iterate all package instances. → pyVHDLModel.Library.LinkPackageInstances()

Todo

Check if package instance’s symbol’s name exists as a generic package in this library.

Add generic package to package instance pyVHDLModel.DesignUnit.Package._packageBody.

Assign found package to package body’s package symbol pyVHDLModel.DesignUnit.PackageBody._package

Set parent namespace of package body’s namespace to the package’s namespace.

Add an edge in the dependency graph from the package body’s corresponding dependency vertex to the package’s corresponding dependency vertex.

See also

LinkArchitectures(): Link all architectures to corresponding entities in all libraries.
LinkPackageBodies(): Link all package bodies to corresponding packages in all libraries.

LinkPackageReferences()[source]

Link all package references (use clause) to the matching packages.

Return type:: None

Algorithm

Iterate all design units with contexts:
- If the design unit is a primary unit:
  - If primary unit isn’t package std.standard:
    1. Iterate all library, packages tuples in DEFAULT_PACKAGES (std: [standard]):
      - Raise an exception, if library isn’t listed in design unit’s _referencedLibraries.
      - For every package in packages:
        
        Get the referenced package by library name and package name from the design.
        
        Add an entry in the design unit’s _referencedPackages dictionary referencing the referenced package.
        
        Add an edge in the dependency graph from design unit to the referenced package.
- If the design unit is a secondary unit:
  - If design unit is an architecture, get the corresponding entity’s referenced packages.
  - If design unit is a package body, get the corresponding package’s referenced packages.
  - Otherwise, raise an exception
  For every referenced package create new dictionary entries in the design unit’s _referencedPackages.
Iterate every package reference (use clause) in the design unit:
- Iterate every package symbol within the package reference:
  1. Get the library identifier from the symbol.
  2. Get the package identifier from the symbol.
  3. Resolve library:
    - If library name is work, get library from design unit.
    - If library name is not in design unit’s _referencedLibraries, raise an exception.
    - Otherwise, lookup library by name in design.
  4. Resolve package:
    - Lookup package by name in library.
  5. Update design unit:
    - Update the package symbol’s target with the referenced package.
    - Add an entry in the design unit’s _referencedPackages dictionary referencing the referenced package.
    - Add an edge in the dependency graph from design unit to the referenced package.
  6. Import public package members.
    - If package symbol is a AllPackageMembersReferenceSymbol:
      - Iterate all components within the referenced package and add entries for each component in the design unit’s _namespace.
      Todo
      
      Other elements are not implemented.
    - If package symbol is a PackageMemberReferenceSymbol
      
      Todo
      
      Not implemented.
    - Otherwise, raise an exception.

See also

LinkLibraryReferences(): Link library clause.
LinkContextReferences(): Link context clause.
AnalyzeDependencies(): Analyze dependencies and link relations.

LoadIEEELibrary(flavor=None)[source]

Load the predefined VHDL library ieee into the design.

This will create a virtual source code file ieee.vhdl and register VHDL design units of library ieee to that file.

Parameters:: flavor (IEEEFlavor | None) – Select the IEEE library flavor: IEEE, Synopsys, MentorGraphics.
Return type:: Library
Returns:: The library object of library ieee.

LoadStdLibrary()[source]

Load the predefined VHDL library std into the design.

This will create a virtual source code file std.vhdl and register VHDL design units of library std to that file.

Return type:: Library
Returns:: The library object of library std.

property Name: str | None

Read-only property to access the design’s name (_name).

Returns:: The name of the design.

property ObjectGraph: Graph

Read-only property to access the object graph (_objectGraph).

Returns:: Reference to the object graph.

property Parent: ModelEntity

Property to access the model entity’s parent element reference in a logical hierarchy (_parent).

Returns:: Reference to the parent entity.

property TopLevel: Entity | Configuration

Read-only property to access the design’s top-level (_toplevel).

When called the first time, the hierarchy graph is checked for its root elements. When there is only one root element in the graph, a new field toplevel is added to _hierarchyGraph referencing that single element. In addition, the result is cached in _toplevel.

Returns:

Reference to the design’s top-level.

Raises:

VHDLModelException – If the hierarchy graph is not yet computed from dependency graph.
VHDLModelException – If there is more than one top-level.

__getstate__() → Dict[str, Any]

Helper for pickle.

Return type:: Dict[str, Any]

__repr__()[source]

Formats a representation of the design.

Format: Document: 'my_design'

Return type:: str
Returns:: String representation of the design.

__str__()

Formats a representation of the design.

Format: Document: 'my_design'

Return type:: str
Returns:: String representation of the design.

_allowBlackbox: bool: Allow blackboxes after linking the design.

_compileOrderGraph: Graph[None, None, None, None, None, None, None, None, None, Document, None, None, None, None, None, None, None, None, None, None, None, None, None]: A graph derived from dependency graph containing the order of documents for compilation.

_dependencyGraph: Graph[None, None, None, None, None, None, None, None, str, DesignUnit, None, None, None, None, None, None, None, None, None, None, None, None, None]: The graph of all dependencies in the designs.

_documents: List[Document]: List of all documents loaded for a design.

_hierarchyGraph: Graph[None, None, None, None, None, None, None, None, str, DesignUnit, None, None, None, None, None, None, None, None, None, None, None, None, None]: A graph derived from dependency graph containing the design hierarchy.

_libraries: Dict[str, Library]: List of all libraries defined for a design.

_name: str | None: Name of the design.

_objectGraph: Graph[None, None, None, None, None, None, None, None, str, Obj, None, None, None, None, None, None, None, None, None, None, None, None, None]: The graph of all types and objects in the design.

_parent: ModelEntity: Reference to a parent entity in the logical model hierarchy.

_toplevel: Entity | Configuration: When computed, the toplevel design unit is cached in this field.

class pyGHDL.dom.NonStandard.Library(identifier, documentation=None, allowBlackbox=None, parent=None)[source]

A Library represents a VHDL library. It contains all primary and secondary design units.

See also

Predefined library

This class implements a pyGHDL.dom object derived from pyVHDLModel.Library.

Inheritance

Parameters:

identifier (str)
documentation (str | None)
allowBlackbox (bool | None)
parent (ModelEntity | None)

property AllowBlackbox: bool

Property to return whether a design supports blackboxes, inherited from the parent if not set locally (_allowBlackbox).

Algorithm

If allow blackbox property is locally set, return the local value,
Otherwise, return allow blackbox value from parent object.

Returns:: True, if blackboxes are allowed.
Raises:: VHDLModelException – If neither a local value is set nor a parent object is available to inherit the value from.

property Architectures: Dict[str, Dict[str, Architecture]]

Read-only property to access the dictionary of all architecture declarations in this library (_architectures).

Returns:: Dictionary of all architectures, indexed by normalized entity identifier, then by normalized architecture identifier.

property Configurations: Dict[str, Configuration]

Read-only property to access the dictionary of all configuration declarations in this library (_configurations).

Returns:: Dictionary of all configurations, indexed by normalized identifier.

property Contexts: Dict[str, Context]

Read-only property to access the dictionary of all context declarations in this library (_contexts).

Returns:: Dictionary of all contexts, indexed by normalized identifier.

property DependencyVertex: Vertex

Read-only property to access the corresponding dependency vertex (_dependencyVertex).

The dependency vertex references this library by its value field.

Returns:: The corresponding dependency vertex.

property Documentation: str | None

Property to access the library’s documentation (_documentation).

Hint

Unlike every other documented entity, a library’s documentation cannot come from VHDL source: the language has no library declaration to attach a comment to. It is therefore settable, so a caller can supply one from elsewhere - a compile-order file, a project description, …

Returns:: Associated documentation of this VHDL library.

property Entities: Dict[str, Entity]

Read-only property to access the dictionary of all entity declarations in this library (_entities).

Returns:: Dictionary of all entities, indexed by normalized identifier.

GetAncestor(type)

Return the closest ancestor of the given type found by walking the parent chain upwards.

Iterates the parent chain - starting at this model entity - upwards (toward the root of the model) until an ancestor of the requested type is found.

Parameters:: type (Type) – Class (type) of the ancestor to find.
Return type:: ModelEntity
Returns:: The closest ancestor of the requested type.
Raises:: VHDLModelException – If the root of the model is reached without finding an ancestor of the requested type.

classmethod GetMethodsWithAttributes(predicate: TAttr | Iterable[TAttr] | None = None) → Dict[Callable, Tuple[Attribute, ...]]

Parameters:

predicate (TypeVar(TAttr) | Iterable[TypeVar(TAttr)] | None) – An attribute class, an iterable of attribute classes, or None to accept every attribute.

Return type:

Dict[Callable, Tuple[Attribute, ...]]

Returns:

Dictionary of methods and the matching attributes attached to them.

Raises:

ValueError – If an element of parameter ‘predicate’ is not a sub-class of Attribute.
ValueError – If parameter ‘predicate’ is neither an attribute class nor an iterable of those.

property Identifier: str

Read-only property to access the model entity’s identifier (_identifier).

Returns:: Name of a model entity.

IndexArchitectures()[source]

Index declared items in all architectures.

Return type:: None

Algorithm

Iterate all architectures:
- Index all declared items.
  → pyVHDLModel.DesignUnit.Architecture.IndexDeclaredItems()

See also

IndexPackages(): Index all declared items in a package.
IndexPackageBodies(): Index all declared items in a package body.
IndexEntities(): Index all declared items in an entity.

IndexEntities()[source]

Index declared items in all entities.

Return type:: None

Algorithm

Iterate all entities:
- Index all declared items.
  → pyVHDLModel.DesignUnit.Entity.IndexDeclaredItems()

See also

IndexPackages(): Index all declared items in a package.
IndexPackageBodies(): Index all declared items in a package body.
IndexArchitectures(): Index all declared items in an architecture.

IndexPackageBodies()[source]

Index declared items in all package bodies.

Return type:: None

Algorithm

Iterate all package bodies:
- Index all declared items.
  → pyVHDLModel.DesignUnit.PackageBody.IndexDeclaredItems()

See also

IndexPackages(): Index all declared items in a package.
IndexEntities(): Index all declared items in an entity.
IndexArchitectures(): Index all declared items in an architecture.

IndexPackages()[source]

Index declared items in all packages.

Return type:: None

Algorithm

Iterate all packages:
- Index all declared items.
  → pyVHDLModel.DesignUnit.Package.IndexDeclaredItems()

See also

IndexPackageBodies(): Index all declared items in a package body.
IndexEntities(): Index all declared items in an entity.
IndexArchitectures(): Index all declared items in an architecture.

IterateDesignUnits(filter=<DesignUnitKind.All: 63>)[source]

Iterate all design units in the library.

A union of DesignUnitKind values can be given to filter the returned result for suitable design units.

Algorithm

Iterate all contexts in that library.
Iterate all packages in that library.
Iterate all package bodies in that library.
Iterate all entities in that library.
Iterate all architectures in that library.
Iterate all configurations in that library.

Parameters:: filter (DesignUnitKind) – An enumeration with possibly multiple flags to filter the returned design units.
Return type:: Generator[DesignUnit, None, None]
Returns:: A generator to iterate all matched design units in the library.

See also

pyVHDLModel.Design.IterateDesignUnits(): Iterate all design units in the design.
pyVHDLModel.Document.IterateDesignUnits(): Iterate all design units in the document.

LinkArchitectures()[source]

Link all architectures to corresponding entities.

Return type:: None

Algorithm

Iterate all architecture groups (grouped per entity symbol’s name).
- Check if entity symbol’s name exists as an entity in this library.
1. For each architecture in the same architecture group:
  - Add architecture to entities architecture dictionary pyVHDLModel.DesignUnit.Entity._architectures.
  - Assign found entity to architecture’s entity symbol pyVHDLModel.DesignUnit.Architecture._entity
  - Set parent namespace of architecture’s namespace to the entitie’s namespace.
  - Add an edge in the dependency graph from the architecture’s corresponding dependency vertex to the entity’s corresponding dependency vertex.

Raises:

VHDLModelException – If entity name doesn’t exist.
VHDLModelException – If architecture name already exists for entity.

Return type:

None

See also

LinkPackageBodies(): Link all package bodies to corresponding packages.
LinkPackageInstances(): Link all package instances to corresponding generic packages.

LinkPackageBodies()[source]

Link all package bodies to corresponding packages.

Return type:: None

Algorithm

Iterate all package bodies.
- Check if package body symbol’s name exists as a package in this library.
- Add package body to package pyVHDLModel.DesignUnit.Package._packageBody.
- Assign found package to package body’s package symbol pyVHDLModel.DesignUnit.PackageBody._package
- Set parent namespace of package body’s namespace to the package’s namespace.
- Add an edge in the dependency graph from the package body’s corresponding dependency vertex to the package’s corresponding dependency vertex.

Raises:: VHDLModelException – If package name doesn’t exist.
Return type:: None

See also

LinkArchitectures(): Link all architectures to corresponding entities.
LinkPackageInstances(): Link all package instances to corresponding generic packages.

LinkPackageInstances()[source]

Link all package instances to corresponding generic packages.

Return type:: None

Algorithm

Iterate all package instances.
Todo
- Check if package body symbol’s name exists as a package in this library.
- Add package body to package pyVHDLModel.DesignUnit.Package._packageBody.
- Assign found package to package body’s package symbol pyVHDLModel.DesignUnit.PackageBody._package
- Set parent namespace of package body’s namespace to the package’s namespace.
- Add an edge in the dependency graph from the package body’s corresponding dependency vertex to the package’s corresponding dependency vertex.

Raises:: VHDLModelException – If generic package name doesn’t exist.
Return type:: None

See also

LinkArchitectures(): Link all architectures to corresponding entities.
LinkPackageBodies(): Link all package bodies to corresponding packages.

property NormalizedIdentifier: str

Read-only property to access the model entity’s normalized identifier (_normalizedIdentifier).

Returns:: Normalized name of a model entity.

property PackageBodies: Dict[str, PackageBody]

Read-only property to access the dictionary of all package body declarations in this library (_packageBodies).

Returns:: Dictionary of all package bodies, indexed by normalized identifier.

property Packages: Dict[str, Package]

Read-only property to access the dictionary of all package declarations in this library (_packages).

Returns:: Dictionary of all packages, indexed by normalized identifier.

property Parent: ModelEntity

Property to access the model entity’s parent element reference in a logical hierarchy (_parent).

Returns:: Reference to the parent entity.

__getstate__() → Dict[str, Any]

Helper for pickle.

Return type:: Dict[str, Any]

__init__(identifier, documentation=None, allowBlackbox=None, parent=None)[source]

Initialize a VHDL library.

Parameters:

identifier (str) – Name of the VHDL library.
documentation (str | None) – Documentation of this VHDL library, if the caller has one to supply.
allowBlackbox (bool | None) – Specify if blackboxes are allowed in this design.
parent (ModelEntity | None) – The parent model entity (design) of this VHDL library.

Return type:

None

__repr__()[source]

Formats a representation of the library.

Format: Library: 'my_library'

Return type:: str
Returns:: String representation of the library.

__str__()

Formats a representation of the library.

Format: Library: 'my_library'

Return type:: str
Returns:: String representation of the library.

_allowBlackbox: bool | None: Allow blackboxes for components in this library.

_architectures: Dict[str, Dict[str, Architecture]]: Dictionary of all architectures defined in a library.

_configurations: Dict[str, Configuration]: Dictionary of all configurations defined in a library.

_contexts: Dict[str, Context]: Dictionary of all contexts defined in a library.

_dependencyVertex: Vertex[None, None, str, Library | DesignUnit, None, None, None, None, None, None, None, None, None, None, None, None, None]: Reference to the vertex in the dependency graph representing the library.
This reference is set by CreateDependencyGraph().

_documentation: str | None: The associated documentation of a model entity.

_entities: Dict[str, Entity]: Dictionary of all entities defined in a library.

_identifier: str: The identifier of a model entity.

_normalizedIdentifier: str: The normalized (lower case) identifier of a model entity.

_packageBodies: Dict[str, PackageBody]: Dictionary of all package bodies defined in a library.

_packages: Dict[str, Package]: Dictionary of all packages defined in a library.

_parent: ModelEntity: Reference to a parent entity in the logical model hierarchy.

class pyGHDL.dom.NonStandard.Document(path, sourceCode=None, vhdlVersion=2008, dontParse=False, dontTranslate=False)[source]

A Document represents a sourcefile. It contains primary and secondary design units.

This class implements a pyGHDL.dom object derived from pyVHDLModel.Document.

Inheritance

Parameters:

path (Path)
sourceCode (str)
vhdlVersion (VHDLVersion)
dontParse (bool)
dontTranslate (bool)

__ghdlFileID: Any: libghdl’s name table identifier for _filename.

__ghdlSourceFileEntry: Any: libghdl’s source file entry holding this document’s source code.

__init__(path, sourceCode=None, vhdlVersion=2008, dontParse=False, dontTranslate=False)[source]

Initializes a VHDL document.

Parameters:

path (Path) – Path to the document. None if in-memory document.
sourceCode (str) – The source code to analyze, or None to read it from path.
vhdlVersion (VHDLVersion) – VHDL version used for analyzing this source file.
dontParse (bool) – True to skip parsing the source code.
dontTranslate (bool) – True to parse the source code, but skip translating it to the DOM.

Return type:

None

_filename: Path: The source file this document was read from.

_warnings: List: Warnings collected from libghdl while this document is translated.

property Architectures: Dict[str, Dict[str, Architecture]]

Read-only property to access the dictionary of all architecture declarations in this document (_architectures).

Returns:: Dictionary of all architectures, indexed by normalized entity identifier, then by normalized architecture identifier.

property CompileOrderVertex: Vertex[None, None, None, Document, None, None, None, None, None, None, None, None, None, None, None, None, None]

Read-only property to access the corresponding compile-order vertex (_compileOrderVertex).

The compile-order vertex references this document by its value field.

Returns:: The corresponding compile-order vertex.

property Configurations: Dict[str, Configuration]

Read-only property to access the dictionary of all configuration declarations in this document (_configurations).

Returns:: Dictionary of all configurations, indexed by normalized identifier.

property Contexts: Dict[str, Context]

Read-only property to access the dictionary of all context declarations in this document (_contexts).

Returns:: Dictionary of all contexts, indexed by normalized identifier.

property DesignUnits: List[DesignUnit]

Read-only property to access a list of all design units declarations found in this document (_designUnits).

Returns:: List of all design units.

property Documentation: str | None

Read-only property to access the model entity’s documentation (_documentation).

Returns:: Associated documentation of a model entity.

property Entities: Dict[str, Entity]

Read-only property to access the dictionary of all entity declarations in this document (_entities).

Returns:: Dictionary of all entities, indexed by normalized identifier.

GetAncestor(type)

Return the closest ancestor of the given type found by walking the parent chain upwards.

Iterates the parent chain - starting at this model entity - upwards (toward the root of the model) until an ancestor of the requested type is found.

Parameters:: type (Type) – Class (type) of the ancestor to find.
Return type:: ModelEntity
Returns:: The closest ancestor of the requested type.
Raises:: VHDLModelException – If the root of the model is reached without finding an ancestor of the requested type.

classmethod GetMethodsWithAttributes(predicate: TAttr | Iterable[TAttr] | None = None) → Dict[Callable, Tuple[Attribute, ...]]

Parameters:

predicate (TypeVar(TAttr) | Iterable[TypeVar(TAttr)] | None) – An attribute class, an iterable of attribute classes, or None to accept every attribute.

Return type:

Dict[Callable, Tuple[Attribute, ...]]

Returns:

Dictionary of methods and the matching attributes attached to them.

Raises:

ValueError – If an element of parameter ‘predicate’ is not a sub-class of Attribute.
ValueError – If parameter ‘predicate’ is neither an attribute class nor an iterable of those.

IterateDesignUnits(filter=<DesignUnitKind.All: 63>)[source]

Iterate all design units in the document.

A union of DesignUnitKind values can be given to filter the returned result for suitable design units.

Algorithm

If contexts are selected in the filter:
1. Iterate all contexts in that library.
If packages are selected in the filter:
1. Iterate all packages in that library.
If package bodies are selected in the filter:
1. Iterate all package bodies in that library.
If entites are selected in the filter:
1. Iterate all entites in that library.
If architectures are selected in the filter:
1. Iterate all architectures in that library.
If configurations are selected in the filter:
1. Iterate all configurations in that library.

Parameters:: filter (DesignUnitKind) – An enumeration with possibly multiple flags to filter the returned design units.
Return type:: Generator[DesignUnit, None, None]
Returns:: A generator to iterate all matched design units in the document.

See also

pyVHDLModel.Design.IterateDesignUnits(): Iterate all design units in the design.
pyVHDLModel.Library.IterateDesignUnits(): Iterate all design units in the library.

property Library: <pyTooling.Decorators.readonly object at 0x7d2df0f761d0>

Read-only property to access the document’s VHDL library (_library).

Returns:: VHDL library used to analyze the VHDL file’s design units into.

property PackageBodies: Dict[str, PackageBody]

Read-only property to access the dictionary of all package body declarations in this document (_packageBodies).

Returns:: Dictionary of all package bodies, indexed by normalized identifier.

property Packages: Dict[str, Package]

Read-only property to access the dictionary of all package declarations in this document (_packages).

Returns:: Dictionary of all packages, indexed by normalized identifier.

property Parent: ModelEntity

Property to access the model entity’s parent element reference in a logical hierarchy (_parent).

Returns:: Reference to the parent entity.

property Path: <pyTooling.Decorators.readonly object at 0x7d2df0f760d0>

Read-only property to access the document’s path (_path).

Returns:: The path of this document.

property VHDLVersion: <pyTooling.Decorators.readonly object at 0x7d2df0f76150>

Read-only property to access the document’s VHDL version (_vhdlVersion).

Returns:: VHDL version used to analyze this VHDL file.

property VerificationModes: Dict[str, VerificationMode]

Read-only property to access the dictionary of all verification mode declarations in this document (_verificationModes).

Returns:: Dictionary of all verification mode declarations, indexed by normalized identifier.

property VerificationProperties: Dict[str, VerificationProperty]

Read-only property to access the dictionary of all verification property declarations in this document (_verificationProperties).

Returns:: Dictionary of all verification properties, indexed by normalized identifier.

property VerificationUnits: Dict[str, VerificationUnit]

Read-only property to access the dictionary of all verification unit declarations in this document (_verificationUnits).

Returns:: Dictionary of all verification units, indexed by normalized identifier.

_AddArchitecture(item)[source]

Add an architecture to the document’s lists of design units.

Parameters:

item (Architecture) – Architecture object to be added to the document.

Raises:

TypeError – If parameter ‘item’ is not of type Architecture.
VHDLModelException – If architecture name already exists for the referenced entity name in document.

Return type:

None

_AddConfiguration(item)[source]

Add a configuration to the document’s lists of design units.

Parameters:

item (Configuration) – Configuration object to be added to the document.

Raises:

TypeError – If parameter ‘item’ is not of type Configuration.
VHDLModelException – If configuration name already exists in document.

Return type:

None

_AddContext(item)[source]

Add a context to the document’s lists of design units.

Parameters:

item (Context) – Context object to be added to the document.

Raises:

TypeError – If parameter ‘item’ is not of type Context.
VHDLModelException – If context name already exists in document.

Return type:

None

_AddDesignUnit(item)[source]

Add a design unit to the document’s lists of design units.

Parameters:

item (DesignUnit) – Configuration object to be added to the document.

Raises:

TypeError – If parameter ‘item’ is not of type DesignUnit.
ValueError – If parameter ‘item’ is an unknown DesignUnit.
VHDLModelException – If configuration name already exists in document.

Return type:

None

_AddEntity(item)[source]

Add an entity to the document’s lists of design units.

Parameters:

item (Entity) – Entity object to be added to the document.

Raises:

TypeError – If parameter ‘item’ is not of type Entity.
VHDLModelException – If entity name already exists in document.

Return type:

None

_AddPackage(item)[source]

Add a package to the document’s lists of design units.

Parameters:

item (Package) – Package object to be added to the document.

Raises:

TypeError – If parameter ‘item’ is not of type Package.
VHDLModelException – If package name already exists in document.

Return type:

None

_AddPackageBody(item)[source]

Add a package body to the document’s lists of design units.

Parameters:

item (PackageBody) – Package body object to be added to the document.

Raises:

TypeError – If parameter ‘item’ is not of type PackageBody.
VHDLModelException – If package body name already exists in document.

Return type:

None

__getstate__() → Dict[str, Any]

Helper for pickle.

Return type:: Dict[str, Any]

__repr__()[source]

Formats a representation of the document.

Format: Document: 'path/to/file.vhdl'

Return type:: str
Returns:: String representation of the document.

__str__()

Formats a representation of the document.

Format: Document: 'path/to/file.vhdl'

Return type:: str
Returns:: String representation of the document.

_architectures: Dict[str, Dict[str, Architecture]]: Dictionary of all architectures defined in a document.

_compileOrderVertex: Vertex[None, None, None, Document, None, None, None, None, None, None, None, None, None, None, None, None, None]: Reference to the vertex in the compile-order graph representing the document.
This reference is set by CreateCompileOrderGraph().

_configurations: Dict[str, Configuration]: Dictionary of all configurations defined in a document.

_contexts: Dict[str, Context]: Dictionary of all contexts defined in a document.

_dependencyVertex: Vertex[None, None, None, Document, None, None, None, None, None, None, None, None, None, None, None, None, None]: Reference to the vertex in the dependency graph representing the document.
This reference is set by CreateCompileOrderGraph().

_designUnits: List[DesignUnit]: List of all design units defined in a document.

_documentation: str | None: The associated documentation of a model entity.

_entities: Dict[str, Entity]: Dictionary of all entities defined in a document.

_library: <pyTooling.Decorators.readonly object at 0x7d2df0f761d0>: VHDL library used for analyzing the source file’s content into.

_packageBodies: Dict[str, PackageBody]: Dictionary of all package bodies defined in a document.

_packages: Dict[str, Package]: Dictionary of all packages defined in a document.

_parent: ModelEntity: Reference to a parent entity in the logical model hierarchy.

_path: <pyTooling.Decorators.readonly object at 0x7d2df0f760d0>: Path to the document. None if in-memory document.

_verificationModes: Dict[str, VerificationMode]: Dictionary of all PSL verification modes defined in a document.

_verificationProperties: Dict[str, VerificationProperty]: Dictionary of all PSL verification properties defined in a document.

_verificationUnits: Dict[str, VerificationUnit]: Dictionary of all PSL verification units defined in a document.

_vhdlVersion: <pyTooling.Decorators.readonly object at 0x7d2df0f76150>: VHDL version used for analyzing this source file.

__ghdlFile: Any: The IIR design file node returned by libghdl when the source code was parsed.

__ghdlProcessingTime: float: Duration of libghdl’s parsing in seconds, unset if dontParse was True.

__domTranslateTime: float: Duration of the IIR to DOM translation in seconds, unset if it was skipped.

__loadFromPath()

Reads the source file named by _filename and hands it to libghdl.

Raises:: DOMException – If the source file does not exist.

__loadFromString(sourceCode)

Hands the given source code to libghdl under the name in _filename.

Hint

The source file itself is not read, which is how a document can be analyzed in-memory from a string.

Parameters:: sourceCode (str) – The source code to analyze.

translate()[source]

Translates the design units of the parsed IIR tree to pyGHDL.dom objects.

Raises:: DOMException – If a design unit’s kind is not handled.

property LibGHDLProcessingTime: float

Read-only property to access the time libghdl spent parsing this document (__ghdlProcessingTime).

The duration is measured while the document is constructed, so it is set only if dontParse was False.

Returns:: The parse duration in seconds.
Raises:: AttributeError – If the document was constructed with dontParse=True.

property DOMTranslationTime: float

Read-only property to access the time spent translating the IIR tree to the DOM (__domTranslateTime).

The duration is measured while the document is constructed, so it is set only if neither dontParse nor dontTranslate was True.

Returns:: The translation duration in seconds.
Raises:: AttributeError – If the document was constructed with dontParse=True or dontTranslate=True.