Selected Element

The diagrams below draw one box per node kind, with one port per field. The edge colours say how a link is held; they are listed in full on the Fields page.

Iir_Kind_Selected_Element

A record element selection. This corresponds to a refined selected names. The production doesn’t exist in the VHDL grammar.

Format: Short

Accessor	Field	Type	Access	Description
Prefix	`Field0`	`Iir`	owned	Prefix of a name.
Type	`Field1`	`Iir`	ref	—
Identifier	`Field3`	`Name_Id`	owned	Get/Set the identifier of a declaration. Can also be used instead of get/set_label.
Named_Entity	`Field4`	`Iir`	maybe forward ref	The selected element.
Base_Name	`Field5`	`Iir`	ref	The base name of a name is the node at the origin of the name. The base name is a declaration (signal, object, constant or interface), a selected_by_all name, an implicit_dereference name.
Expr_Staticness	`State1`	`Iir_Staticness`	owned	Expression staticness, defined by rules of LRM 7.4
Name_Staticness	`State2`	`Iir_Staticness`	owned	Staticness of a name, according to rules of LRM 6.1
Is_Forward_Ref	`Flag1`	`Boolean`	owned	Always false.