# =============================================================================
# ____ _ _ ____ _ _
# _ __ _ _ / ___| | | | _ \| | __| | ___ _ __ ___
# | '_ \| | | | | _| |_| | | | | | / _` |/ _ \| '_ ` _ \
# | |_) | |_| | |_| | _ | |_| | |___ | (_| | (_) | | | | | |
# | .__/ \__, |\____|_| |_|____/|_____(_)__,_|\___/|_| |_| |_|
# |_| |___/
# =============================================================================
# Authors:
# Patrick Lehmann
#
# Package module: DOM: Concurrent statements.
#
# License:
# ============================================================================
# Copyright (C) 2019-2021 Tristan Gingold
#
# This program is free software: you can redistribute it and/or modify
# it under the terms of the GNU General Public License as published by
# the Free Software Foundation, either version 2 of the License, or
# (at your option) any later version.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
# You should have received a copy of the GNU General Public License
# along with this program. If not, see <gnu.org/licenses>.
#
# SPDX-License-Identifier: GPL-2.0-or-later
# ============================================================================
"""
This module implements derived concurrent statement classes from :mod:`pyVHDLModel.Concurrent`.
"""
from typing import Iterable, List, Optional as Nullable
from pyTooling.Decorators import export, InheritDocString
from pyVHDLModel.Base import ExpressionUnion, WaveformElement as VHDLModel_WaveformElement, ModelEntity, Range
from pyVHDLModel.Common import (
ConditionalWaveform as VHDLModel_ConditionalWaveform,
SelectedWaveform as VHDLModel_SelectedWaveform,
OthersSelectedWaveform as VHDLModel_OthersSelectedWaveform,
)
from pyVHDLModel.Symbol import Symbol
from pyVHDLModel.Association import (
AssociationItem,
GenericAssociationItem as VHDLModel_GenericAssociationItem,
PortAssociationItem as VHDLModel_PortAssociationItem,
ParameterAssociationItem as VHDLModel_ParameterAssociationItem,
)
from pyVHDLModel.Sequential import SequentialStatement
from pyVHDLModel.Concurrent import (
ComponentInstantiation as VHDLModel_ComponentInstantiation,
EntityInstantiation as VHDLModel_EntityInstantiation,
ConfigurationInstantiation as VHDLModel_ConfigurationInstantiation,
ProcessStatement as VHDLModel_ProcessStatement,
ConcurrentProcedureCall as VHDLModel_ConcurrentProcedureCall,
ConcurrentBlockStatement as VHDLModel_ConcurrentBlockStatement,
IfGenerateBranch as VHDLModel_IfGenerateBranch,
ElsifGenerateBranch as VHDLModel_ElsifGenerateBranch,
ElseGenerateBranch as VHDLModel_ElseGenerateBranch,
IfGenerateStatement as VHDLModel_IfGenerateStatement,
ConcurrentChoice,
ConcurrentCase,
CaseGenerateStatement as VHDLModel_CaseGenerateStatement,
ForGenerateStatement as VHDLModel_ForGenerateStatement,
ConcurrentSimpleSignalAssignment as VHDLModel_ConcurrentSimpleSignalAssignment,
ConcurrentConditionalSignalAssignment as VHDLModel_ConcurrentConditionalSignalAssignment,
ConcurrentSelectedSignalAssignment as VHDLModel_ConcurrentSelectedSignalAssignment,
ConcurrentAssertStatement as VHDLModel_ConcurrentAssertStatement,
ConcurrentStatement,
GenerateCase as VHDLModel_GenerateCase,
OthersGenerateCase as VHDLModel_OthersGenerateCase,
IndexedGenerateChoice as VHDLModel_IndexedGenerateChoice,
RangedGenerateChoice as VHDLModel_RangedGenerateChoice,
)
from pyGHDL.libghdl import Iir, utils
from pyGHDL.libghdl.vhdl import nodes
from pyGHDL.dom import DOMMixin, DOMException, Position
from pyGHDL.dom._Utils import GetLabelOfNode
from pyGHDL.dom.Symbol import (
ArchitectureSymbol,
EntityInstantiationSymbol,
ComponentInstantiationSymbol,
ConfigurationInstantiationSymbol,
SignalSymbol,
)
[docs]
@export
@InheritDocString(VHDLModel_GenericAssociationItem, merge=True)
class GenericAssociationItem(VHDLModel_GenericAssociationItem, DOMMixin):
"""
This class implements a :mod:`pyGHDL.dom` object derived from :class:`pyVHDLModel.Association.GenericAssociationItem`.
"""
[docs]
def __init__(self, associationNode: Iir, formal: Symbol, actual: ExpressionUnion) -> None:
"""
Initializes a generic association item.
:param associationNode: The IIR node of the association element.
:param formal: Reference to the formal part, or ``None`` for a positional association.
:param actual: The actual part of this association.
"""
super().__init__(formal, actual)
DOMMixin.__init__(self, associationNode)
[docs]
@export
@InheritDocString(VHDLModel_PortAssociationItem, merge=True)
class PortAssociationItem(VHDLModel_PortAssociationItem, DOMMixin):
"""
This class implements a :mod:`pyGHDL.dom` object derived from :class:`pyVHDLModel.Association.PortAssociationItem`.
"""
[docs]
def __init__(self, associationNode: Iir, formal: Symbol, actual: ExpressionUnion) -> None:
"""
Initializes a port association item.
:param associationNode: The IIR node of the association element.
:param formal: Reference to the formal part, or ``None`` for a positional association.
:param actual: The actual part of this association.
"""
super().__init__(formal, actual)
DOMMixin.__init__(self, associationNode)
[docs]
@export
@InheritDocString(VHDLModel_ParameterAssociationItem, merge=True)
class ParameterAssociationItem(VHDLModel_ParameterAssociationItem, DOMMixin):
"""
This class implements a :mod:`pyGHDL.dom` object derived from :class:`pyVHDLModel.Association.ParameterAssociationItem`.
"""
[docs]
def __init__(self, associationNode: Iir, formal: Symbol, actual: ExpressionUnion) -> None:
"""
Initializes a parameter association item.
:param associationNode: The IIR node of the association element.
:param formal: Reference to the formal part, or ``None`` for a positional association.
:param actual: The actual part of this association.
"""
super().__init__(formal, actual)
DOMMixin.__init__(self, associationNode)
[docs]
@export
@InheritDocString(VHDLModel_ComponentInstantiation, merge=True)
class ComponentInstantiation(VHDLModel_ComponentInstantiation, DOMMixin):
"""
This class implements a :mod:`pyGHDL.dom` object derived from :class:`pyVHDLModel.Concurrent.ComponentInstantiation`.
"""
[docs]
def __init__(
self,
instantiationNode: Iir,
label: str,
componentSymbol: ComponentInstantiationSymbol,
genericAssociationItems: Iterable[AssociationItem] = None,
portAssociationItems: Iterable[AssociationItem] = None,
) -> None:
"""
Initializes a component instantiation.
:param instantiationNode: The IIR node of the instantiation statement.
:param label: The label of the component instantiation statement.
:param componentSymbol: Reference to the instantiated component.
:param genericAssociationItems: List of all generic associations in the generic map aspect.
:param portAssociationItems: List of all port associations in the port map aspect.
"""
super().__init__(label, componentSymbol, genericAssociationItems, portAssociationItems)
DOMMixin.__init__(self, instantiationNode)
[docs]
@classmethod
def parse(cls, instantiationNode: Iir, instantiatedUnit: Iir, label: str) -> "ComponentInstantiation":
"""
Translates the IIR node of the instantiation statement to a :class:`ComponentInstantiation`.
:param instantiationNode: The IIR node of the instantiation statement.
:param instantiatedUnit: The IIR node of the instantiated unit.
:param label: The statement's label, or ``None`` if it has none.
:returns: The translated instantiation statement.
"""
from pyGHDL.dom._Translate import GetName, GetGenericMapAspect, GetPortMapAspect
componentSymbol = ComponentInstantiationSymbol(instantiatedUnit, GetName(instantiatedUnit))
genericAssociationItems = GetGenericMapAspect(nodes.Get_Generic_Map_Aspect_Chain(instantiationNode))
portAssociationItems = GetPortMapAspect(nodes.Get_Port_Map_Aspect_Chain(instantiationNode))
return cls(instantiationNode, label, componentSymbol, genericAssociationItems, portAssociationItems)
[docs]
@export
@InheritDocString(VHDLModel_EntityInstantiation, merge=True)
class EntityInstantiation(VHDLModel_EntityInstantiation, DOMMixin):
"""
This class implements a :mod:`pyGHDL.dom` object derived from :class:`pyVHDLModel.Concurrent.EntityInstantiation`.
"""
[docs]
def __init__(
self,
instantiationNode: Iir,
label: str,
entitySymbol: EntityInstantiationSymbol,
architectureSymbol: ArchitectureSymbol = None, # TODO: merge both symbols ?
genericAssociationItems: Iterable[AssociationItem] = None,
portAssociationItems: Iterable[AssociationItem] = None,
) -> None:
"""
Initializes a direct entity instantiation.
:param instantiationNode: The IIR node of the instantiation statement.
:param label: The label of the entity instantiation statement.
:param entitySymbol: Reference to the directly instantiated entity.
:param architectureSymbol: Reference to the selected architecture, if one was given.
:param genericAssociationItems: List of all generic associations in the generic map aspect.
:param portAssociationItems: List of all port associations in the port map aspect.
"""
super().__init__(label, entitySymbol, architectureSymbol, genericAssociationItems, portAssociationItems)
DOMMixin.__init__(self, instantiationNode)
[docs]
@classmethod
def parse(cls, instantiationNode: Iir, instantiatedUnit: Iir, label: str) -> "EntityInstantiation":
"""
Translates the IIR node of the instantiation statement to an :class:`EntityInstantiation`.
:param instantiationNode: The IIR node of the instantiation statement.
:param instantiatedUnit: The IIR node of the instantiated unit.
:param label: The statement's label, or ``None`` if it has none.
:returns: The translated instantiation statement.
"""
from pyGHDL.dom._Translate import GetName, GetGenericMapAspect, GetPortMapAspect
entityName = nodes.Get_Entity_Name(instantiatedUnit)
entitySymbol = EntityInstantiationSymbol(entityName, GetName(entityName))
architectureSymbol = None
architectureId = nodes.Get_Architecture(instantiatedUnit)
if architectureId != nodes.Null_Iir:
architectureSymbol = ArchitectureSymbol(GetName(architectureId), entitySymbol)
genericAssociationItems = GetGenericMapAspect(nodes.Get_Generic_Map_Aspect_Chain(instantiationNode))
portAssociationItems = GetPortMapAspect(nodes.Get_Port_Map_Aspect_Chain(instantiationNode))
return cls(
instantiationNode, label, entitySymbol, architectureSymbol, genericAssociationItems, portAssociationItems
)
[docs]
@export
@InheritDocString(VHDLModel_ConfigurationInstantiation, merge=True)
class ConfigurationInstantiation(VHDLModel_ConfigurationInstantiation, DOMMixin):
"""
This class implements a :mod:`pyGHDL.dom` object derived from :class:`pyVHDLModel.Concurrent.ConfigurationInstantiation`.
"""
[docs]
def __init__(
self,
instantiationNode: Iir,
label: str,
configurationSymbol: ConfigurationInstantiationSymbol,
genericAssociationItems: Iterable[AssociationItem] = None,
portAssociationItems: Iterable[AssociationItem] = None,
) -> None:
"""
Initializes a configuration instantiation.
:param instantiationNode: The IIR node of the instantiation statement.
:param label: The label of the configuration instantiation statement.
:param configurationSymbol: Reference to the instantiated configuration.
:param genericAssociationItems: List of all generic associations in the generic map aspect.
:param portAssociationItems: List of all port associations in the port map aspect.
"""
super().__init__(label, configurationSymbol, genericAssociationItems, portAssociationItems)
DOMMixin.__init__(self, instantiationNode)
[docs]
@classmethod
def parse(cls, instantiationNode: Iir, instantiatedUnit: Iir, label: str) -> "ConfigurationInstantiation":
"""
Translates the IIR node of the instantiation statement to a :class:`ConfigurationInstantiation`.
:param instantiationNode: The IIR node of the instantiation statement.
:param instantiatedUnit: The IIR node of the instantiated unit.
:param label: The statement's label, or ``None`` if it has none.
:returns: The translated instantiation statement.
"""
from pyGHDL.dom._Translate import GetName, GetGenericMapAspect, GetPortMapAspect
configurationName = nodes.Get_Configuration_Name(instantiatedUnit)
configurationSymbol = ConfigurationInstantiationSymbol(configurationName, GetName(configurationName))
genericAssociationItems = GetGenericMapAspect(nodes.Get_Generic_Map_Aspect_Chain(instantiationNode))
portAssociationItems = GetPortMapAspect(nodes.Get_Port_Map_Aspect_Chain(instantiationNode))
return cls(instantiationNode, label, configurationSymbol, genericAssociationItems, portAssociationItems)
[docs]
@export
@InheritDocString(VHDLModel_ConcurrentBlockStatement, merge=True)
class ConcurrentBlockStatement(VHDLModel_ConcurrentBlockStatement, DOMMixin):
"""
This class implements a :mod:`pyGHDL.dom` object derived from :class:`pyVHDLModel.Concurrent.ConcurrentBlockStatement`.
"""
[docs]
def __init__(
self,
blockNode: Iir,
label: str,
genericItems: Iterable = None,
genericAssociationItems: Iterable = None,
portItems: Iterable = None,
portAssociationItems: Iterable = None,
declaredItems: Iterable = None,
statements: Iterable["ConcurrentStatement"] = None,
) -> None:
"""
Initializes a block statement.
:param blockNode: The IIR node of the :vhdlkw:`block` statement.
:param label: The label of the :vhdlkw:`block` statement.
:param genericItems: List of all generics, in declaration order.
:param genericAssociationItems: List of all generic associations in the generic map aspect.
:param portItems: List of all ports, in declaration order.
:param portAssociationItems: List of all port associations in the port map aspect.
:param declaredItems: List of all declared items in this concurrent declaration region.
:param statements: List of all concurrent statements in this construct.
"""
super().__init__(
label,
genericItems,
genericAssociationItems,
portItems,
portAssociationItems,
declaredItems,
statements,
)
DOMMixin.__init__(self, blockNode)
[docs]
@classmethod
def parse(cls, blockNode: Iir, label: str) -> "ConcurrentBlockStatement":
"""
Translates the IIR node of the block statement to a :class:`ConcurrentBlockStatement`.
:param blockNode: The IIR node of the block statement.
:param label: The statement's label, or ``None`` if it has none.
:returns: The translated block statement.
"""
from pyGHDL.dom._Translate import (
GetDeclaredItemsFromChainedNodes,
GetConcurrentStatementsFromChainedNodes,
GetGenericsFromChainedNodes,
GetPortsFromChainedNodes,
GetGenericMapAspect,
GetPortMapAspect,
)
# A block's generic/port clauses and their map aspects live on the block *header*, not on the
# block node itself. A block without a header has none of them.
blockHeader = nodes.Get_Block_Header(blockNode)
if blockHeader != nodes.Null_Iir:
genericItems = GetGenericsFromChainedNodes(nodes.Get_Generic_Chain(blockHeader))
genericAssociationItems = GetGenericMapAspect(nodes.Get_Generic_Map_Aspect_Chain(blockHeader))
portItems = GetPortsFromChainedNodes(nodes.Get_Port_Chain(blockHeader))
portAssociationItems = GetPortMapAspect(nodes.Get_Port_Map_Aspect_Chain(blockHeader))
else:
genericItems = genericAssociationItems = portItems = portAssociationItems = None
declaredItems = GetDeclaredItemsFromChainedNodes(nodes.Get_Declaration_Chain(blockNode), "block", label)
statements = GetConcurrentStatementsFromChainedNodes(
nodes.Get_Concurrent_Statement_Chain(blockNode), "block", label
)
return cls(
blockNode,
label,
genericItems,
genericAssociationItems,
portItems,
portAssociationItems,
declaredItems,
statements,
)
[docs]
@export
@InheritDocString(VHDLModel_ProcessStatement, merge=True)
class ProcessStatement(VHDLModel_ProcessStatement, DOMMixin):
"""
This class implements a :mod:`pyGHDL.dom` object derived from :class:`pyVHDLModel.Concurrent.ProcessStatement`.
"""
[docs]
def __init__(
self,
processNode: Iir,
label: str = None,
declaredItems: Iterable = None,
statements: Iterable[SequentialStatement] = None,
sensitivityList: Iterable[Symbol] = None,
) -> None:
"""
Initializes a :vhdlkw:`process` statement.
:param processNode: The IIR node of the :vhdlkw:`process` statement.
:param label: The label of the :vhdlkw:`process` statement, or ``None`` if it has none.
:param declaredItems: List of all declared items in this sequential declaration region.
:param statements: List of all sequential statements in this construct.
:param sensitivityList: List of all signal names in the sensitivity list, or ``None`` if none was given.
"""
super().__init__(label, declaredItems, statements, sensitivityList)
DOMMixin.__init__(self, processNode)
[docs]
@classmethod
def parse(cls, processNode: Iir, label: str, hasSensitivityList: bool) -> "ProcessStatement":
"""
Translates the IIR node of the process statement to a :class:`ProcessStatement`.
:param processNode: The IIR node of the process statement.
:param label: The statement's label, or ``None`` if it has none.
:param hasSensitivityList: ``True`` if the process was declared with a sensitivity list.
:returns: The translated process statement.
"""
from pyGHDL.dom._Translate import (
GetName,
GetDeclaredItemsFromChainedNodes,
GetSequentialStatementsFromChainedNodes,
)
sensitivityList = None
if hasSensitivityList:
sensitivityList = []
for item in utils.list_iter(nodes.Get_Sensitivity_List(processNode)):
sensitivityList.append(GetName(item))
declaredItems = GetDeclaredItemsFromChainedNodes(nodes.Get_Declaration_Chain(processNode), "process", label)
statements = GetSequentialStatementsFromChainedNodes(
nodes.Get_Sequential_Statement_Chain(processNode), "process", label
)
return cls(processNode, label, declaredItems, statements, sensitivityList)
[docs]
@export
@InheritDocString(VHDLModel_IfGenerateBranch, merge=True)
class IfGenerateBranch(VHDLModel_IfGenerateBranch, DOMMixin):
"""
This class implements a :mod:`pyGHDL.dom` object derived from :class:`pyVHDLModel.Concurrent.IfGenerateBranch`.
"""
[docs]
def __init__(
self,
branchNode: Iir,
condition: ExpressionUnion,
declaredItems: Iterable = None,
statements: Iterable[ConcurrentStatement] = None,
alternativeLabel: str = None,
) -> None:
"""
Initializes an :vhdlkw:`if..generate` branch.
:param branchNode: The IIR node of the branch this object represents.
:param condition: The condition under which this branch's declarations and statements are elaborated.
:param declaredItems: List of all declared items in this concurrent declaration region.
:param statements: List of all concurrent statements in this construct.
:param alternativeLabel: The branch's alternative label, if one was given.
"""
super().__init__(condition, declaredItems, statements, alternativeLabel)
DOMMixin.__init__(self, branchNode)
[docs]
@classmethod
def parse(cls, generateNode: Iir) -> "IfGenerateBranch":
"""
Translates the IIR node of the generate statement to an :class:`IfGenerateBranch`.
:param generateNode: The IIR node of the generate statement.
:returns: The translated generate statement.
"""
from pyGHDL.dom._Translate import (
GetDeclaredItemsFromChainedNodes,
GetConcurrentStatementsFromChainedNodes,
GetExpressionFromNode,
)
condition = GetExpressionFromNode(nodes.Get_Condition(generateNode))
body = nodes.Get_Generate_Statement_Body(generateNode)
alternativeLabel = GetLabelOfNode(body)
declarationChain = nodes.Get_Declaration_Chain(body)
declaredItems = GetDeclaredItemsFromChainedNodes(declarationChain, "if-generate branch", alternativeLabel)
statementChain = nodes.Get_Concurrent_Statement_Chain(body)
statements = GetConcurrentStatementsFromChainedNodes(statementChain, "if-generate branch", alternativeLabel)
return cls(generateNode, condition, declaredItems, statements, alternativeLabel)
[docs]
@export
@InheritDocString(VHDLModel_ElsifGenerateBranch, merge=True)
class ElsifGenerateBranch(VHDLModel_ElsifGenerateBranch, DOMMixin):
"""
This class implements a :mod:`pyGHDL.dom` object derived from :class:`pyVHDLModel.Concurrent.ElsifGenerateBranch`.
"""
[docs]
def __init__(
self,
branchNode: Iir,
condition: ExpressionUnion,
declaredItems: Iterable = None,
statements: Iterable[ConcurrentStatement] = None,
alternativeLabel: str = None,
) -> None:
"""
Initializes an :vhdlkw:`elsif` branch of an :vhdlkw:`if..generate` statement.
:param branchNode: The IIR node of the branch this object represents.
:param condition: The condition under which this branch's declarations and statements are elaborated.
:param declaredItems: List of all declared items in this concurrent declaration region.
:param statements: List of all concurrent statements in this construct.
:param alternativeLabel: The branch's alternative label, if one was given.
"""
super().__init__(condition, declaredItems, statements, alternativeLabel)
DOMMixin.__init__(self, branchNode)
[docs]
@classmethod
def parse(cls, generateNode: Iir, condition: Iir) -> "ElsifGenerateBranch":
"""
Translates the IIR node of the generate statement to an :class:`ElsifGenerateBranch`.
:param generateNode: The IIR node of the generate statement.
:param condition: The condition guarding the branch.
:returns: The translated generate statement.
"""
from pyGHDL.dom._Translate import (
GetDeclaredItemsFromChainedNodes,
GetConcurrentStatementsFromChainedNodes,
GetExpressionFromNode,
)
condition = GetExpressionFromNode(condition)
body = nodes.Get_Generate_Statement_Body(generateNode)
alternativeLabel = GetLabelOfNode(body)
declarationChain = nodes.Get_Declaration_Chain(body)
declaredItems = GetDeclaredItemsFromChainedNodes(declarationChain, "elsif-generate branch", alternativeLabel)
statementChain = nodes.Get_Concurrent_Statement_Chain(body)
statements = GetConcurrentStatementsFromChainedNodes(statementChain, "elsif-generate branch", alternativeLabel)
return cls(generateNode, condition, declaredItems, statements, alternativeLabel)
[docs]
@export
@InheritDocString(VHDLModel_ElseGenerateBranch, merge=True)
class ElseGenerateBranch(VHDLModel_ElseGenerateBranch, DOMMixin):
"""
This class implements a :mod:`pyGHDL.dom` object derived from :class:`pyVHDLModel.Concurrent.ElseGenerateBranch`.
"""
[docs]
def __init__(
self,
branchNode: Iir,
declaredItems: Iterable = None,
statements: Iterable[ConcurrentStatement] = None,
alternativeLabel: str = None,
) -> None:
"""
Initializes an else generate branch.
:param branchNode: The IIR node of the branch this object represents.
:param declaredItems: List of all declared items in this concurrent declaration region.
:param statements: List of all concurrent statements in this construct.
:param alternativeLabel: The branch's alternative label, if one was given.
"""
super().__init__(declaredItems, statements, alternativeLabel)
DOMMixin.__init__(self, branchNode)
[docs]
@classmethod
def parse(cls, generateNode: Iir) -> "ElseGenerateBranch":
"""
Translates the IIR node of the generate statement to an :class:`ElseGenerateBranch`.
:param generateNode: The IIR node of the generate statement.
:returns: The translated generate statement.
"""
from pyGHDL.dom._Translate import (
GetDeclaredItemsFromChainedNodes,
GetConcurrentStatementsFromChainedNodes,
)
body = nodes.Get_Generate_Statement_Body(generateNode)
alternativeLabel = GetLabelOfNode(body)
declarationChain = nodes.Get_Declaration_Chain(body)
declaredItems = GetDeclaredItemsFromChainedNodes(declarationChain, "else-generate branch", alternativeLabel)
statementChain = nodes.Get_Concurrent_Statement_Chain(body)
statements = GetConcurrentStatementsFromChainedNodes(statementChain, "else-generate branch", alternativeLabel)
return cls(generateNode, declaredItems, statements, alternativeLabel)
[docs]
@export
@InheritDocString(VHDLModel_IfGenerateStatement, merge=True)
class IfGenerateStatement(VHDLModel_IfGenerateStatement, DOMMixin):
"""
This class implements a :mod:`pyGHDL.dom` object derived from :class:`pyVHDLModel.Concurrent.IfGenerateStatement`.
"""
[docs]
def __init__(
self,
generateNode: Iir,
label: str,
ifBranch: IfGenerateBranch,
elsifBranches: Iterable[ElsifGenerateBranch] = None,
elseBranch: ElseGenerateBranch = None,
) -> None:
"""
Initializes an :vhdlkw:`if..generate` statement.
:param generateNode: The IIR node of the generate statement.
:param label: The label of the :vhdlkw:`if..generate` statement.
:param ifBranch: The mandatory :vhdlkw:`if` branch.
:param elsifBranches: List of all :vhdlkw:`elsif` branches, in the order they were written.
:param elseBranch: The optional :vhdlkw:`else` branch, or ``None`` if none was given.
"""
super().__init__(label, ifBranch, elsifBranches, elseBranch)
DOMMixin.__init__(self, generateNode)
[docs]
@classmethod
def parse(cls, generateNode: Iir, label: str) -> "IfGenerateStatement":
"""
Translates the IIR node of the generate statement to an :class:`IfGenerateStatement`.
:param generateNode: The IIR node of the generate statement.
:param label: The statement's label, or ``None`` if it has none.
:returns: The translated generate statement.
"""
ifBranch = IfGenerateBranch.parse(generateNode)
elsifBranches = []
elseBranch = None
# WORKAROUND: Python 3.8 syntax
# elseClause = generateNode
# while (elseClause := nodes.Get_Generate_Else_Clause(elseClause)) != nodes.Null_Iir:
elseClause = nodes.Get_Generate_Else_Clause(generateNode)
while elseClause != nodes.Null_Iir:
condition = nodes.Get_Condition(elseClause)
if condition != nodes.Null_Iir:
elsifBranches.append(ElsifGenerateBranch.parse(elseClause, condition))
else:
elseBranch = ElseGenerateBranch.parse(elseClause)
break
elseClause = nodes.Get_Generate_Else_Clause(elseClause)
return cls(generateNode, label, ifBranch, elsifBranches, elseBranch)
[docs]
@export
@InheritDocString(VHDLModel_IndexedGenerateChoice, merge=True)
class IndexedGenerateChoice(VHDLModel_IndexedGenerateChoice, DOMMixin):
"""
This class implements a :mod:`pyGHDL.dom` object derived from :class:`pyVHDLModel.Concurrent.IndexedGenerateChoice`.
"""
[docs]
def __init__(self, node: Iir, expression: ExpressionUnion) -> None:
"""
Initializes a case-generate choice given by a single value.
:param node: The IIR node this object was translated from.
:param expression: The expression this choice selects on.
"""
super().__init__(expression)
DOMMixin.__init__(self, node)
[docs]
@export
@InheritDocString(VHDLModel_RangedGenerateChoice, merge=True)
class RangedGenerateChoice(VHDLModel_RangedGenerateChoice, DOMMixin):
"""
This class implements a :mod:`pyGHDL.dom` object derived from :class:`pyVHDLModel.Concurrent.RangedGenerateChoice`.
"""
[docs]
def __init__(self, node: Iir, rng: Range) -> None:
"""
Initializes a case-generate choice given by a range.
:param node: The IIR node this object was translated from.
:param rng: The range this choice selects on.
"""
super().__init__(rng)
DOMMixin.__init__(self, node)
[docs]
@export
@InheritDocString(VHDLModel_GenerateCase, merge=True)
class GenerateCase(VHDLModel_GenerateCase, DOMMixin):
"""
This class implements a :mod:`pyGHDL.dom` object derived from :class:`pyVHDLModel.Concurrent.GenerateCase`.
"""
[docs]
def __init__(
self,
node: Iir,
choices: Iterable[ConcurrentChoice],
declaredItems: Iterable = None,
statements: Iterable[ConcurrentStatement] = None,
alternativeLabel: str = None,
) -> None:
"""
Initializes a generate case.
:param node: The IIR node this object was translated from.
:param choices: List of all choices selecting this alternative.
:param declaredItems: List of all declared items in this concurrent declaration region.
:param statements: List of all concurrent statements in this construct.
:param alternativeLabel: The alternative's label.
"""
super().__init__(choices, declaredItems, statements, alternativeLabel)
DOMMixin.__init__(self, node)
[docs]
@classmethod
def parse(cls, caseNode: Iir, choices: Iterable[ConcurrentChoice]) -> "GenerateCase":
"""
Translates the IIR node of the alternative to a :class:`GenerateCase`.
:param caseNode: The IIR node of the alternative.
:param choices: List of all choices selecting this alternative.
:returns: The translated alternative.
"""
from pyGHDL.dom._Translate import (
GetDeclaredItemsFromChainedNodes,
GetConcurrentStatementsFromChainedNodes,
)
body = nodes.Get_Associated_Block(caseNode)
alternativeLabel = GetLabelOfNode(body)
declarationChain = nodes.Get_Declaration_Chain(body)
declaredItems = GetDeclaredItemsFromChainedNodes(declarationChain, "generate case", alternativeLabel)
statementChain = nodes.Get_Concurrent_Statement_Chain(body)
statements = GetConcurrentStatementsFromChainedNodes(statementChain, "generate case", alternativeLabel)
return cls(caseNode, choices, declaredItems, statements, alternativeLabel)
[docs]
@export
@InheritDocString(VHDLModel_OthersGenerateCase, merge=True)
class OthersGenerateCase(VHDLModel_OthersGenerateCase, DOMMixin):
"""
This class implements a :mod:`pyGHDL.dom` object derived from :class:`pyVHDLModel.Concurrent.OthersGenerateCase`.
"""
[docs]
def __init__(
self,
caseNode: Iir,
declaredItems: Iterable = None,
statements: Iterable[ConcurrentStatement] = None,
alternativeLabel: str = None,
) -> None:
"""
Initializes an :vhdlkw:`others` generate alternative.
:param caseNode: The IIR node of the :vhdlkw:`case` statement.
:param declaredItems: List of all declared items in this concurrent declaration region.
:param statements: List of all concurrent statements in this construct.
:param alternativeLabel: The alternative's label.
"""
super().__init__(declaredItems, statements, alternativeLabel)
DOMMixin.__init__(self, caseNode)
[docs]
@classmethod
def parse(cls, caseNode: Iir) -> "OthersGenerateCase":
"""
Translates the IIR node of the alternative to an :class:`OthersGenerateCase`.
:param caseNode: The IIR node of the alternative.
:returns: The translated alternative.
"""
from pyGHDL.dom._Translate import (
GetDeclaredItemsFromChainedNodes,
GetConcurrentStatementsFromChainedNodes,
)
body = nodes.Get_Associated_Block(caseNode)
alternativeLabel = GetLabelOfNode(body)
declarationChain = nodes.Get_Declaration_Chain(body)
declaredItems = GetDeclaredItemsFromChainedNodes(declarationChain, "case-generate others", alternativeLabel)
statementChain = nodes.Get_Concurrent_Statement_Chain(body)
statements = GetConcurrentStatementsFromChainedNodes(statementChain, "case-generate others", alternativeLabel)
return cls(caseNode, declaredItems, statements, alternativeLabel)
[docs]
@export
@InheritDocString(VHDLModel_CaseGenerateStatement, merge=True)
class CaseGenerateStatement(VHDLModel_CaseGenerateStatement, DOMMixin):
"""
This class implements a :mod:`pyGHDL.dom` object derived from :class:`pyVHDLModel.Concurrent.CaseGenerateStatement`.
"""
[docs]
def __init__(
self,
generateNode: Iir,
label: str,
expression: ExpressionUnion,
cases: Iterable[ConcurrentCase],
) -> None:
"""
Initializes a :vhdlkw:`case..generate` statement.
:param generateNode: The IIR node of the generate statement.
:param label: The label of the :vhdlkw:`case..generate` statement.
:param expression: The expression selecting the alternative.
:param cases: List of all alternatives, in the order they were written.
"""
super().__init__(label, expression, cases)
DOMMixin.__init__(self, generateNode)
[docs]
@classmethod
def parse(cls, generateNode: Iir, label: str) -> "CaseGenerateStatement":
"""
Translates the IIR node of the generate statement to a :class:`CaseGenerateStatement`.
:param generateNode: The IIR node of the generate statement.
:param label: The statement's label, or ``None`` if it has none.
:returns: The translated generate statement.
"""
from pyGHDL.dom._Utils import GetIirKindOfNode
from pyGHDL.dom._Translate import (
GetExpressionFromNode,
GetRangeFromNode,
GetName,
)
expression = GetExpressionFromNode(nodes.Get_Expression(generateNode))
cases = []
choices = None
alternative = nodes.Get_Case_Statement_Alternative_Chain(generateNode)
caseNode = alternative
while alternative != nodes.Null_Iir:
choiceKind = GetIirKindOfNode(alternative)
sameAlternative = nodes.Get_Same_Alternative_Flag(alternative)
if choiceKind in (
nodes.Iir_Kind.Choice_By_Name,
nodes.Iir_Kind.Choice_By_Expression,
):
choiceExpression = GetExpressionFromNode(nodes.Get_Choice_Expression(alternative))
choice = IndexedGenerateChoice(alternative, choiceExpression)
if sameAlternative:
choices.append(choice)
alternative = nodes.Get_Chain(alternative)
continue
elif choiceKind is nodes.Iir_Kind.Choice_By_Range:
choiceRange = nodes.Get_Choice_Range(alternative)
choiceRangeKind = GetIirKindOfNode(choiceRange)
if choiceRangeKind == nodes.Iir_Kind.Range_Expression:
rng = GetRangeFromNode(choiceRange)
elif choiceRangeKind in (
nodes.Iir_Kind.Attribute_Name,
nodes.Iir_Kind.Parenthesis_Name,
):
rng = GetName(choiceRange)
else:
pos = Position.parse(alternative)
raise DOMException(
f"Unknown choice range kind '{choiceRangeKind.name}' in case...generate statement at line {pos.Line}."
)
choice = RangedGenerateChoice(alternative, rng)
if sameAlternative:
choices.append(choice)
alternative = nodes.Get_Chain(alternative)
continue
elif choiceKind is nodes.Iir_Kind.Choice_By_Others:
if choices is not None:
cases.append(GenerateCase.parse(caseNode, choices))
choices = None
cases.append(OthersGenerateCase.parse(alternative))
alternative = nodes.Get_Chain(alternative)
caseNode = alternative
continue
else:
pos = Position.parse(alternative)
raise DOMException(
f"Unknown choice kind '{choiceKind.name}' in case...generate statement at line {pos.Line}."
)
if choices is not None:
cases.append(GenerateCase.parse(caseNode, choices))
caseNode = alternative
choices = [choice]
alternative = nodes.Get_Chain(alternative)
if choices is not None:
cases.append(GenerateCase.parse(caseNode, choices))
return cls(generateNode, label, expression, cases)
[docs]
@export
@InheritDocString(VHDLModel_ForGenerateStatement, merge=True)
class ForGenerateStatement(VHDLModel_ForGenerateStatement, DOMMixin):
"""
This class implements a :mod:`pyGHDL.dom` object derived from :class:`pyVHDLModel.Concurrent.ForGenerateStatement`.
"""
[docs]
def __init__(
self,
generateNode: Iir,
label: str,
loopIndex: str,
rng: Range,
declaredItems: Iterable = None,
statements: Iterable[ConcurrentStatement] = None,
parent: Nullable[ModelEntity] = None,
) -> None:
"""
Initializes a :vhdlkw:`for..generate` statement.
:param generateNode: The IIR node of the generate statement.
:param label: The label of the :vhdlkw:`for..generate` statement.
:param loopIndex: The name of the generate loop's index.
:param rng: The range the generate loop iterates over.
:param declaredItems: List of all declared items in this concurrent declaration region.
:param statements: List of all concurrent statements in this construct.
:param parent: The parent model entity of this entity.
"""
super().__init__(label, loopIndex, rng, declaredItems, statements, parent=parent)
DOMMixin.__init__(self, generateNode)
[docs]
@classmethod
def parse(cls, generateNode: Iir, label: str) -> "ForGenerateStatement":
"""
Translates the IIR node of the generate statement to a :class:`ForGenerateStatement`.
:param generateNode: The IIR node of the generate statement.
:param label: The statement's label, or ``None`` if it has none.
:returns: The translated generate statement.
"""
from pyGHDL.dom._Utils import GetNameOfNode
from pyGHDL.dom._Translate import (
GetDeclaredItemsFromChainedNodes,
GetConcurrentStatementsFromChainedNodes,
GetDiscreteRangeFromNode,
)
spec = nodes.Get_Parameter_Specification(generateNode)
loopIndex = GetNameOfNode(spec)
rng = GetDiscreteRangeFromNode(nodes.Get_Discrete_Range(spec), "for...generate statement")
body = nodes.Get_Generate_Statement_Body(generateNode)
declarationChain = nodes.Get_Declaration_Chain(body)
declaredItems = GetDeclaredItemsFromChainedNodes(declarationChain, "for-generate", label)
statementChain = nodes.Get_Concurrent_Statement_Chain(body)
statements = GetConcurrentStatementsFromChainedNodes(statementChain, "for-generate", label)
return cls(generateNode, label, loopIndex, rng, declaredItems, statements)
def GetWaveformElementsFromChainedNodes(nodeChain: Iir) -> List[WaveformElement]:
"""
Translates a chain of ``Waveform_Element`` nodes into a list of :class:`WaveformElement`.
The chain is used at multiple call sites: simple, conditional and selected signal assignments,
both concurrent and sequential.
:param nodeChain: The IIR node starting the chain of waveform elements.
:returns: List of the translated waveform elements, in source order.
"""
return [WaveformElement.parse(wave) for wave in utils.chain_iter(nodeChain)]
def GetConditionalWaveformsFromChainedNodes(nodeChain: Iir) -> Iterable["ConditionalWaveform"]:
"""
Translates a chain of ``Conditional_Waveform`` nodes into a sequence of :class:`ConditionalWaveform`.
The chain is shared by concurrent and sequential conditional signal assignments.
:param nodeChain: The IIR node starting the chain of conditional waveforms.
:returns: The translated conditional waveforms, in source order.
"""
return [ConditionalWaveform.parse(node) for node in utils.chain_iter(nodeChain)]
def GetSelectedWaveformsFromChainedNodes(nodeChain: Iir) -> Iterable:
"""
Translates a chain of choices (shared by concurrent and sequential selected signal assignments)
into a sequence of :class:`SelectedWaveform`/:class:`OthersSelectedWaveform`.
Mirrors the grouping algorithm already used for case-generate alternatives
(``Get_Same_Alternative_Flag`` groups e.g. ``when 0 | 1 =>`` into one alternative): the *first*
choice in a group owns the real content (``Get_Associated_Chain``, ``Same_Alternative_Flag=False``);
later choices in the same group (``Same_Alternative_Flag=True``) have a null associated chain and
are just additional choice values for that same, already-established alternative.
:param nodeChain: The IIR node starting the chain of choices.
:returns: The translated selected waveforms, in source order.
:raises DOMException: If a choice's kind is not handled.
"""
from pyGHDL.dom._Utils import GetIirKindOfNode
from pyGHDL.dom._Translate import GetExpressionFromNode, GetRangeFromNode
from pyGHDL.dom.Sequential import IndexedChoice, RangedChoice
alternatives = []
choices = None
ownerNode = None
choice = nodeChain
while choice != nodes.Null_Iir:
kind = GetIirKindOfNode(choice)
sameAlternative = nodes.Get_Same_Alternative_Flag(choice)
if kind == nodes.Iir_Kind.Choice_By_Expression:
choiceValue = IndexedChoice(choice, GetExpressionFromNode(nodes.Get_Choice_Expression(choice)))
if sameAlternative:
choices.append(choiceValue)
choice = nodes.Get_Chain(choice)
continue
elif kind == nodes.Iir_Kind.Choice_By_Range:
choiceValue = RangedChoice(choice, GetRangeFromNode(nodes.Get_Choice_Range(choice)))
if sameAlternative:
choices.append(choiceValue)
choice = nodes.Get_Chain(choice)
continue
elif kind == nodes.Iir_Kind.Choice_By_Others:
if choices is not None:
waveform = GetWaveformElementsFromChainedNodes(nodes.Get_Associated_Chain(ownerNode))
alternatives.append(SelectedWaveform(ownerNode, choices, waveform))
choices = None
othersWaveform = GetWaveformElementsFromChainedNodes(nodes.Get_Associated_Chain(choice))
alternatives.append(OthersSelectedWaveform(choice, othersWaveform))
choice = nodes.Get_Chain(choice)
continue
else:
position = Position.parse(choice)
raise DOMException(f"Unknown choice kind '{kind.name}' in selected waveform at {position}.")
if choices is not None:
waveform = GetWaveformElementsFromChainedNodes(nodes.Get_Associated_Chain(ownerNode))
alternatives.append(SelectedWaveform(ownerNode, choices, waveform))
ownerNode = choice
choices = [choiceValue]
choice = nodes.Get_Chain(choice)
if choices is not None:
waveform = GetWaveformElementsFromChainedNodes(nodes.Get_Associated_Chain(ownerNode))
alternatives.append(SelectedWaveform(ownerNode, choices, waveform))
return alternatives
[docs]
@export
@InheritDocString(VHDLModel_ConcurrentSimpleSignalAssignment, merge=True)
class ConcurrentSimpleSignalAssignment(VHDLModel_ConcurrentSimpleSignalAssignment, DOMMixin):
"""
This class implements a :mod:`pyGHDL.dom` object derived from :class:`pyVHDLModel.Concurrent.ConcurrentSimpleSignalAssignment`.
"""
[docs]
def __init__(
self,
assignmentNode: Iir,
label: str,
target: SignalSymbol,
waveform: Iterable[WaveformElement],
) -> None:
"""
Initializes a simple concurrent signal assignment.
:param assignmentNode: The IIR node of the assignment statement.
:param label: The label of the concurrent signal assignment, or ``None`` if it has none.
:param target: Reference to the assignment's destination.
:param waveform: List of all waveform elements, in the order they were written.
"""
super().__init__(label, target, waveform)
DOMMixin.__init__(self, assignmentNode)
[docs]
@classmethod
def parse(cls, assignmentNode: Iir, label: str) -> "ConcurrentSimpleSignalAssignment":
"""
Translates the IIR node of the assignment statement to a :class:`ConcurrentSimpleSignalAssignment`.
:param assignmentNode: The IIR node of the assignment statement.
:param label: The statement's label, or ``None`` if it has none.
:returns: The translated assignment statement.
"""
from pyGHDL.dom._Translate import GetName
targetNode = nodes.Get_Target(assignmentNode)
targetName = SignalSymbol(targetNode, GetName(targetNode))
waveform = GetWaveformElementsFromChainedNodes(nodes.Get_Waveform_Chain(assignmentNode))
return cls(assignmentNode, label, targetName, waveform)
[docs]
@export
@InheritDocString(VHDLModel_ConcurrentConditionalSignalAssignment, merge=True)
class ConcurrentConditionalSignalAssignment(VHDLModel_ConcurrentConditionalSignalAssignment, DOMMixin):
"""
This class implements a :mod:`pyGHDL.dom` object derived from :class:`pyVHDLModel.Concurrent.ConcurrentConditionalSignalAssignment`.
"""
[docs]
def __init__(
self,
assignmentNode: Iir,
label: str,
target: SignalSymbol,
conditionalWaveforms: Iterable[ConditionalWaveform],
) -> None:
"""
Initializes a conditional concurrent signal assignment.
:param assignmentNode: The IIR node of the assignment statement.
:param label: The label of the conditional concurrent signal assignment, or ``None`` if it has none.
:param target: Reference to the assignment's destination.
:param conditionalWaveforms: All alternatives, in order.
"""
super().__init__(label, target, conditionalWaveforms)
DOMMixin.__init__(self, assignmentNode)
[docs]
@classmethod
def parse(cls, assignmentNode: Iir, label: str) -> "ConcurrentConditionalSignalAssignment":
"""
Translates the IIR node of the assignment statement to a :class:`ConcurrentConditionalSignalAssignment`.
:param assignmentNode: The IIR node of the assignment statement.
:param label: The statement's label, or ``None`` if it has none.
:returns: The translated assignment statement.
"""
from pyGHDL.dom._Translate import GetName
targetNode = nodes.Get_Target(assignmentNode)
targetName = SignalSymbol(targetNode, GetName(targetNode))
conditionalWaveforms = GetConditionalWaveformsFromChainedNodes(
nodes.Get_Conditional_Waveform_Chain(assignmentNode)
)
return cls(assignmentNode, label, targetName, conditionalWaveforms)
[docs]
@export
@InheritDocString(VHDLModel_ConcurrentSelectedSignalAssignment, merge=True)
class ConcurrentSelectedSignalAssignment(VHDLModel_ConcurrentSelectedSignalAssignment, DOMMixin):
"""
This class implements a :mod:`pyGHDL.dom` object derived from :class:`pyVHDLModel.Concurrent.ConcurrentSelectedSignalAssignment`.
"""
[docs]
def __init__(
self,
assignmentNode: Iir,
label: str,
target: SignalSymbol,
expression: ExpressionUnion,
selectedWaveforms: Iterable,
) -> None:
"""
Initializes a selected concurrent signal assignment.
:param assignmentNode: The IIR node of the assignment statement.
:param label: The label of the selected concurrent signal assignment, or ``None`` if it has none.
:param target: Reference to the assignment's destination.
:param expression: The selector expression.
:param selectedWaveforms: All alternatives, in order.
"""
super().__init__(label, target, expression, selectedWaveforms)
DOMMixin.__init__(self, assignmentNode)
[docs]
@classmethod
def parse(cls, assignmentNode: Iir, label: str) -> "ConcurrentSelectedSignalAssignment":
"""
Translates the IIR node of the assignment statement to a :class:`ConcurrentSelectedSignalAssignment`.
:param assignmentNode: The IIR node of the assignment statement.
:param label: The statement's label, or ``None`` if it has none.
:returns: The translated assignment statement.
"""
from pyGHDL.dom._Translate import GetName, GetExpressionFromNode
targetNode = nodes.Get_Target(assignmentNode)
targetName = SignalSymbol(targetNode, GetName(targetNode))
expression = GetExpressionFromNode(nodes.Get_Expression(assignmentNode))
selectedWaveforms = GetSelectedWaveformsFromChainedNodes(nodes.Get_Selected_Waveform_Chain(assignmentNode))
return cls(assignmentNode, label, targetName, expression, selectedWaveforms)
[docs]
@export
@InheritDocString(VHDLModel_ConcurrentProcedureCall, merge=True)
class ConcurrentProcedureCall(VHDLModel_ConcurrentProcedureCall, DOMMixin):
"""
This class implements a :mod:`pyGHDL.dom` object derived from :class:`pyVHDLModel.Concurrent.ConcurrentProcedureCall`.
"""
[docs]
def __init__(
self,
callNode: Iir,
label: str,
procedureName: Symbol,
parameterAssociationItems: Iterable,
) -> None:
"""
Initializes a concurrent procedure call.
:param callNode: The IIR node of the subprogram call.
:param label: The label of the concurrent procedure call, or ``None`` if it has none.
:param procedureName: Reference to the called procedure.
:param parameterAssociationItems: List of all parameter associations of the call.
"""
super().__init__(label, procedureName, parameterAssociationItems)
DOMMixin.__init__(self, callNode)
[docs]
@classmethod
def parse(cls, concurrentCallNode: Iir, label: str) -> "ConcurrentProcedureCall":
"""
Translates the IIR node of the concurrent procedure call to a :class:`ConcurrentProcedureCall`.
:param concurrentCallNode: The IIR node of the concurrent procedure call.
:param label: The statement's label, or ``None`` if it has none.
:returns: The translated concurrent procedure call.
"""
from pyGHDL.dom._Translate import GetName, GetParameterMapAspect
callNode = nodes.Get_Procedure_Call(concurrentCallNode)
prefix = nodes.Get_Prefix(callNode)
procedureName = GetName(prefix)
parameterAssociations = GetParameterMapAspect(nodes.Get_Parameter_Association_Chain(callNode))
return cls(concurrentCallNode, label, procedureName, parameterAssociations)
[docs]
@export
@InheritDocString(VHDLModel_ConcurrentAssertStatement, merge=True)
class ConcurrentAssertStatement(VHDLModel_ConcurrentAssertStatement, DOMMixin):
"""
This class implements a :mod:`pyGHDL.dom` object derived from :class:`pyVHDLModel.Concurrent.ConcurrentAssertStatement`.
"""
[docs]
def __init__(
self,
assertNode: Iir,
condition: ExpressionUnion,
message: ExpressionUnion = None,
severity: ExpressionUnion = None,
label: str = None,
) -> None:
"""
Initializes a concurrent assertion statement.
:param assertNode: The IIR node of the assertion.
:param condition: The condition that must hold; the report is issued when it is false.
:param message: The reported message, or ``None`` if none was given.
:param severity: The reported severity level, or ``None`` if none was given.
:param label: The label of the concurrent assertion statement, or ``None`` if it has none.
"""
super().__init__(condition, message, severity, label)
DOMMixin.__init__(self, assertNode)
[docs]
@classmethod
def parse(cls, assertNode: Iir, label: str) -> "ConcurrentAssertStatement":
"""
Translates the IIR node of the assertion to a :class:`ConcurrentAssertStatement`.
:param assertNode: The IIR node of the assertion.
:param label: The statement's label, or ``None`` if it has none.
:returns: The translated assertion.
"""
from pyGHDL.dom._Translate import GetOptionalExpressionFromNode
# FIXME: how to get the condition?
# assertNode is a Psl_Assert_Directive
condition = None # GetOptionalExpressionFromNode(nodes.Get_Assertion_Condition(assertNode))
message = GetOptionalExpressionFromNode(nodes.Get_Report_Expression(assertNode))
severity = GetOptionalExpressionFromNode(nodes.Get_Severity_Expression(assertNode))
return cls(assertNode, condition, message, severity, label)