.. # This page is generated by doc/ASTReference.py when Sphinx starts. Do not edit it. Sequential Statement Ext ######################## The diagrams below draw one box per node kind, with one port per field. The edge colours say how a link is held; they are listed in full on the :ref:`INT:AST:Fields` page. .. graphviz:: digraph { rankdir="LR" nodesep=0.1 node [shape=point width=0.06 color="#888a85"] edge [fontname="monospace" fontsize=10 minlen=3] l0a -> l0b [label="owned" color="#000000"] l1a -> l1b [label="ref" color="#3465a4" style=dashed] l2a -> l2b [label="maybe ref" color="#3465a4" style=dotted] l3a -> l3b [label="of ref" color="#3465a4" style=dashed] l4a -> l4b [label="of maybe ref" color="#3465a4" style=dotted] l5a -> l5b [label="forward ref" color="#f57900" style=dashed] l6a -> l6b [label="maybe forward ref" color="#f57900" style=dotted] l7a -> l7b [label="chain" color="#4e9a06"] l8a -> l8b [label="chain next" color="#4e9a06" style=bold] } .. _INT:AST:Simple_Signal_Assignment_Statement: Iir_Kind_Simple_Signal_Assignment_Statement =========================================== Format: ``Short`` .. list-table:: :header-rows: 1 :widths: 30 12 18 12 28 * - Accessor - Field - Type - Access - Description * - :ref:`Parent ` - ``Field0`` - ``Iir`` - ref - Get/Set the statement in which TARGET appears. This is used to check if next/exit is in a loop. * - :ref:`Target ` - ``Field1`` - ``Iir`` - maybe ref - — * - :ref:`Chain ` - ``Field2`` - ``Iir`` - chain next - — * - :ref:`Label ` - ``Field3`` - ``Name_Id`` - owned - — * - :ref:`Reject_Time_Expression ` - ``Field4`` - ``Iir`` - owned - — * - :ref:`Waveform_Chain ` - ``Field5`` - ``Iir`` - chain - The waveform. If the waveform_chain is null_iir, then the signal assignment is a disconnection statement, ie TARGET <= null_iir after disconection_time, where disconnection_time is specified by a disconnection specification. * - :ref:`Delay_Mechanism ` - ``Flag1`` - ``Iir_Delay_Mechanism`` - owned - — * - :ref:`Has_Delay_Mechanism ` - ``Flag2`` - ``Boolean`` - owned - Layout flag for signal assignment. If True, the delay mechanism is present. This is obviously true for transport or inertial with reject, but the simple 'inertial' is optional. * - :ref:`Visible_Flag ` - ``Flag4`` - ``Boolean`` - owned - Get/Set the visible flag of a declaration. The visible flag is true to make invalid the use of the identifier during its declaration. It is set to false when the identifier is added to the name table, and set to true when the declaration is finished. * - :ref:`Guarded_Target_State ` - ``State1`` - ``Tri_State_Type`` - owned - True if the target of the assignment is guarded * - :ref:`Is_Ref ` - ``Flag12`` - ``Boolean`` - owned - Set to True if Maybe_Ref fields are references. This cannot be shared with Has_Identifier_List as: Is_Ref is set to True on all items but the first, while Has_Identifier_List is set to True on all items but the last. Furthermore Is_Ref appears in nodes where Has_Identifier_List is not present. * - :ref:`Covered_Flag ` - ``Flag10`` - ``Boolean`` - owned - Set during elaboration when the statement is executed. .. graphviz:: digraph { rankdir="LR" node [shape=record fontname="monospace" fontsize=10] edge [fontname="monospace" fontsize=9] "Simple_Signal_Assignment_Statement" [style=filled fillcolor="#eeeeec" label="{Simple_Signal_Assignment_Statement|{ Parent| Target| Chain|