# =============================================================================
# ____ _ _ ____ _ _
# _ __ _ _ / ___| | | | _ \| | __| | ___ _ __ ___
# | '_ \| | | | | _| |_| | | | | | / _` |/ _ \| '_ ` _ \
# | |_) | |_| | |_| | _ | |_| | |___ | (_| | (_) | | | | | |
# | .__/ \__, |\____|_| |_|____/|_____(_)__,_|\___/|_| |_| |_|
# |_| |___/
# =============================================================================
# Authors:
# Patrick Lehmann
#
# Package module: DOM: Interface items (e.g. generic or port)
#
# License:
# ============================================================================
# Copyright (C) 2019-2021 Tristan Gingold
#
# This program is free software: you can redistribute it and/or modify
# it under the terms of the GNU General Public License as published by
# the Free Software Foundation, either version 2 of the License, or
# (at your option) any later version.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
# You should have received a copy of the GNU General Public License
# along with this program. If not, see <gnu.org/licenses>.
#
# SPDX-License-Identifier: GPL-2.0-or-later
# ============================================================================
from typing import List
from pyTooling.Decorators import export
from pyVHDLModel.Name import Name
from pyVHDLModel.Name import SimpleName as VHDLModel_SimpleName
from pyVHDLModel.Name import ParenthesisName as VHDLModel_ParenthesisName
from pyVHDLModel.Name import IndexedName as VHDLModel_IndexedName
from pyVHDLModel.Name import SlicedName as VHDLModel_SlicedName
from pyVHDLModel.Name import SelectedName as VHDLModel_SelectedName
from pyVHDLModel.Name import AttributeName as VHDLModel_AttributeName
from pyVHDLModel.Name import AllName as VHDLModel_AllName
from pyVHDLModel.Name import OpenName as VHDLModel_OpenName
from pyGHDL.libghdl._types import Iir
from pyGHDL.dom import DOMMixin
[docs]@export
class SimpleName(VHDLModel_SimpleName, DOMMixin):
[docs] def __init__(self, node: Iir, identifier: str):
super().__init__(identifier)
DOMMixin.__init__(self, node)
[docs]@export
class ParenthesisName(VHDLModel_ParenthesisName, DOMMixin):
[docs] def __init__(self, node: Iir, prefix: Name, associations: List):
super().__init__(prefix, associations)
DOMMixin.__init__(self, node)
[docs]@export
class IndexedName(VHDLModel_IndexedName, DOMMixin):
[docs] def __init__(self, node: Iir, identifier: str):
super().__init__(identifier)
DOMMixin.__init__(self, node)
[docs]@export
class SlicedName(VHDLModel_SlicedName, DOMMixin):
[docs] def __init__(self, node: Iir, identifier: str):
super().__init__(identifier)
DOMMixin.__init__(self, node)
[docs]@export
class SelectedName(VHDLModel_SelectedName, DOMMixin):
[docs] def __init__(self, node: Iir, identifier: str, prefix: Name):
super().__init__(identifier, prefix)
DOMMixin.__init__(self, node)
[docs]@export
class AttributeName(VHDLModel_AttributeName, DOMMixin):
[docs] def __init__(self, node: Iir, identifier: str, prefix: Name):
super().__init__(identifier, prefix)
DOMMixin.__init__(self, node)
[docs]@export
class AllName(VHDLModel_AllName, DOMMixin):
[docs] def __init__(self, node: Iir, prefix: Name):
super().__init__(prefix)
DOMMixin.__init__(self, node)
[docs]@export
class OpenName(VHDLModel_OpenName, DOMMixin):
[docs] def __init__(self, node: Iir):
super().__init__()
DOMMixin.__init__(self, node)