Examples# Quick Start ‘rand’ from stdlib ‘sin’ from libmath custom C Wrapping ghdl_main basic time exitcb Linking bind package sharedvar shint shrecord Command-Line Arguments Top-level generics Parsing/customizing argv Setting parameters in C through VHDL generics JSON-for-VHDL GRT step Shared libs and dynamic loading shlib dlopen shghdl py py/vunit pycb Arrays Constrained/bounded integer arrays Sized in C Sized in VHDL Vector of std_logic Matrices Constrained multidimensional arrays of doubles/reals Array and AXI4 Stream Verification Components VGA (RGB image buffer) FFI/DPI Header demo crypto xyce Xyce: C interface Xyce: VHDL interface xyce package xyce_xhdl package Examples runACircuit runACircuitInSteps runWithDACs Usage GUI features Analog modelling Other co-simulation projects ghdlex and netpp VUnit ygdes.com