Test Report

Summary

Started 2021-11-23 15:22:05
Ended 2021-11-23 15:41:40
Duration 0:19:35.168741
Total run time 0:38:14.624903
8954
621 xfailed 8333 xpassed

Tests

TestDOM.py 6218333 0:38:14.624903

XPASS test_AllVHDLSources[/home/runner/work/extended-tests/extended-tests/ghdl-cosim/vhpidirect/vffi_user-body.vhd] 0:00:00.369339

Started 2021-11-23 15:22:07
Ended 2021-11-23 15:22:08
Duration 0:00:00.369339
Markers
xfail
Fixtures file

Setup

Call

Captured stdout call
================================================================================
                         pyGHDL.dom - Test Application                          
================================================================================
Parsing file '/home/runner/work/extended-tests/extended-tests/ghdl-cosim/vhpidirect/vffi_user-body.vhd'
libghdl processing time:  76.301 us
DOM translation time:    197.201 us

Design:
  Libraries:
    - Name: pretty
      Entities:
      Packages:
      Configurations:
      Contexts:
  Documents:
    - Path: '/home/runner/work/extended-tests/extended-tests/ghdl-cosim/vhpidirect/vffi_user-body.vhd':
      Entities:
      Architectures:
      Packages:
      PackageBodies:
        - Name: vffi_user
          Declared:
          - function reverseBitsInBytes return std_logic_vector
      Configurations:
      Contexts:

Teardown

XPASS test_AllVHDLSources[/home/runner/work/extended-tests/extended-tests/ghdl-cosim/vhpidirect/vffi_user.vhd] 0:00:00.372299

Started 2021-11-23 15:22:07
Ended 2021-11-23 15:22:08
Duration 0:00:00.372299
Markers
xfail
Fixtures file

Setup

Call

Captured stdout call
================================================================================
                         pyGHDL.dom - Test Application                          
================================================================================
Parsing file '/home/runner/work/extended-tests/extended-tests/ghdl-cosim/vhpidirect/vffi_user.vhd'
[NOT IMPLEMENTED] function declaration without body
libghdl processing time:  46.200 us
DOM translation time:    132.801 us

Design:
  Libraries:
    - Name: pretty
      Entities:
      Packages:
        - vffi_user
      Configurations:
      Contexts:
  Documents:
    - Path: '/home/runner/work/extended-tests/extended-tests/ghdl-cosim/vhpidirect/vffi_user.vhd':
      Entities:
      Architectures:
      Packages:
        - Name: vffi_user
          File: vffi_user.vhd
          Position: 4:8
          Declared:
      PackageBodies:
      Configurations:
      Contexts:

Teardown

XPASS test_AllVHDLSources[/home/runner/work/extended-tests/extended-tests/ghdl-cosim/vhpidirect/grt/step/tb.vhd] 0:00:00.248733

Started 2021-11-23 15:22:08
Ended 2021-11-23 15:22:08
Duration 0:00:00.248733
Markers
xfail
Fixtures file

Setup

Call

Captured stdout call
================================================================================
                         pyGHDL.dom - Test Application                          
================================================================================
Parsing file '/home/runner/work/extended-tests/extended-tests/ghdl-cosim/vhpidirect/grt/step/tb.vhd'
[NOT IMPLEMENTED] Variable assignment (label: 'None') at line 11
libghdl processing time:  58.501 us
DOM translation time:    732.704 us

Design:
  Libraries:
    - Name: pretty
      Entities:
        - tb(arch)
      Packages:
      Configurations:
      Contexts:
  Documents:
    - Path: '/home/runner/work/extended-tests/extended-tests/ghdl-cosim/vhpidirect/grt/step/tb.vhd':
      Entities:
        - Name: tb
          File: tb.vhd
          Position: 1:7
          Generics:
          Ports:
          Declared:
          Statements:
          Architecures:
          - arch
      Architectures:
        - Name: arch
          File: tb.vhd
          Position: 4:13
          Entity: tb
          Declared:
          Hierarchy:
            - None: process(...)
          Statements:
            ...
      Packages:
      PackageBodies:
      Configurations:
      Contexts:

Teardown

XPASS test_AllVHDLSources[/home/runner/work/extended-tests/extended-tests/ghdl-cosim/vhpidirect/vffi_user/xyce/runACircuitInSteps/tb_xyce.vhd] 0:00:00.246917

Started 2021-11-23 15:22:08
Ended 2021-11-23 15:22:08
Duration 0:00:00.246917
Markers
xfail
Fixtures file

Setup

Call

Captured stdout call
================================================================================
                         pyGHDL.dom - Test Application                          
================================================================================
Parsing file '/home/runner/work/extended-tests/extended-tests/ghdl-cosim/vhpidirect/vffi_user/xyce/runACircuitInSteps/tb_xyce.vhd'
libghdl processing time:  99.300 us
DOM translation time:    1213.008 us

Design:
  Libraries:
    - Name: pretty
      Entities:
        - tb_xyce_eg_in_steps(tb)
      Packages:
      Configurations:
      Contexts:
  Documents:
    - Path: '/home/runner/work/extended-tests/extended-tests/ghdl-cosim/vhpidirect/vffi_user/xyce/runACircuitInSteps/tb_xyce.vhd':
      Entities:
        - Name: tb_xyce_eg_in_steps
          File: tb_xyce.vhd
          Position: 6:7
          Generics:
            - runner_cfg : in string
            - tb_path : in string
            - circuit : in string := "../circuit.cir"
          Ports:
          Declared:
          Statements:
          Architecures:
          - tb
      Architectures:
        - Name: tb
          File: tb_xyce.vhd
          Position: 14:13
          Entity: tb_xyce_eg_in_steps
          Declared:
          Hierarchy:
            - main: process(...)
          Statements:
            ...
      Packages:
      PackageBodies:
      Configurations:
      Contexts:

Teardown

XPASS test_AllVHDLSources[/home/runner/work/extended-tests/extended-tests/ghdl-cosim/vhpidirect/vffi_user/xyce/pkg/xyce_pkg-body.vhd] 0:00:00.244962

Started 2021-11-23 15:22:08
Ended 2021-11-23 15:22:08
Duration 0:00:00.244962
Markers
xfail
Fixtures file

Setup

Call

Captured stdout call
================================================================================
                         pyGHDL.dom - Test Application                          
================================================================================
Parsing file '/home/runner/work/extended-tests/extended-tests/ghdl-cosim/vhpidirect/vffi_user/xyce/pkg/xyce_pkg-body.vhd'
libghdl processing time:  158.801 us
DOM translation time:    782.705 us

Design:
  Libraries:
    - Name: pretty
      Entities:
      Packages:
      Configurations:
      Contexts:
  Documents:
    - Path: '/home/runner/work/extended-tests/extended-tests/ghdl-cosim/vhpidirect/vffi_user/xyce/pkg/xyce_pkg-body.vhd':
      Entities:
      Architectures:
      Packages:
      PackageBodies:
        - Name: xyce_pkg
          Declared:
          - type xyce_t is protected body ..... end protected body
      Configurations:
      Contexts:

Teardown

XPASS test_AllVHDLSources[/home/runner/work/extended-tests/extended-tests/ghdl-cosim/vhpidirect/vffi_user/xyce/pkg/xyce_pkg.vhd] 0:00:00.247426

Started 2021-11-23 15:22:08
Ended 2021-11-23 15:22:08
Duration 0:00:00.247426
Markers
xfail
Fixtures file

Setup

Call

Captured stdout call
================================================================================
                         pyGHDL.dom - Test Application                          
================================================================================
Parsing file '/home/runner/work/extended-tests/extended-tests/ghdl-cosim/vhpidirect/vffi_user/xyce/pkg/xyce_pkg.vhd'
libghdl processing time:  64.200 us
DOM translation time:    584.304 us

Design:
  Libraries:
    - Name: pretty
      Entities:
      Packages:
        - xyce_pkg
      Configurations:
      Contexts:
  Documents:
    - Path: '/home/runner/work/extended-tests/extended-tests/ghdl-cosim/vhpidirect/vffi_user/xyce/pkg/xyce_pkg.vhd':
      Entities:
      Architectures:
      Packages:
        - Name: xyce_pkg
          File: xyce_pkg.vhd
          Position: 3:8
          Declared:
          - alias arr2D_t is ?????
          - type xyce_t is protected ..... end protected
      PackageBodies:
      Configurations:
      Contexts:

Teardown

XPASS test_AllVHDLSources[/home/runner/work/extended-tests/extended-tests/ghdl-cosim/vhpidirect/vffi_user/xyce/pkg/xyce_xhdl_pkg.vhd] 0:00:00.250134

Started 2021-11-23 15:22:08
Ended 2021-11-23 15:22:08
Duration 0:00:00.250134
Markers
xfail
Fixtures file

Setup

Call

Captured stdout call
================================================================================
                         pyGHDL.dom - Test Application                          
================================================================================
Parsing file '/home/runner/work/extended-tests/extended-tests/ghdl-cosim/vhpidirect/vffi_user/xyce/pkg/xyce_xhdl_pkg.vhd'
[NOT IMPLEMENTED] function declaration without body
[NOT IMPLEMENTED] function declaration without body
[NOT IMPLEMENTED] function declaration without body
[NOT IMPLEMENTED] Signature name in attribute specifications.
[NOT IMPLEMENTED] function declaration without body
[NOT IMPLEMENTED] Signature name in attribute specifications.
[NOT IMPLEMENTED] function declaration without body
[NOT IMPLEMENTED] procedure declaration without body
libghdl processing time:  141.501 us
DOM translation time:    778.305 us

Design:
  Libraries:
    - Name: pretty
      Entities:
      Packages:
        - xyce_xhdl_pkg
      Configurations:
      Contexts:
  Documents:
    - Path: '/home/runner/work/extended-tests/extended-tests/ghdl-cosim/vhpidirect/vffi_user/xyce/pkg/xyce_xhdl_pkg.vhd':
      Entities:
      Architectures:
      Packages:
        - Name: xyce_xhdl_pkg
          File: xyce_xhdl_pkg.vhd
          Position: 1:8
          Declared:
          - attribute foreign of ???? : ???? is ????
          - attribute foreign of ???? : ???? is ????
          - attribute foreign of ???? : ???? is ????
          - type arr2D_t is array(........) of .....
          - attribute foreign of ???? : ???? is ????
          - attribute foreign of ???? : ???? is ????
          - attribute foreign of ???? : ???? is ????
      PackageBodies:
      Configurations:
      Contexts:

Teardown

XPASS test_AllVHDLSources[/home/runner/work/extended-tests/extended-tests/ghdl-cosim/vhpidirect/vffi_user/xyce/pkg/xyce_xhdl_pkg-body.vhd] 0:00:00.251232

Started 2021-11-23 15:22:08
Ended 2021-11-23 15:22:08
Duration 0:00:00.251232
Markers
xfail
Fixtures file

Setup

Call

Captured stdout call
================================================================================
                         pyGHDL.dom - Test Application                          
================================================================================
Parsing file '/home/runner/work/extended-tests/extended-tests/ghdl-cosim/vhpidirect/vffi_user/xyce/pkg/xyce_xhdl_pkg-body.vhd'
libghdl processing time:  133.801 us
DOM translation time:    702.504 us

Design:
  Libraries:
    - Name: pretty
      Entities:
      Packages:
      Configurations:
      Contexts:
  Documents:
    - Path: '/home/runner/work/extended-tests/extended-tests/ghdl-cosim/vhpidirect/vffi_user/xyce/pkg/xyce_xhdl_pkg-body.vhd':
      Entities:
      Architectures:
      Packages:
      PackageBodies:
        - Name: xyce_xhdl_pkg
          Declared:
          - function xyce_init return integer
          - function xyce_run return integer
          - function xyce_run return integer
          - function xyce_run return integer
          - function xyce_read return real
          - procedure xyce_close
      Configurations:
      Contexts:

Teardown

XPASS test_AllVHDLSources[/home/runner/work/extended-tests/extended-tests/ghdl-cosim/vhpidirect/vffi_user/xyce/runWithDACs/tb_xyce_1D.vhd] 0:00:00.242903

Started 2021-11-23 15:22:08
Ended 2021-11-23 15:22:09
Duration 0:00:00.242903
Markers
xfail
Fixtures file

Setup

Call

Captured stdout call
================================================================================
                         pyGHDL.dom - Test Application                          
================================================================================
Parsing file '/home/runner/work/extended-tests/extended-tests/ghdl-cosim/vhpidirect/vffi_user/xyce/runWithDACs/tb_xyce_1D.vhd'
libghdl processing time:  183.202 us
DOM translation time:    1701.210 us

Design:
  Libraries:
    - Name: pretty
      Entities:
        - tb_xyce_eg_with_dacs_1D(tb)
      Packages:
      Configurations:
      Contexts:
  Documents:
    - Path: '/home/runner/work/extended-tests/extended-tests/ghdl-cosim/vhpidirect/vffi_user/xyce/runWithDACs/tb_xyce_1D.vhd':
      Entities:
        - Name: tb_xyce_eg_with_dacs_1D
          File: tb_xyce_1D.vhd
          Position: 6:7
          Generics:
            - runner_cfg : in string
            - tb_path : in string
            - circuit : in string := "../circuit_DACs.cir"
          Ports:
          Declared:
          Statements:
          Architecures:
          - tb
      Architectures:
        - Name: tb
          File: tb_xyce_1D.vhd
          Position: 14:13
          Entity: tb_xyce_eg_with_dacs_1D
          Declared:
          Hierarchy:
            - main: process(...)
          Statements:
            ...
      Packages:
      PackageBodies:
      Configurations:
      Contexts:

Teardown

XPASS test_AllVHDLSources[/home/runner/work/extended-tests/extended-tests/ghdl-cosim/vhpidirect/vffi_user/xyce/runWithDACs/tb_xyce_2D.vhd] 0:00:00.246148

Started 2021-11-23 15:22:08
Ended 2021-11-23 15:22:09
Duration 0:00:00.246148
Markers
xfail
Fixtures file

Setup

Call

Captured stdout call
================================================================================
                         pyGHDL.dom - Test Application                          
================================================================================
Parsing file '/home/runner/work/extended-tests/extended-tests/ghdl-cosim/vhpidirect/vffi_user/xyce/runWithDACs/tb_xyce_2D.vhd'
libghdl processing time:  171.601 us
DOM translation time:    1551.709 us

Design:
  Libraries:
    - Name: pretty
      Entities:
        - tb_xyce_eg_with_dacs_2D(tb)
      Packages:
      Configurations:
      Contexts:
  Documents:
    - Path: '/home/runner/work/extended-tests/extended-tests/ghdl-cosim/vhpidirect/vffi_user/xyce/runWithDACs/tb_xyce_2D.vhd':
      Entities:
        - Name: tb_xyce_eg_with_dacs_2D
          File: tb_xyce_2D.vhd
          Position: 7:7
          Generics:
            - runner_cfg : in string
            - tb_path : in string
            - circuit : in string := "../circuit_DACs.cir"
          Ports:
          Declared:
          Statements:
          Architecures:
          - tb
      Architectures:
        - Name: tb
          File: tb_xyce_2D.vhd
          Position: 15:13
          Entity: tb_xyce_eg_with_dacs_2D
          Declared:
          Hierarchy:
            - main: process(...)
          Statements:
            ...
      Packages:
      PackageBodies:
      Configurations:
      Contexts:

Teardown

XPASS test_AllVHDLSources[/home/runner/work/extended-tests/extended-tests/ghdl-cosim/vhpidirect/vffi_user/xyce/runACircuit/tb_xyce.vhd] 0:00:00.257854

Started 2021-11-23 15:22:09
Ended 2021-11-23 15:22:09
Duration 0:00:00.257854
Markers
xfail
Fixtures file

Setup

Call

Captured stdout call
================================================================================
                         pyGHDL.dom - Test Application                          
================================================================================
Parsing file '/home/runner/work/extended-tests/extended-tests/ghdl-cosim/vhpidirect/vffi_user/xyce/runACircuit/tb_xyce.vhd'
libghdl processing time:  176.601 us
DOM translation time:    942.905 us

Design:
  Libraries:
    - Name: pretty
      Entities:
        - tb_xyce_eg_minimal(tb)
      Packages:
      Configurations:
      Contexts:
  Documents:
    - Path: '/home/runner/work/extended-tests/extended-tests/ghdl-cosim/vhpidirect/vffi_user/xyce/runACircuit/tb_xyce.vhd':
      Entities:
        - Name: tb_xyce_eg_minimal
          File: tb_xyce.vhd
          Position: 4:7
          Generics:
            - runner_cfg : in string
            - tb_path : in string
          Ports:
          Declared:
          Statements:
          Architecures:
          - tb
      Architectures:
        - Name: tb
          File: tb_xyce.vhd
          Position: 11:13
          Entity: tb_xyce_eg_minimal
          Declared:
            - function xyce return integer
            - attribute foreign of ???? : ???? is ????
          Hierarchy:
            - main: process(...)
          Statements:
            ...
      Packages:
      PackageBodies:
      Configurations:
      Contexts:

Teardown

XPASS test_AllVHDLSources[/home/runner/work/extended-tests/extended-tests/ghdl-cosim/vhpidirect/vffi_user/crypto/c/tb.vhd] 0:00:00.251874

Started 2021-11-23 15:22:09
Ended 2021-11-23 15:22:09
Duration 0:00:00.251874
Markers
xfail
Fixtures file

Setup

Call

Captured stdout call
================================================================================
                         pyGHDL.dom - Test Application                          
================================================================================
Parsing file '/home/runner/work/extended-tests/extended-tests/ghdl-cosim/vhpidirect/vffi_user/crypto/c/tb.vhd'
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
libghdl processing time:  176.502 us
DOM translation time:    1647.210 us

Design:
  Libraries:
    - Name: pretty
      Entities:
        - tb(arch)
      Packages:
      Configurations:
      Contexts:
  Documents:
    - Path: '/home/runner/work/extended-tests/extended-tests/ghdl-cosim/vhpidirect/vffi_user/crypto/c/tb.vhd':
      Entities:
        - Name: tb
          File: tb.vhd
          Position: 7:7
          Generics:
          Ports:
          Declared:
          Statements:
          Architecures:
          - arch
      Architectures:
        - Name: arch
          File: tb.vhd
          Position: 10:13
          Entity: tb
          Declared:
          Hierarchy:
            - None: process(...)
          Statements:
            ...
      Packages:
      PackageBodies:
      Configurations:
      Contexts:

Teardown

XPASS test_AllVHDLSources[/home/runner/work/extended-tests/extended-tests/ghdl-cosim/vhpidirect/vffi_user/demo/accessesFromVhdlToC.vhd] 0:00:00.244828

Started 2021-11-23 15:22:09
Ended 2021-11-23 15:22:09
Duration 0:00:00.244828
Markers
xfail
Fixtures file

Setup

Call

Captured stdout call
================================================================================
                         pyGHDL.dom - Test Application                          
================================================================================
Parsing file '/home/runner/work/extended-tests/extended-tests/ghdl-cosim/vhpidirect/vffi_user/demo/accessesFromVhdlToC.vhd'
libghdl processing time:  104.500 us
DOM translation time:    642.304 us

Design:
  Libraries:
    - Name: pretty
      Entities:
        - tb_AccessesFromVhdlToC(arch)
      Packages:
      Configurations:
      Contexts:
  Documents:
    - Path: '/home/runner/work/extended-tests/extended-tests/ghdl-cosim/vhpidirect/vffi_user/demo/accessesFromVhdlToC.vhd':
      Entities:
        - Name: tb_AccessesFromVhdlToC
          File: accessesFromVhdlToC.vhd
          Position: 5:7
          Generics:
          Ports:
          Declared:
          Statements:
          Architecures:
          - arch
      Architectures:
        - Name: arch
          File: accessesFromVhdlToC.vhd
          Position: 8:13
          Entity: tb_AccessesFromVhdlToC
          Declared:
            - type int_natural1D_t is array(........) of .....
          Hierarchy:
            - None: process(...)
          Statements:
            ...
      Packages:
      PackageBodies:
      Configurations:
      Contexts:

Teardown

XFAIL test_AllVHDLSources[/home/runner/work/extended-tests/extended-tests/ghdl-cosim/vhpidirect/vffi_user/demo/accessesFromCToVhdl.vhd] 0:00:00.250090

Started 2021-11-23 15:22:09
Ended 2021-11-23 15:22:09
Duration 0:00:00.250090
Markers
xfail
Fixtures file

Setup

Call 

[gw1] linux -- Python 3.9.8 /opt/hostedtoolcache/Python/3.9.8/x64/bin/python

file = '/home/runner/work/extended-tests/extended-tests/ghdl-cosim/vhpidirect/vffi_user/demo/accessesFromCToVhdl.vhd'

    @mark.parametrize(
    	"file",
    	getVHDLSources()
    )
    @mark.xfail
    def test_AllVHDLSources(file):
>   	check_call(['ghdl-dom', 'pretty', '-f', str(file)], stderr=STDOUT)

TestDOM.py:25: 
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ 

popenargs = (['ghdl-dom', 'pretty', '-f', '/home/runner/work/extended-tests/extended-tests/ghdl-cosim/vhpidirect/vffi_user/demo/accessesFromCToVhdl.vhd'],)
kwargs = {'stderr': -2}, retcode = 6
cmd = ['ghdl-dom', 'pretty', '-f', '/home/runner/work/extended-tests/extended-tests/ghdl-cosim/vhpidirect/vffi_user/demo/accessesFromCToVhdl.vhd']

    def check_call(*popenargs, **kwargs):
        """Run command with arguments.  Wait for command to complete.  If
        the exit code was zero then return, otherwise raise
        CalledProcessError.  The CalledProcessError object will have the
        return code in the returncode attribute.
    
        The arguments are the same as for the call function.  Example:
    
        check_call(["ls", "-l"])
        """
        retcode = call(*popenargs, **kwargs)
        if retcode:
            cmd = kwargs.get("args")
            if cmd is None:
                cmd = popenargs[0]
>           raise CalledProcessError(retcode, cmd)
E           subprocess.CalledProcessError: Command '['ghdl-dom', 'pretty', '-f', '/home/runner/work/extended-tests/extended-tests/ghdl-cosim/vhpidirect/vffi_user/demo/accessesFromCToVhdl.vhd']' returned non-zero exit status 6.

/opt/hostedtoolcache/Python/3.9.8/x64/lib/python3.9/subprocess.py:373: CalledProcessError
Captured stdout call
================================================================================
                         pyGHDL.dom - Test Application                          
================================================================================
Parsing file '/home/runner/work/extended-tests/extended-tests/ghdl-cosim/vhpidirect/vffi_user/demo/accessesFromCToVhdl.vhd'
DOM: Unknown expression kind 'Selected_By_All_Name' in expression '1332' at /home/runner/work/extended-tests/extended-tests/ghdl-cosim/vhpidirect/vffi_user/demo/accessesFromCToVhdl.vhd:27:33.

Teardown

XPASS test_AllVHDLSources[/home/runner/work/extended-tests/extended-tests/ghdl-cosim/vhpidirect/vffi_user/demo/valuesFromVhdlToC.vhd] 0:00:00.249712

Started 2021-11-23 15:22:09
Ended 2021-11-23 15:22:09
Duration 0:00:00.249712
Markers
xfail
Fixtures file

Setup

Call

Captured stdout call
================================================================================
                         pyGHDL.dom - Test Application                          
================================================================================
Parsing file '/home/runner/work/extended-tests/extended-tests/ghdl-cosim/vhpidirect/vffi_user/demo/valuesFromVhdlToC.vhd'
libghdl processing time:  277.402 us
DOM translation time:    4663.628 us

Design:
  Libraries:
    - Name: pretty
      Entities:
        - tb_valuesFromVhdlToC(arch)
      Packages:
      Configurations:
      Contexts:
  Documents:
    - Path: '/home/runner/work/extended-tests/extended-tests/ghdl-cosim/vhpidirect/vffi_user/demo/valuesFromVhdlToC.vhd':
      Entities:
        - Name: tb_valuesFromVhdlToC
          File: valuesFromVhdlToC.vhd
          Position: 5:7
          Generics:
          Ports:
          Declared:
          Statements:
          Architecures:
          - arch
      Architectures:
        - Name: arch
          File: valuesFromVhdlToC.vhd
          Position: 8:13
          Entity: tb_valuesFromVhdlToC
          Declared:
            - type rec_t is record ..... end record
            - type enum_t is (........)
            - type int_natural1D_t is array(........) of .....
            - type real_natural1D_t is array(........) of .....
            - type bool_natural1D_t is array(........) of .....
            - type time_natural1D_t is array(........) of .....
            - type rec_natural1D_t is array(........) of .....
            - type enum_natural1D_t is array(........) of .....
            - type real_natural2D_t is array(........) of .....
          Hierarchy:
            - None: process(...)
          Statements:
            ...
      Packages:
      PackageBodies:
      Configurations:
      Contexts:

Teardown

XPASS test_AllVHDLSources[/home/runner/work/extended-tests/extended-tests/ghdl-cosim/vhpidirect/shared/shghdl/tb.vhd] 0:00:00.246387

Started 2021-11-23 15:22:09
Ended 2021-11-23 15:22:09
Duration 0:00:00.246387
Markers
xfail
Fixtures file

Setup

Call

Captured stdout call
================================================================================
                         pyGHDL.dom - Test Application                          
================================================================================
Parsing file '/home/runner/work/extended-tests/extended-tests/ghdl-cosim/vhpidirect/shared/shghdl/tb.vhd'
libghdl processing time:  37.200 us
DOM translation time:    342.202 us

Design:
  Libraries:
    - Name: pretty
      Entities:
        - tb(arch)
      Packages:
      Configurations:
      Contexts:
  Documents:
    - Path: '/home/runner/work/extended-tests/extended-tests/ghdl-cosim/vhpidirect/shared/shghdl/tb.vhd':
      Entities:
        - Name: tb
          File: tb.vhd
          Position: 1:7
          Generics:
          Ports:
          Declared:
          Statements:
          Architecures:
          - arch
      Architectures:
        - Name: arch
          File: tb.vhd
          Position: 4:13
          Entity: tb
          Declared:
          Hierarchy:
            - None: process(...)
          Statements:
            ...
      Packages:
      PackageBodies:
      Configurations:
      Contexts:

Teardown

XPASS test_AllVHDLSources[/home/runner/work/extended-tests/extended-tests/ghdl-cosim/vhpidirect/shared/shlib/tb.vhd] 0:00:00.246643

Started 2021-11-23 15:22:09
Ended 2021-11-23 15:22:10
Duration 0:00:00.246643
Markers
xfail
Fixtures file

Setup

Call

Captured stdout call
================================================================================
                         pyGHDL.dom - Test Application                          
================================================================================
Parsing file '/home/runner/work/extended-tests/extended-tests/ghdl-cosim/vhpidirect/shared/shlib/tb.vhd'
libghdl processing time:  83.901 us
DOM translation time:    565.803 us

Design:
  Libraries:
    - Name: pretty
      Entities:
        - tb(arch)
      Packages:
      Configurations:
      Contexts:
  Documents:
    - Path: '/home/runner/work/extended-tests/extended-tests/ghdl-cosim/vhpidirect/shared/shlib/tb.vhd':
      Entities:
        - Name: tb
          File: tb.vhd
          Position: 1:7
          Generics:
          Ports:
          Declared:
          Statements:
          Architecures:
          - arch
      Architectures:
        - Name: arch
          File: tb.vhd
          Position: 4:13
          Entity: tb
          Declared:
            - function get_rand return integer
            - attribute foreign of ???? : ???? is ????
          Hierarchy:
            - None: process(...)
          Statements:
            ...
      Packages:
      PackageBodies:
      Configurations:
      Contexts:

Teardown

XPASS test_AllVHDLSources[/home/runner/work/extended-tests/extended-tests/ghdl-cosim/vhpidirect/shared/pycb/pyghdl/tb.vhd] 0:00:00.249844

Started 2021-11-23 15:22:09
Ended 2021-11-23 15:22:10
Duration 0:00:00.249844
Markers
xfail
Fixtures file

Setup

Call

Captured stdout call
================================================================================
                         pyGHDL.dom - Test Application                          
================================================================================
Parsing file '/home/runner/work/extended-tests/extended-tests/ghdl-cosim/vhpidirect/shared/pycb/pyghdl/tb.vhd'
[NOT IMPLEMENTED] Array_Subtype_Definition
libghdl processing time:  98.401 us
DOM translation time:    866.105 us

Design:
  Libraries:
    - Name: pretty
      Entities:
        - tb(arch)
      Packages:
      Configurations:
      Contexts:
  Documents:
    - Path: '/home/runner/work/extended-tests/extended-tests/ghdl-cosim/vhpidirect/shared/pycb/pyghdl/tb.vhd':
      Entities:
        - Name: tb
          File: tb.vhd
          Position: 1:7
          Generics:
          Ports:
          Declared:
          Statements:
          Architecures:
          - arch
      Architectures:
        - Name: arch
          File: tb.vhd
          Position: 4:13
          Entity: tb
          Declared:
            - type ???? is array(........) of .....
            - procedure plot
            - attribute foreign of ???? : ???? is ????
            - constant x : arr_t := (1, 2, 3, 4, 5)
            - constant y : arr_t := (11, 2, 38, 45, 57)
          Hierarchy:
            - None: process(...)
          Statements:
            ...
      Packages:
      PackageBodies:
      Configurations:
      Contexts:

Teardown

XPASS test_AllVHDLSources[/home/runner/work/extended-tests/extended-tests/ghdl-cosim/vhpidirect/shared/py/vunit/tb.vhd] 0:00:00.253599

Started 2021-11-23 15:22:10
Ended 2021-11-23 15:22:10
Duration 0:00:00.253599
Markers
xfail
Fixtures file

Setup

Call

Captured stdout call
================================================================================
                         pyGHDL.dom - Test Application                          
================================================================================
Parsing file '/home/runner/work/extended-tests/extended-tests/ghdl-cosim/vhpidirect/shared/py/vunit/tb.vhd'
libghdl processing time:  81.700 us
DOM translation time:    757.505 us

Design:
  Libraries:
    - Name: pretty
      Entities:
        - tb_vunit(tb)
      Packages:
      Configurations:
      Contexts:
  Documents:
    - Path: '/home/runner/work/extended-tests/extended-tests/ghdl-cosim/vhpidirect/shared/py/vunit/tb.vhd':
      Entities:
        - Name: tb_vunit
          File: tb.vhd
          Position: 5:7
          Generics:
            - runner_cfg : in string
          Ports:
          Declared:
          Statements:
          Architecures:
          - tb
      Architectures:
        - Name: tb
          File: tb.vhd
          Position: 9:13
          Entity: tb_vunit
          Declared:
          Hierarchy:
            - main: process(...)
          Statements:
            ...
      Packages:
      PackageBodies:
      Configurations:
      Contexts:

Teardown

XPASS test_AllVHDLSources[/home/runner/work/extended-tests/extended-tests/ghdl-cosim/vhpidirect/arrays/logicvector/tb.vhd] 0:00:00.259078

Started 2021-11-23 15:22:10
Ended 2021-11-23 15:22:10
Duration 0:00:00.259078
Markers
xfail
Fixtures file

Setup

Call

Captured stdout call
================================================================================
                         pyGHDL.dom - Test Application                          
================================================================================
Parsing file '/home/runner/work/extended-tests/extended-tests/ghdl-cosim/vhpidirect/arrays/logicvector/tb.vhd'
libghdl processing time:  235.602 us
DOM translation time:    1960.612 us

Design:
  Libraries:
    - Name: pretty
      Entities:
        - tb(arch)
      Packages:
      Configurations:
      Contexts:
  Documents:
    - Path: '/home/runner/work/extended-tests/extended-tests/ghdl-cosim/vhpidirect/arrays/logicvector/tb.vhd':
      Entities:
        - Name: tb
          File: tb.vhd
          Position: 4:7
          Generics:
          Ports:
          Declared:
          Statements:
          Architecures:
          - arch
      Architectures:
        - Name: arch
          File: tb.vhd
          Position: 7:13
          Entity: tb
          Declared:
          Hierarchy:
            - None: process(...)
          Statements:
            ...
      Packages:
      PackageBodies:
      Configurations:
      Contexts:

Teardown

XPASS test_AllVHDLSources[/home/runner/work/extended-tests/extended-tests/ghdl-cosim/vhpidirect/arrays/intvector/vhdlsized/tb.vhd] 0:00:00.256699

Started 2021-11-23 15:22:10
Ended 2021-11-23 15:22:10
Duration 0:00:00.256699
Markers
xfail
Fixtures file

Setup

Call

Captured stdout call
================================================================================
                         pyGHDL.dom - Test Application                          
================================================================================
Parsing file '/home/runner/work/extended-tests/extended-tests/ghdl-cosim/vhpidirect/arrays/intvector/vhdlsized/tb.vhd'
libghdl processing time:  148.800 us
DOM translation time:    2022.213 us

Design:
  Libraries:
    - Name: pretty
      Entities:
        - tb(vhdlallocarr, vhdlallocacc, calloc)
      Packages:
      Configurations:
      Contexts:
  Documents:
    - Path: '/home/runner/work/extended-tests/extended-tests/ghdl-cosim/vhpidirect/arrays/intvector/vhdlsized/tb.vhd':
      Entities:
        - Name: tb
          File: tb.vhd
          Position: 3:7
          Generics:
          Ports:
          Declared:
          Statements:
          Architecures:
          - vhdlallocarr
          - vhdlallocacc
          - calloc
      Architectures:
        - Name: vhdlallocarr
          File: tb.vhd
          Position: 7:13
          Entity: tb
          Declared:
          Hierarchy:
            - None: process(...)
          Statements:
            ...
        - Name: vhdlallocacc
          File: tb.vhd
          Position: 31:13
          Entity: tb
          Declared:
          Hierarchy:
            - None: process(...)
          Statements:
            ...
        - Name: calloc
          File: tb.vhd
          Position: 57:13
          Entity: tb
          Declared:
          Hierarchy:
            - None: process(...)
          Statements:
            ...
      Packages:
      PackageBodies:
      Configurations:
      Contexts:

Teardown

XPASS test_AllVHDLSources[/home/runner/work/extended-tests/extended-tests/ghdl-cosim/vhpidirect/arrays/intvector/vhdlsized/pkg.vhd] 0:00:00.251463

Started 2021-11-23 15:22:10
Ended 2021-11-23 15:22:10
Duration 0:00:00.251463
Markers
xfail
Fixtures file

Setup

Call

Captured stdout call
================================================================================
                         pyGHDL.dom - Test Application                          
================================================================================
Parsing file '/home/runner/work/extended-tests/extended-tests/ghdl-cosim/vhpidirect/arrays/intvector/vhdlsized/pkg.vhd'
[NOT IMPLEMENTED] Array_Subtype_Definition
[NOT IMPLEMENTED] procedure declaration without body
[NOT IMPLEMENTED] procedure declaration without body
[NOT IMPLEMENTED] procedure declaration without body
[NOT IMPLEMENTED] procedure declaration without body
[NOT IMPLEMENTED] function declaration without body
[NOT IMPLEMENTED] procedure declaration without body
libghdl processing time:  146.001 us
DOM translation time:    1119.607 us

Design:
  Libraries:
    - Name: pretty
      Entities:
      Packages:
        - pkg
      Configurations:
      Contexts:
  Documents:
    - Path: '/home/runner/work/extended-tests/extended-tests/ghdl-cosim/vhpidirect/arrays/intvector/vhdlsized/pkg.vhd':
      Entities:
      Architectures:
      Packages:
        - Name: pkg
          File: pkg.vhd
          Position: 1:8
          Declared:
          - type ???? is array(........) of .....
          - type int_arr_ptr is access .....
          - attribute foreign of ???? : ???? is ????
          - attribute foreign of ???? : ???? is ????
          - attribute foreign of ???? : ???? is ????
          - attribute foreign of ???? : ???? is ????
          - attribute foreign of ???? : ???? is ????
          - attribute foreign of ???? : ???? is ????
      PackageBodies:
        - Name: pkg
          Declared:
          - procedure c_initIntArrOut
          - procedure c_checkAndPrintIntArrOut
          - procedure c_initIntArr
          - procedure c_checkAndPrintIntArr
          - function c_allocIntArr return int_arr_ptr
          - procedure c_freePointer
      Configurations:
      Contexts:

Teardown

XPASS test_AllVHDLSources[/home/runner/work/extended-tests/extended-tests/ghdl-cosim/vhpidirect/arrays/intvector/csized/fcn/tb.vhd] 0:00:00.250443

Started 2021-11-23 15:22:10
Ended 2021-11-23 15:22:10
Duration 0:00:00.250443
Markers
xfail
Fixtures file

Setup

Call

Captured stdout call
================================================================================
                         pyGHDL.dom - Test Application                          
================================================================================
Parsing file '/home/runner/work/extended-tests/extended-tests/ghdl-cosim/vhpidirect/arrays/intvector/csized/fcn/tb.vhd'
[NOT IMPLEMENTED] Array_Subtype_Definition
libghdl processing time:  110.201 us
DOM translation time:    891.905 us

Design:
  Libraries:
    - Name: pretty
      Entities:
        - tb(arch)
      Packages:
      Configurations:
      Contexts:
  Documents:
    - Path: '/home/runner/work/extended-tests/extended-tests/ghdl-cosim/vhpidirect/arrays/intvector/csized/fcn/tb.vhd':
      Entities:
        - Name: tb
          File: tb.vhd
          Position: 1:7
          Generics:
          Ports:
          Declared:
          Statements:
          Architecures:
          - arch
      Architectures:
        - Name: arch
          File: tb.vhd
          Position: 4:13
          Entity: tb
          Declared:
          Hierarchy:
            - None: process(...)
          Statements:
            ...
      Packages:
      PackageBodies:
      Configurations:
      Contexts:

Teardown

XPASS test_AllVHDLSources[/home/runner/work/extended-tests/extended-tests/ghdl-cosim/vhpidirect/arrays/intvector/csized/proc/tb.vhd] 0:00:00.248578

Started 2021-11-23 15:22:10
Ended 2021-11-23 15:22:10
Duration 0:00:00.248578
Markers
xfail
Fixtures file

Setup

Call

Captured stdout call
================================================================================
                         pyGHDL.dom - Test Application                          
================================================================================
Parsing file '/home/runner/work/extended-tests/extended-tests/ghdl-cosim/vhpidirect/arrays/intvector/csized/proc/tb.vhd'
[NOT IMPLEMENTED] Array_Subtype_Definition
libghdl processing time:  118.601 us
DOM translation time:    819.005 us

Design:
  Libraries:
    - Name: pretty
      Entities:
        - tb(arch)
      Packages:
      Configurations:
      Contexts:
  Documents:
    - Path: '/home/runner/work/extended-tests/extended-tests/ghdl-cosim/vhpidirect/arrays/intvector/csized/proc/tb.vhd':
      Entities:
        - Name: tb
          File: tb.vhd
          Position: 1:7
          Generics:
          Ports:
          Declared:
          Statements:
          Architecures:
          - arch
      Architectures:
        - Name: arch
          File: tb.vhd
          Position: 4:13
          Entity: tb
          Declared:
          Hierarchy:
            - None: process(...)
          Statements:
            ...
      Packages:
      PackageBodies:
      Configurations:
      Contexts:

Teardown

XPASS test_AllVHDLSources[/home/runner/work/extended-tests/extended-tests/ghdl-cosim/vhpidirect/arrays/matrices/tb.vhd] 0:00:00.248081

Started 2021-11-23 15:22:10
Ended 2021-11-23 15:22:11
Duration 0:00:00.248081
Markers
xfail
Fixtures file

Setup

Call

Captured stdout call
================================================================================
                         pyGHDL.dom - Test Application                          
================================================================================
Parsing file '/home/runner/work/extended-tests/extended-tests/ghdl-cosim/vhpidirect/arrays/matrices/tb.vhd'
libghdl processing time:  137.801 us
DOM translation time:    1111.907 us

Design:
  Libraries:
    - Name: pretty
      Entities:
        - tb(arch)
      Packages:
        - fixed_pkg instantiate from 1297
      Configurations:
      Contexts:
  Documents:
    - Path: '/home/runner/work/extended-tests/extended-tests/ghdl-cosim/vhpidirect/arrays/matrices/tb.vhd':
      Entities:
        - Name: tb
          File: tb.vhd
          Position: 11:7
          Generics:
          Ports:
          Declared:
          Statements:
          Architecures:
          - arch
      Architectures:
        - Name: arch
          File: tb.vhd
          Position: 14:13
          Entity: tb
          Declared:
          Hierarchy:
            - None: process(...)
          Statements:
            ...
      Packages:
        - Name: fixed_pkg
          Package: 1297
          Generic Map: ...
      PackageBodies:
      Configurations:
      Contexts:

Teardown

XPASS test_AllVHDLSources[/home/runner/work/extended-tests/extended-tests/ghdl-cosim/vhpidirect/arrays/matrices/pkg.vhd] 0:00:00.257010

Started 2021-11-23 15:22:10
Ended 2021-11-23 15:22:11
Duration 0:00:00.257010
Markers
xfail
Fixtures file

Setup

Call

Captured stdout call
================================================================================
                         pyGHDL.dom - Test Application                          
================================================================================
Parsing file '/home/runner/work/extended-tests/extended-tests/ghdl-cosim/vhpidirect/arrays/matrices/pkg.vhd'
[NOT IMPLEMENTED] function declaration without body
[NOT IMPLEMENTED] Array_Subtype_Definition
[NOT IMPLEMENTED] function declaration without body
libghdl processing time:  98.101 us
DOM translation time:    581.804 us

Design:
  Libraries:
    - Name: pretty
      Entities:
      Packages:
        - pkg
      Configurations:
      Contexts:
  Documents:
    - Path: '/home/runner/work/extended-tests/extended-tests/ghdl-cosim/vhpidirect/arrays/matrices/pkg.vhd':
      Entities:
      Architectures:
      Packages:
        - Name: pkg
          File: pkg.vhd
          Position: 1:8
          Declared:
          - attribute foreign of ???? : ???? is ????
          - type ???? is array(........) of .....
          - type matrix_acc_t is access .....
          - attribute foreign of ???? : ???? is ????
          - shared variable matrix : matrix_acc_t
      PackageBodies:
        - Name: pkg
          Declared:
          - function getMatSize return integer
          - function getMatPointer return matrix_acc_t
      Configurations:
      Contexts:

Teardown

XFAIL test_AllVHDLSources[/home/runner/work/extended-tests/extended-tests/ghdl-cosim/vhpidirect/arrays/matrices/vunit_axis_vcs/tb.vhd] 0:00:00.269104

Started 2021-11-23 15:22:11
Ended 2021-11-23 15:22:11
Duration 0:00:00.269104
Markers
xfail
Fixtures file

Setup

Call 

[gw0] linux -- Python 3.9.8 /opt/hostedtoolcache/Python/3.9.8/x64/bin/python

file = '/home/runner/work/extended-tests/extended-tests/ghdl-cosim/vhpidirect/arrays/matrices/vunit_axis_vcs/tb.vhd'

    @mark.parametrize(
    	"file",
    	getVHDLSources()
    )
    @mark.xfail
    def test_AllVHDLSources(file):
>   	check_call(['ghdl-dom', 'pretty', '-f', str(file)], stderr=STDOUT)

TestDOM.py:25: 
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ 

popenargs = (['ghdl-dom', 'pretty', '-f', '/home/runner/work/extended-tests/extended-tests/ghdl-cosim/vhpidirect/arrays/matrices/vunit_axis_vcs/tb.vhd'],)
kwargs = {'stderr': -2}, retcode = 6
cmd = ['ghdl-dom', 'pretty', '-f', '/home/runner/work/extended-tests/extended-tests/ghdl-cosim/vhpidirect/arrays/matrices/vunit_axis_vcs/tb.vhd']

    def check_call(*popenargs, **kwargs):
        """Run command with arguments.  Wait for command to complete.  If
        the exit code was zero then return, otherwise raise
        CalledProcessError.  The CalledProcessError object will have the
        return code in the returncode attribute.
    
        The arguments are the same as for the call function.  Example:
    
        check_call(["ls", "-l"])
        """
        retcode = call(*popenargs, **kwargs)
        if retcode:
            cmd = kwargs.get("args")
            if cmd is None:
                cmd = popenargs[0]
>           raise CalledProcessError(retcode, cmd)
E           subprocess.CalledProcessError: Command '['ghdl-dom', 'pretty', '-f', '/home/runner/work/extended-tests/extended-tests/ghdl-cosim/vhpidirect/arrays/matrices/vunit_axis_vcs/tb.vhd']' returned non-zero exit status 6.

/opt/hostedtoolcache/Python/3.9.8/x64/lib/python3.9/subprocess.py:373: CalledProcessError
Captured stdout call
================================================================================
                         pyGHDL.dom - Test Application                          
================================================================================
Parsing file '/home/runner/work/extended-tests/extended-tests/ghdl-cosim/vhpidirect/arrays/matrices/vunit_axis_vcs/tb.vhd'
DOM: Unknown statement of kind 'While_Loop_Statement' in process 'main' at /home/runner/work/extended-tests/extended-tests/ghdl-cosim/vhpidirect/arrays/matrices/vunit_axis_vcs/tb.vhd:54:4.

Teardown

XPASS test_AllVHDLSources[/home/runner/work/extended-tests/extended-tests/ghdl-cosim/vhpidirect/arrays/matrices/vunit_axis_vcs/vc_axis.vhd] 0:00:00.269529

Started 2021-11-23 15:22:11
Ended 2021-11-23 15:22:11
Duration 0:00:00.269529
Markers
xfail
Fixtures file

Setup

Call

Captured stdout call
================================================================================
                         pyGHDL.dom - Test Application                          
================================================================================
Parsing file '/home/runner/work/extended-tests/extended-tests/ghdl-cosim/vhpidirect/arrays/matrices/vunit_axis_vcs/vc_axis.vhd'
libghdl processing time:  171.101 us
DOM translation time:    1738.911 us

Design:
  Libraries:
    - Name: pretty
      Entities:
        - vc_axis(arch)
      Packages:
      Configurations:
      Contexts:
  Documents:
    - Path: '/home/runner/work/extended-tests/extended-tests/ghdl-cosim/vhpidirect/arrays/matrices/vunit_axis_vcs/vc_axis.vhd':
      Entities:
        - Name: vc_axis
          File: vc_axis.vhd
          Position: 8:7
          Generics:
            - m_axis : in axi_stream_master_t
            - s_axis : in axi_stream_slave_t
            - data_width : in natural := 32
            - fifo_depth : in natural := 4
          Ports:
            - clk, rstn : in std_logic
          Declared:
          Statements:
          Architecures:
          - arch
      Architectures:
        - Name: arch
          File: vc_axis.vhd
          Position: 20:13
          Entity: vc_axis
          Declared:
            - signal m_valid, m_ready, m_last, s_valid, s_ready, s_last : std_logic
            - signal m_data, s_data : std_logic_vector(data_length(m_axis) - 1 downto 0)
          Hierarchy:
            - vunit_axism: entity vunit_lib.axi_stream_master
            - vunit_axiss: entity vunit_lib.axi_stream_slave
            - uut: entity work.axis_buffer
          Statements:
            ...
            ...
            ...
      Packages:
      PackageBodies:
      Configurations:
      Contexts:

Teardown

XPASS test_AllVHDLSources[/home/runner/work/extended-tests/extended-tests/ghdl-cosim/vhpidirect/arrays/matrices/vunit_axis_vcs/src/fifo.vhd] 0:00:00.270760

Started 2021-11-23 15:22:11
Ended 2021-11-23 15:22:11
Duration 0:00:00.270760
Markers
xfail
Fixtures file

Setup

Call

Captured stdout call
================================================================================
                         pyGHDL.dom - Test Application                          
================================================================================
Parsing file '/home/runner/work/extended-tests/extended-tests/ghdl-cosim/vhpidirect/arrays/matrices/vunit_axis_vcs/src/fifo.vhd'
[NOT IMPLEMENTED] Array_Subtype_Definition
libghdl processing time:  289.002 us
DOM translation time:    3941.924 us

Design:
  Libraries:
    - Name: pretty
      Entities:
        - fifo(arch)
      Packages:
      Configurations:
      Contexts:
  Documents:
    - Path: '/home/runner/work/extended-tests/extended-tests/ghdl-cosim/vhpidirect/arrays/matrices/vunit_axis_vcs/src/fifo.vhd':
      Entities:
        - Name: fifo
          File: fifo.vhd
          Position: 4:7
          Generics:
            - data_width : in positive := 8
            - fifo_depth : in positive := 8
          Ports:
            - clkw : in std_logic
            - clkr : in std_logic
            - rst : in std_logic
            - wr : in std_logic
            - rd : in std_logic
            - d : in std_logic_vector(data_width - 1 downto 0)
            - e : out std_logic
            - f : out std_logic
            - q : out std_logic_vector(data_width - 1 downto 0)
          Declared:
          Statements:
          Architecures:
          - arch
      Architectures:
        - Name: arch
          File: fifo.vhd
          Position: 22:13
          Entity: fifo
          Declared:
            - type ???? is array(........) of .....
            - signal mem : fifo_t
            - signal rdp, wrp : unsigned(fifo_depth downto 0)
          Hierarchy:
            - pslchecks: block
            - None: process(...)
            - None: process(...)
            - None: process(...)
            - None: process(...)
          Statements:
            ...
            ...
            ...
            ...
            ...
            ...
            ...
      Packages:
      PackageBodies:
      Configurations:
      Contexts:

Teardown

XPASS test_AllVHDLSources[/home/runner/work/extended-tests/extended-tests/ghdl-cosim/vhpidirect/arrays/matrices/vunit_axis_vcs/src/axis_buffer.vhd] 0:00:00.265785

Started 2021-11-23 15:22:11
Ended 2021-11-23 15:22:11
Duration 0:00:00.265785
Markers
xfail
Fixtures file

Setup

Call

Captured stdout call
================================================================================
                         pyGHDL.dom - Test Application                          
================================================================================
Parsing file '/home/runner/work/extended-tests/extended-tests/ghdl-cosim/vhpidirect/arrays/matrices/vunit_axis_vcs/src/axis_buffer.vhd'
libghdl processing time:  241.401 us
DOM translation time:    3681.723 us

Design:
  Libraries:
    - Name: pretty
      Entities:
        - axis_buffer(arch)
      Packages:
      Configurations:
      Contexts:
  Documents:
    - Path: '/home/runner/work/extended-tests/extended-tests/ghdl-cosim/vhpidirect/arrays/matrices/vunit_axis_vcs/src/axis_buffer.vhd':
      Entities:
        - Name: axis_buffer
          File: axis_buffer.vhd
          Position: 4:7
          Generics:
            - data_width : in integer := 32
            - fifo_depth : in integer := 0
          Ports:
            - s_axis_clk : in std_logic
            - s_axis_rstn : in std_logic
            - s_axis_rdy : out std_logic
            - s_axis_data : in std_logic_vector(data_width - 1 downto 0)
            - s_axis_valid : in std_logic
            - s_axis_strb : in std_logic_vector((data_width / 8) - 1 downto 0)
            - s_axis_last : in std_logic
            - m_axis_clk : in std_logic
            - m_axis_rstn : in std_logic
            - m_axis_valid : out std_logic
            - m_axis_data : out std_logic_vector(data_width - 1 downto 0)
            - m_axis_rdy : in std_logic
            - m_axis_strb : out std_logic_vector((data_width / 8) - 1 downto 0)
            - m_axis_last : out std_logic
          Declared:
          Statements:
          Architecures:
          - arch
      Architectures:
        - Name: arch
          File: axis_buffer.vhd
          Position: 28:13
          Entity: axis_buffer
          Declared:
            - signal r, e, f, wr, rd, valid : std_logic
            - signal d, q : std_logic_vector(data_width + data_width / 8 downto 0)
          Hierarchy:
            - fifo: entity work.fifo
            - None: process(...)
          Statements:
            ...
            ...
            ...
            ...
            ...
            ...
            ...
            ...
            ...
            ...
            ...
      Packages:
      PackageBodies:
      Configurations:
      Contexts:

Teardown

XPASS test_AllVHDLSources[/home/runner/work/extended-tests/extended-tests/ghdl-cosim/vhpidirect/arrays/matrices/framebuffer/tb.vhd] 0:00:00.257428

Started 2021-11-23 15:22:11
Ended 2021-11-23 15:22:11
Duration 0:00:00.257428
Markers
xfail
Fixtures file

Setup

Call

Captured stdout call
================================================================================
                         pyGHDL.dom - Test Application                          
================================================================================
Parsing file '/home/runner/work/extended-tests/extended-tests/ghdl-cosim/vhpidirect/arrays/matrices/framebuffer/tb.vhd'
libghdl processing time:  231.202 us
DOM translation time:    2092.012 us

Design:
  Libraries:
    - Name: pretty
      Entities:
        - tb(test, bars)
      Packages:
      Configurations:
      Contexts:
  Documents:
    - Path: '/home/runner/work/extended-tests/extended-tests/ghdl-cosim/vhpidirect/arrays/matrices/framebuffer/tb.vhd':
      Entities:
        - Name: tb
          File: tb.vhd
          Position: 1:7
          Generics:
            - WIDTH : in natural := 640
            - HEIGHT : in natural := 480
          Ports:
          Declared:
          - package tb_pkg is new 1304 generic map (.....)
          - use tb_pkg.all
          Statements:
          Architecures:
          - test
          - bars
      Architectures:
        - Name: test
          File: tb.vhd
          Position: 14:13
          Entity: tb
          Declared:
            - constant c_width : integer := screen'length(2)
            - constant c_height : integer := screen'length(1)
          Hierarchy:
            - None: process(...)
          Statements:
            ...
        - Name: bars
          File: tb.vhd
          Position: 59:13
          Entity: tb
          Declared:
            - constant c_width : integer := screen'length(2)
            - constant c_height : integer := screen'length(1)
          Hierarchy:
            - None: process(...)
          Statements:
            ...
      Packages:
      PackageBodies:
      Configurations:
      Contexts:

Teardown

XPASS test_AllVHDLSources[/home/runner/work/extended-tests/extended-tests/ghdl-cosim/vhpidirect/arrays/matrices/framebuffer/pkg.vhd] 0:00:00.258064

Started 2021-11-23 15:22:11
Ended 2021-11-23 15:22:11
Duration 0:00:00.258064
Markers
xfail
Fixtures file

Setup

Call

Captured stdout call
================================================================================
                         pyGHDL.dom - Test Application                          
================================================================================
Parsing file '/home/runner/work/extended-tests/extended-tests/ghdl-cosim/vhpidirect/arrays/matrices/framebuffer/pkg.vhd'
[NOT IMPLEMENTED] Array_Subtype_Definition
[NOT IMPLEMENTED] procedure declaration without body
[NOT IMPLEMENTED] procedure declaration without body
[NOT IMPLEMENTED] procedure declaration without body
[NOT IMPLEMENTED] function declaration without body
libghdl processing time:  184.901 us
DOM translation time:    1117.307 us

Design:
  Libraries:
    - Name: pretty
      Entities:
      Packages:
        - pkg
      Configurations:
      Contexts:
  Documents:
    - Path: '/home/runner/work/extended-tests/extended-tests/ghdl-cosim/vhpidirect/arrays/matrices/framebuffer/pkg.vhd':
      Entities:
      Architectures:
      Packages:
        - Name: pkg
          File: pkg.vhd
          Position: 4:8
          Declared:
          - type ???? is array(........) of .....
          - shared variable screen : screen_t
          - attribute foreign of ???? : ???? is ????
          - attribute foreign of ???? : ???? is ????
          - attribute foreign of ???? : ???? is ????
      PackageBodies:
        - Name: pkg
          Declared:
          - procedure sim_init
          - procedure save_screenshot
          - procedure sim_cleanup
          - function RGB_to_integer return integer
      Configurations:
      Contexts:

Teardown

XPASS test_AllVHDLSources[/home/runner/work/extended-tests/extended-tests/ghdl-cosim/vhpidirect/quickstart/wrapping/basic/tb.vhd] 0:00:00.250523

Started 2021-11-23 15:22:11
Ended 2021-11-23 15:22:12
Duration 0:00:00.250523
Markers
xfail
Fixtures file

Setup

Call

Captured stdout call
================================================================================
                         pyGHDL.dom - Test Application                          
================================================================================
Parsing file '/home/runner/work/extended-tests/extended-tests/ghdl-cosim/vhpidirect/quickstart/wrapping/basic/tb.vhd'
libghdl processing time:  69.801 us
DOM translation time:    323.602 us

Design:
  Libraries:
    - Name: pretty
      Entities:
        - tb(arch)
      Packages:
      Configurations:
      Contexts:
  Documents:
    - Path: '/home/runner/work/extended-tests/extended-tests/ghdl-cosim/vhpidirect/quickstart/wrapping/basic/tb.vhd':
      Entities:
        - Name: tb
          File: tb.vhd
          Position: 1:7
          Generics:
          Ports:
          Declared:
          Statements:
          Architecures:
          - arch
      Architectures:
        - Name: arch
          File: tb.vhd
          Position: 4:13
          Entity: tb
          Declared:
          Hierarchy:
            - None: process(...)
          Statements:
            ...
      Packages:
      PackageBodies:
      Configurations:
      Contexts:

Teardown

XPASS test_AllVHDLSources[/home/runner/work/extended-tests/extended-tests/ghdl-cosim/vhpidirect/quickstart/wrapping/time/tb.vhd] 0:00:00.250896

Started 2021-11-23 15:22:11
Ended 2021-11-23 15:22:12
Duration 0:00:00.250896
Markers
xfail
Fixtures file

Setup

Call

Captured stdout call
================================================================================
                         pyGHDL.dom - Test Application                          
================================================================================
Parsing file '/home/runner/work/extended-tests/extended-tests/ghdl-cosim/vhpidirect/quickstart/wrapping/time/tb.vhd'
libghdl processing time:  105.901 us
DOM translation time:    1586.709 us

Design:
  Libraries:
    - Name: pretty
      Entities:
        - tb(arch)
      Packages:
      Configurations:
      Contexts:
  Documents:
    - Path: '/home/runner/work/extended-tests/extended-tests/ghdl-cosim/vhpidirect/quickstart/wrapping/time/tb.vhd':
      Entities:
        - Name: tb
          File: tb.vhd
          Position: 1:7
          Generics:
          Ports:
          Declared:
          Statements:
          Architecures:
          - arch
      Architectures:
        - Name: arch
          File: tb.vhd
          Position: 4:13
          Entity: tb
          Declared:
            - signal sum : integer
            - signal n_sum : integer
            - signal clk : bit
            - signal rst : bit
          Hierarchy:
            - None: process(...)
            - None: process(...)
          Statements:
            ...
            ...
            ...
      Packages:
      PackageBodies:
      Configurations:
      Contexts:

Teardown

XPASS test_AllVHDLSources[/home/runner/work/extended-tests/extended-tests/ghdl-cosim/vhpidirect/quickstart/wrapping/exitcb/tb.vhd] 0:00:00.254821

Started 2021-11-23 15:22:12
Ended 2021-11-23 15:22:12
Duration 0:00:00.254821
Markers
xfail
Fixtures file

Setup

Call

Captured stdout call
================================================================================
                         pyGHDL.dom - Test Application                          
================================================================================
Parsing file '/home/runner/work/extended-tests/extended-tests/ghdl-cosim/vhpidirect/quickstart/wrapping/exitcb/tb.vhd'
libghdl processing time:  43.400 us
DOM translation time:    472.603 us

Design:
  Libraries:
    - Name: pretty
      Entities:
        - tb(pass, fail)
      Packages:
      Configurations:
      Contexts:
  Documents:
    - Path: '/home/runner/work/extended-tests/extended-tests/ghdl-cosim/vhpidirect/quickstart/wrapping/exitcb/tb.vhd':
      Entities:
        - Name: tb
          File: tb.vhd
          Position: 1:7
          Generics:
          Ports:
          Declared:
          Statements:
          Architecures:
          - pass
          - fail
      Architectures:
        - Name: pass
          File: tb.vhd
          Position: 4:13
          Entity: tb
          Declared:
          Hierarchy:
            - None: process(...)
          Statements:
            ...
        - Name: fail
          File: tb.vhd
          Position: 12:13
          Entity: tb
          Declared:
          Hierarchy:
            - None: process(...)
          Statements:
            ...
      Packages:
      PackageBodies:
      Configurations:
      Contexts:

Teardown

XPASS test_AllVHDLSources[/home/runner/work/extended-tests/extended-tests/ghdl-cosim/vhpidirect/quickstart/sharedvar/tb.vhd] 0:00:00.255674

Started 2021-11-23 15:22:12
Ended 2021-11-23 15:22:12
Duration 0:00:00.255674
Markers
xfail
Fixtures file

Setup

Call

Captured stdout call
================================================================================
                         pyGHDL.dom - Test Application                          
================================================================================
Parsing file '/home/runner/work/extended-tests/extended-tests/ghdl-cosim/vhpidirect/quickstart/sharedvar/tb.vhd'
libghdl processing time:  65.000 us
DOM translation time:    447.803 us

Design:
  Libraries:
    - Name: pretty
      Entities:
        - tb(arch)
      Packages:
      Configurations:
      Contexts:
  Documents:
    - Path: '/home/runner/work/extended-tests/extended-tests/ghdl-cosim/vhpidirect/quickstart/sharedvar/tb.vhd':
      Entities:
        - Name: tb
          File: tb.vhd
          Position: 1:7
          Generics:
          Ports:
          Declared:
          Statements:
          Architecures:
          - arch
      Architectures:
        - Name: arch
          File: tb.vhd
          Position: 4:13
          Entity: tb
          Declared:
          Hierarchy:
            - enta: entity work.ent
            - entb: entity work.ent
            - None: process(...)
          Statements:
            ...
            ...
            ...
      Packages:
      PackageBodies:
      Configurations:
      Contexts:

Teardown

XPASS test_AllVHDLSources[/home/runner/work/extended-tests/extended-tests/ghdl-cosim/vhpidirect/quickstart/sharedvar/ent.vhd] 0:00:00.247502

Started 2021-11-23 15:22:12
Ended 2021-11-23 15:22:12
Duration 0:00:00.247502
Markers
xfail
Fixtures file

Setup

Call

Captured stdout call
================================================================================
                         pyGHDL.dom - Test Application                          
================================================================================
Parsing file '/home/runner/work/extended-tests/extended-tests/ghdl-cosim/vhpidirect/quickstart/sharedvar/ent.vhd'
libghdl processing time:  71.100 us
DOM translation time:    953.505 us

Design:
  Libraries:
    - Name: pretty
      Entities:
        - ent(rtl_A, rtl_B)
      Packages:
      Configurations:
      Contexts:
  Documents:
    - Path: '/home/runner/work/extended-tests/extended-tests/ghdl-cosim/vhpidirect/quickstart/sharedvar/ent.vhd':
      Entities:
        - Name: ent
          File: ent.vhd
          Position: 3:7
          Generics:
          Ports:
          Declared:
          Statements:
          Architecures:
          - rtl_A
          - rtl_B
      Architectures:
        - Name: rtl_A
          File: ent.vhd
          Position: 6:13
          Entity: ent
          Declared:
          Hierarchy:
            - None: process(...)
          Statements:
            ...
        - Name: rtl_B
          File: ent.vhd
          Position: 18:13
          Entity: ent
          Declared:
          Hierarchy:
            - None: process(...)
          Statements:
            ...
      Packages:
      PackageBodies:
      Configurations:
      Contexts:

Teardown

XPASS test_AllVHDLSources[/home/runner/work/extended-tests/extended-tests/ghdl-cosim/vhpidirect/quickstart/sharedvar/pkg_93.vhd] 0:00:00.246564

Started 2021-11-23 15:22:12
Ended 2021-11-23 15:22:12
Duration 0:00:00.246564
Markers
xfail
Fixtures file

Setup

Call

Captured stdout call
================================================================================
                         pyGHDL.dom - Test Application                          
================================================================================
Parsing file '/home/runner/work/extended-tests/extended-tests/ghdl-cosim/vhpidirect/quickstart/sharedvar/pkg_93.vhd'
[NOT IMPLEMENTED] function declaration without body
[NOT IMPLEMENTED] procedure declaration without body
[NOT IMPLEMENTED] procedure declaration without body
[NOT IMPLEMENTED] function declaration without body
libghdl processing time:  102.700 us
DOM translation time:    653.003 us

Design:
  Libraries:
    - Name: pretty
      Entities:
      Packages:
        - pkg
      Configurations:
      Contexts:
  Documents:
    - Path: '/home/runner/work/extended-tests/extended-tests/ghdl-cosim/vhpidirect/quickstart/sharedvar/pkg_93.vhd':
      Entities:
      Architectures:
      Packages:
        - Name: pkg
          File: pkg_93.vhd
          Position: 1:8
          Declared:
          - type int_ptr is access .....
          - attribute foreign of ???? : ???? is ????
          - attribute foreign of ???? : ???? is ????
          - shared variable c_Var : int_ptr
      PackageBodies:
        - Name: pkg
          Declared:
          - function c_Int_ptr return int_ptr
          - procedure c_printVar
          - procedure setVar
          - function getVar return integer
      Configurations:
      Contexts:

Teardown

XPASS test_AllVHDLSources[/home/runner/work/extended-tests/extended-tests/ghdl-cosim/vhpidirect/quickstart/sharedvar/pkg_08.vhd] 0:00:00.263307

Started 2021-11-23 15:22:12
Ended 2021-11-23 15:22:12
Duration 0:00:00.263307
Markers
xfail
Fixtures file

Setup

Call

Captured stdout call
================================================================================
                         pyGHDL.dom - Test Application                          
================================================================================
Parsing file '/home/runner/work/extended-tests/extended-tests/ghdl-cosim/vhpidirect/quickstart/sharedvar/pkg_08.vhd'
[NOT IMPLEMENTED] function declaration without body
[NOT IMPLEMENTED] procedure declaration without body
[NOT IMPLEMENTED] procedure declaration without body
[NOT IMPLEMENTED] function declaration without body
libghdl processing time:  132.201 us
DOM translation time:    901.905 us

Design:
  Libraries:
    - Name: pretty
      Entities:
      Packages:
        - pkg
      Configurations:
      Contexts:
  Documents:
    - Path: '/home/runner/work/extended-tests/extended-tests/ghdl-cosim/vhpidirect/quickstart/sharedvar/pkg_08.vhd':
      Entities:
      Architectures:
      Packages:
        - Name: pkg
          File: pkg_08.vhd
          Position: 1:8
          Declared:
          - type int_ptr is access .....
          - attribute foreign of ???? : ???? is ????
          - attribute foreign of ???? : ???? is ????
          - type int_ptr_prot is protected ..... end protected
          - shared variable c_Var : int_ptr_prot
      PackageBodies:
        - Name: pkg
          Declared:
          - function c_Int_ptr return int_ptr
          - procedure c_printVar
          - procedure setVar
          - function getVar return integer
          - type int_ptr_prot is protected body ..... end protected body
      Configurations:
      Contexts:

Teardown

XPASS test_AllVHDLSources[/home/runner/work/extended-tests/extended-tests/ghdl-cosim/vhpidirect/quickstart/sharedvar/shint/ent.vhd] 0:00:00.256284

Started 2021-11-23 15:22:12
Ended 2021-11-23 15:22:12
Duration 0:00:00.256284
Markers
xfail
Fixtures file

Setup

Call

Captured stdout call
================================================================================
                         pyGHDL.dom - Test Application                          
================================================================================
Parsing file '/home/runner/work/extended-tests/extended-tests/ghdl-cosim/vhpidirect/quickstart/sharedvar/shint/ent.vhd'
libghdl processing time:  88.301 us
DOM translation time:    1266.706 us

Design:
  Libraries:
    - Name: pretty
      Entities:
        - ent(rtl_A, rtl_B)
      Packages:
      Configurations:
      Contexts:
  Documents:
    - Path: '/home/runner/work/extended-tests/extended-tests/ghdl-cosim/vhpidirect/quickstart/sharedvar/shint/ent.vhd':
      Entities:
        - Name: ent
          File: ent.vhd
          Position: 3:7
          Generics:
          Ports:
          Declared:
          Statements:
          Architecures:
          - rtl_A
          - rtl_B
      Architectures:
        - Name: rtl_A
          File: ent.vhd
          Position: 6:13
          Entity: ent
          Declared:
          Hierarchy:
            - None: process(...)
          Statements:
            ...
        - Name: rtl_B
          File: ent.vhd
          Position: 19:13
          Entity: ent
          Declared:
          Hierarchy:
            - None: process(...)
          Statements:
            ...
      Packages:
      PackageBodies:
      Configurations:
      Contexts:

Teardown

XPASS test_AllVHDLSources[/home/runner/work/extended-tests/extended-tests/ghdl-cosim/vhpidirect/quickstart/sharedvar/shint/pkg.vhd] 0:00:00.258262

Started 2021-11-23 15:22:12
Ended 2021-11-23 15:22:13
Duration 0:00:00.258262
Markers
xfail
Fixtures file

Setup

Call

Captured stdout call
================================================================================
                         pyGHDL.dom - Test Application                          
================================================================================
Parsing file '/home/runner/work/extended-tests/extended-tests/ghdl-cosim/vhpidirect/quickstart/sharedvar/shint/pkg.vhd'
[NOT IMPLEMENTED] procedure declaration without body
[NOT IMPLEMENTED] function declaration without body
[NOT IMPLEMENTED] procedure declaration without body
[NOT IMPLEMENTED] function declaration without body
[NOT IMPLEMENTED] procedure declaration without body
[NOT IMPLEMENTED] function declaration without body
[NOT IMPLEMENTED] procedure declaration without body
libghdl processing time:  198.801 us
DOM translation time:    1128.506 us

Design:
  Libraries:
    - Name: pretty
      Entities:
      Packages:
        - pkg
      Configurations:
      Contexts:
  Documents:
    - Path: '/home/runner/work/extended-tests/extended-tests/ghdl-cosim/vhpidirect/quickstart/sharedvar/shint/pkg.vhd':
      Entities:
      Architectures:
      Packages:
        - Name: pkg
          File: pkg.vhd
          Position: 1:8
          Declared:
          - attribute foreign of ???? : ???? is ????
          - attribute foreign of ???? : ???? is ????
          - attribute foreign of ???? : ???? is ????
          - type shint_t is record ..... end record
      PackageBodies:
        - Name: pkg
          Declared:
          - procedure write_int
          - function read_int return integer
          - procedure print_int
          - function new_shint return shint_t
          - procedure write
          - function read return integer
          - procedure print
      Configurations:
      Contexts:

Teardown

XFAIL test_AllVHDLSources[/home/runner/work/extended-tests/extended-tests/ghdl-cosim/vhpidirect/quickstart/sharedvar/shrecord/ent.vhd] 0:00:00.252001

Started 2021-11-23 15:22:12
Ended 2021-11-23 15:22:13
Duration 0:00:00.252001
Markers
xfail
Fixtures file

Setup

Call 

[gw1] linux -- Python 3.9.8 /opt/hostedtoolcache/Python/3.9.8/x64/bin/python

file = '/home/runner/work/extended-tests/extended-tests/ghdl-cosim/vhpidirect/quickstart/sharedvar/shrecord/ent.vhd'

    @mark.parametrize(
    	"file",
    	getVHDLSources()
    )
    @mark.xfail
    def test_AllVHDLSources(file):
>   	check_call(['ghdl-dom', 'pretty', '-f', str(file)], stderr=STDOUT)

TestDOM.py:25: 
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ 

popenargs = (['ghdl-dom', 'pretty', '-f', '/home/runner/work/extended-tests/extended-tests/ghdl-cosim/vhpidirect/quickstart/sharedvar/shrecord/ent.vhd'],)
kwargs = {'stderr': -2}, retcode = 6
cmd = ['ghdl-dom', 'pretty', '-f', '/home/runner/work/extended-tests/extended-tests/ghdl-cosim/vhpidirect/quickstart/sharedvar/shrecord/ent.vhd']

    def check_call(*popenargs, **kwargs):
        """Run command with arguments.  Wait for command to complete.  If
        the exit code was zero then return, otherwise raise
        CalledProcessError.  The CalledProcessError object will have the
        return code in the returncode attribute.
    
        The arguments are the same as for the call function.  Example:
    
        check_call(["ls", "-l"])
        """
        retcode = call(*popenargs, **kwargs)
        if retcode:
            cmd = kwargs.get("args")
            if cmd is None:
                cmd = popenargs[0]
>           raise CalledProcessError(retcode, cmd)
E           subprocess.CalledProcessError: Command '['ghdl-dom', 'pretty', '-f', '/home/runner/work/extended-tests/extended-tests/ghdl-cosim/vhpidirect/quickstart/sharedvar/shrecord/ent.vhd']' returned non-zero exit status 6.

/opt/hostedtoolcache/Python/3.9.8/x64/lib/python3.9/subprocess.py:373: CalledProcessError
Captured stdout call
================================================================================
                         pyGHDL.dom - Test Application                          
================================================================================
Parsing file '/home/runner/work/extended-tests/extended-tests/ghdl-cosim/vhpidirect/quickstart/sharedvar/shrecord/ent.vhd'
DOM: Unknown expression kind 'Selected_By_All_Name' in expression '1347' at /home/runner/work/extended-tests/extended-tests/ghdl-cosim/vhpidirect/quickstart/sharedvar/shrecord/ent.vhd:20:28.

Teardown

XPASS test_AllVHDLSources[/home/runner/work/extended-tests/extended-tests/ghdl-cosim/vhpidirect/quickstart/sharedvar/shrecord/pkg.vhd] 0:00:00.268044

Started 2021-11-23 15:22:13
Ended 2021-11-23 15:22:13
Duration 0:00:00.268044
Markers
xfail
Fixtures file

Setup

Call

Captured stdout call
================================================================================
                         pyGHDL.dom - Test Application                          
================================================================================
Parsing file '/home/runner/work/extended-tests/extended-tests/ghdl-cosim/vhpidirect/quickstart/sharedvar/shrecord/pkg.vhd'
[NOT IMPLEMENTED] procedure declaration without body
[NOT IMPLEMENTED] procedure declaration without body
[NOT IMPLEMENTED] function declaration without body
libghdl processing time:  134.501 us
DOM translation time:    880.804 us

Design:
  Libraries:
    - Name: pretty
      Entities:
      Packages:
        - pkg
      Configurations:
      Contexts:
  Documents:
    - Path: '/home/runner/work/extended-tests/extended-tests/ghdl-cosim/vhpidirect/quickstart/sharedvar/shrecord/pkg.vhd':
      Entities:
      Architectures:
      Packages:
        - Name: pkg
          File: pkg.vhd
          Position: 4:8
          Declared:
          - type c_struct is record ..... end record
          - type c_struct_ptr is access .....
          - attribute foreign of ???? : ???? is ????
          - attribute foreign of ???? : ???? is ????
          - attribute foreign of ???? : ???? is ????
      PackageBodies:
        - Name: pkg
          Declared:
          - procedure c_printAndChangeStruct
          - procedure c_printStruct
          - function c_getStruct return c_struct_ptr
      Configurations:
      Contexts:

Teardown

XPASS test_AllVHDLSources[/home/runner/work/extended-tests/extended-tests/ghdl-cosim/vhpidirect/quickstart/customc/tb.vhd] 0:00:00.267722

Started 2021-11-23 15:22:13
Ended 2021-11-23 15:22:13
Duration 0:00:00.267722
Markers
xfail
Fixtures file

Setup

Call

Captured stdout call
================================================================================
                         pyGHDL.dom - Test Application                          
================================================================================
Parsing file '/home/runner/work/extended-tests/extended-tests/ghdl-cosim/vhpidirect/quickstart/customc/tb.vhd'
libghdl processing time:  125.301 us
DOM translation time:    1294.306 us

Design:
  Libraries:
    - Name: pretty
      Entities:
        - tb(arch)
      Packages:
      Configurations:
      Contexts:
  Documents:
    - Path: '/home/runner/work/extended-tests/extended-tests/ghdl-cosim/vhpidirect/quickstart/customc/tb.vhd':
      Entities:
        - Name: tb
          File: tb.vhd
          Position: 1:7
          Generics:
          Ports:
          Declared:
          Statements:
          Architecures:
          - arch
      Architectures:
        - Name: arch
          File: tb.vhd
          Position: 4:13
          Entity: tb
          Declared:
            - procedure cproc
            - attribute foreign of ???? : ???? is ????
            - procedure cproc_wargs
            - attribute foreign of ???? : ???? is ????
            - function cfunc return integer
            - attribute foreign of ???? : ???? is ????
            - function cfunc_wargs return integer
            - attribute foreign of ???? : ???? is ????
          Hierarchy:
            - None: process(...)
          Statements:
            ...
      Packages:
      PackageBodies:
      Configurations:
      Contexts:

Teardown

XPASS test_AllVHDLSources[/home/runner/work/extended-tests/extended-tests/ghdl-cosim/vhpidirect/quickstart/linking/bind/tb.vhd] 0:00:00.257731

Started 2021-11-23 15:22:13
Ended 2021-11-23 15:22:13
Duration 0:00:00.257731
Markers
xfail
Fixtures file

Setup

Call

Captured stdout call
================================================================================
                         pyGHDL.dom - Test Application                          
================================================================================
Parsing file '/home/runner/work/extended-tests/extended-tests/ghdl-cosim/vhpidirect/quickstart/linking/bind/tb.vhd'
libghdl processing time:  46.800 us
DOM translation time:    294.002 us

Design:
  Libraries:
    - Name: pretty
      Entities:
        - tb(arch)
      Packages:
      Configurations:
      Contexts:
  Documents:
    - Path: '/home/runner/work/extended-tests/extended-tests/ghdl-cosim/vhpidirect/quickstart/linking/bind/tb.vhd':
      Entities:
        - Name: tb
          File: tb.vhd
          Position: 1:7
          Generics:
          Ports:
          Declared:
          Statements:
          Architecures:
          - arch
      Architectures:
        - Name: arch
          File: tb.vhd
          Position: 4:13
          Entity: tb
          Declared:
          Hierarchy:
            - None: process(...)
          Statements:
            ...
      Packages:
      PackageBodies:
      Configurations:
      Contexts:

Teardown

XPASS test_AllVHDLSources[/home/runner/work/extended-tests/extended-tests/ghdl-cosim/vhpidirect/quickstart/math/tb.vhd] 0:00:00.260857

Started 2021-11-23 15:22:13
Ended 2021-11-23 15:22:13
Duration 0:00:00.260857
Markers
xfail
Fixtures file

Setup

Call

Captured stdout call
================================================================================
                         pyGHDL.dom - Test Application                          
================================================================================
Parsing file '/home/runner/work/extended-tests/extended-tests/ghdl-cosim/vhpidirect/quickstart/math/tb.vhd'
[NOT IMPLEMENTED] Variable assignment (label: 'None') at line 15
libghdl processing time:  97.301 us
DOM translation time:    655.903 us

Design:
  Libraries:
    - Name: pretty
      Entities:
        - tb(arch)
      Packages:
      Configurations:
      Contexts:
  Documents:
    - Path: '/home/runner/work/extended-tests/extended-tests/ghdl-cosim/vhpidirect/quickstart/math/tb.vhd':
      Entities:
        - Name: tb
          File: tb.vhd
          Position: 1:7
          Generics:
          Ports:
          Declared:
          Statements:
          Architecures:
          - arch
      Architectures:
        - Name: arch
          File: tb.vhd
          Position: 4:13
          Entity: tb
          Declared:
            - function sin return real
            - attribute foreign of ???? : ???? is ????
          Hierarchy:
            - None: process(...)
          Statements:
            ...
      Packages:
      PackageBodies:
      Configurations:
      Contexts:

Teardown

XPASS test_AllVHDLSources[/home/runner/work/extended-tests/extended-tests/ghdl-cosim/vhpidirect/quickstart/package/tb.vhd] 0:00:00.245660

Started 2021-11-23 15:22:13
Ended 2021-11-23 15:22:14
Duration 0:00:00.245660
Markers
xfail
Fixtures file

Setup

Call

Captured stdout call
================================================================================
                         pyGHDL.dom - Test Application                          
================================================================================
Parsing file '/home/runner/work/extended-tests/extended-tests/ghdl-cosim/vhpidirect/quickstart/package/tb.vhd'
libghdl processing time:  46.300 us
DOM translation time:    403.902 us

Design:
  Libraries:
    - Name: pretty
      Entities:
        - tb(arch)
      Packages:
      Configurations:
      Contexts:
  Documents:
    - Path: '/home/runner/work/extended-tests/extended-tests/ghdl-cosim/vhpidirect/quickstart/package/tb.vhd':
      Entities:
        - Name: tb
          File: tb.vhd
          Position: 1:7
          Generics:
          Ports:
          Declared:
          Statements:
          Architecures:
          - arch
      Architectures:
        - Name: arch
          File: tb.vhd
          Position: 4:13
          Entity: tb
          Declared:
          Hierarchy:
            - enta: entity work.ent
            - entb: entity work.ent
            - None: process(...)
          Statements:
            ...
            ...
            ...
      Packages:
      PackageBodies:
      Configurations:
      Contexts:

Teardown

XPASS test_AllVHDLSources[/home/runner/work/extended-tests/extended-tests/ghdl-cosim/vhpidirect/quickstart/package/ent.vhd] 0:00:00.248569

Started 2021-11-23 15:22:13
Ended 2021-11-23 15:22:14
Duration 0:00:00.248569
Markers
xfail
Fixtures file

Setup

Call

Captured stdout call
================================================================================
                         pyGHDL.dom - Test Application                          
================================================================================
Parsing file '/home/runner/work/extended-tests/extended-tests/ghdl-cosim/vhpidirect/quickstart/package/ent.vhd'
libghdl processing time:  62.200 us
DOM translation time:    690.103 us

Design:
  Libraries:
    - Name: pretty
      Entities:
        - ent(rtl_A, rtl_B)
      Packages:
      Configurations:
      Contexts:
  Documents:
    - Path: '/home/runner/work/extended-tests/extended-tests/ghdl-cosim/vhpidirect/quickstart/package/ent.vhd':
      Entities:
        - Name: ent
          File: ent.vhd
          Position: 3:7
          Generics:
          Ports:
          Declared:
          Statements:
          Architecures:
          - rtl_A
          - rtl_B
      Architectures:
        - Name: rtl_A
          File: ent.vhd
          Position: 6:13
          Entity: ent
          Declared:
          Hierarchy:
            - None: process(...)
          Statements:
            ...
        - Name: rtl_B
          File: ent.vhd
          Position: 16:13
          Entity: ent
          Declared:
          Hierarchy:
            - None: process(...)
          Statements:
            ...
      Packages:
      PackageBodies:
      Configurations:
      Contexts:

Teardown

XPASS test_AllVHDLSources[/home/runner/work/extended-tests/extended-tests/ghdl-cosim/vhpidirect/quickstart/package/pkg.vhd] 0:00:00.248730

Started 2021-11-23 15:22:14
Ended 2021-11-23 15:22:14
Duration 0:00:00.248730
Markers
xfail
Fixtures file

Setup

Call

Captured stdout call
================================================================================
                         pyGHDL.dom - Test Application                          
================================================================================
Parsing file '/home/runner/work/extended-tests/extended-tests/ghdl-cosim/vhpidirect/quickstart/package/pkg.vhd'
[NOT IMPLEMENTED] procedure declaration without body
libghdl processing time:  62.400 us
DOM translation time:    278.202 us

Design:
  Libraries:
    - Name: pretty
      Entities:
      Packages:
        - pkg
      Configurations:
      Contexts:
  Documents:
    - Path: '/home/runner/work/extended-tests/extended-tests/ghdl-cosim/vhpidirect/quickstart/package/pkg.vhd':
      Entities:
      Architectures:
      Packages:
        - Name: pkg
          File: pkg.vhd
          Position: 1:8
          Declared:
          - attribute foreign of ???? : ???? is ????
      PackageBodies:
        - Name: pkg
          Declared:
          - procedure c_printInt
      Configurations:
      Contexts:

Teardown

XPASS test_AllVHDLSources[/home/runner/work/extended-tests/extended-tests/ghdl-cosim/vhpidirect/quickstart/cli/tb.vhd] 0:00:00.242719

Started 2021-11-23 15:22:14
Ended 2021-11-23 15:22:14
Duration 0:00:00.242719
Markers
xfail
Fixtures file

Setup

Call

Captured stdout call
================================================================================
                         pyGHDL.dom - Test Application                          
================================================================================
Parsing file '/home/runner/work/extended-tests/extended-tests/ghdl-cosim/vhpidirect/quickstart/cli/tb.vhd'
libghdl processing time:  32.900 us
DOM translation time:    257.401 us

Design:
  Libraries:
    - Name: pretty
      Entities:
        - tb()
      Packages:
      Configurations:
      Contexts:
  Documents:
    - Path: '/home/runner/work/extended-tests/extended-tests/ghdl-cosim/vhpidirect/quickstart/cli/tb.vhd':
      Entities:
        - Name: tb
          File: tb.vhd
          Position: 1:7
          Generics:
            - genInt : in integer := 42
            - genStr : in string := "default string"
          Ports:
          Declared:
          Statements:
          Architecures:
      Architectures:
      Packages:
      PackageBodies:
      Configurations:
      Contexts:

Teardown

XPASS test_AllVHDLSources[/home/runner/work/extended-tests/extended-tests/ghdl-cosim/vhpidirect/quickstart/cli/arch.vhd] 0:00:00.234669

Started 2021-11-23 15:22:14
Ended 2021-11-23 15:22:14
Duration 0:00:00.234669
Markers
xfail
Fixtures file

Setup

Call

Captured stdout call
================================================================================
                         pyGHDL.dom - Test Application                          
================================================================================
Parsing file '/home/runner/work/extended-tests/extended-tests/ghdl-cosim/vhpidirect/quickstart/cli/arch.vhd'
libghdl processing time:  45.400 us
DOM translation time:    507.202 us

Design:
  Libraries:
    - Name: pretty
      Entities:
      Packages:
      Configurations:
      Contexts:
  Documents:
    - Path: '/home/runner/work/extended-tests/extended-tests/ghdl-cosim/vhpidirect/quickstart/cli/arch.vhd':
      Entities:
      Architectures:
        - Name: arch
          File: arch.vhd
          Position: 1:13
          Entity: tb
          Declared:
          Hierarchy:
            - None: process(...)
          Statements:
            ...
      Packages:
      PackageBodies:
      Configurations:
      Contexts:

Teardown

XPASS test_AllVHDLSources[/home/runner/work/extended-tests/extended-tests/ghdl-cosim/vhpidirect/quickstart/cli/fcnargs/tb.vhd] 0:00:00.239884

Started 2021-11-23 15:22:14
Ended 2021-11-23 15:22:14
Duration 0:00:00.239884
Markers
xfail
Fixtures file

Setup

Call

Captured stdout call
================================================================================
                         pyGHDL.dom - Test Application                          
================================================================================
Parsing file '/home/runner/work/extended-tests/extended-tests/ghdl-cosim/vhpidirect/quickstart/cli/fcnargs/tb.vhd'
libghdl processing time:  43.700 us
DOM translation time:    257.702 us

Design:
  Libraries:
    - Name: pretty
      Entities:
        - tb()
      Packages:
      Configurations:
      Contexts:
  Documents:
    - Path: '/home/runner/work/extended-tests/extended-tests/ghdl-cosim/vhpidirect/quickstart/cli/fcnargs/tb.vhd':
      Entities:
        - Name: tb
          File: tb.vhd
          Position: 3:7
          Generics:
            - genInt : in integer := getGenInt
            - genStr : in string := "default string"
          Ports:
          Declared:
          Statements:
          Architecures:
      Architectures:
      Packages:
      PackageBodies:
      Configurations:
      Contexts:

Teardown

XPASS test_AllVHDLSources[/home/runner/work/extended-tests/extended-tests/ghdl-cosim/vhpidirect/quickstart/cli/fcnargs/pkg.vhd] 0:00:00.239922

Started 2021-11-23 15:22:14
Ended 2021-11-23 15:22:14
Duration 0:00:00.239922
Markers
xfail
Fixtures file

Setup

Call

Captured stdout call
================================================================================
                         pyGHDL.dom - Test Application                          
================================================================================
Parsing file '/home/runner/work/extended-tests/extended-tests/ghdl-cosim/vhpidirect/quickstart/cli/fcnargs/pkg.vhd'
[NOT IMPLEMENTED] function declaration without body
libghdl processing time:  53.101 us
DOM translation time:    297.901 us

Design:
  Libraries:
    - Name: pretty
      Entities:
      Packages:
        - pkg
      Configurations:
      Contexts:
  Documents:
    - Path: '/home/runner/work/extended-tests/extended-tests/ghdl-cosim/vhpidirect/quickstart/cli/fcnargs/pkg.vhd':
      Entities:
      Architectures:
      Packages:
        - Name: pkg
          File: pkg.vhd
          Position: 1:8
          Declared:
          - attribute foreign of ???? : ???? is ????
      PackageBodies:
        - Name: pkg
          Declared:
          - function getGenInt return integer
      Configurations:
      Contexts:

Teardown

XPASS test_AllVHDLSources[/home/runner/work/extended-tests/extended-tests/ghdl-cosim/vhpidirect/quickstart/cli/fcngen/arch.vhd] 0:00:00.245864

Started 2021-11-23 15:22:14
Ended 2021-11-23 15:22:14
Duration 0:00:00.245864
Markers
xfail
Fixtures file

Setup

Call

Captured stdout call
================================================================================
                         pyGHDL.dom - Test Application                          
================================================================================
Parsing file '/home/runner/work/extended-tests/extended-tests/ghdl-cosim/vhpidirect/quickstart/cli/fcngen/arch.vhd'
libghdl processing time:  128.801 us
DOM translation time:    700.104 us

Design:
  Libraries:
    - Name: pretty
      Entities:
      Packages:
      Configurations:
      Contexts:
  Documents:
    - Path: '/home/runner/work/extended-tests/extended-tests/ghdl-cosim/vhpidirect/quickstart/cli/fcngen/arch.vhd':
      Entities:
      Architectures:
        - Name: arch
          File: arch.vhd
          Position: 1:13
          Entity: tb
          Declared:
            - procedure setGenInt
            - attribute foreign of ???? : ???? is ????
          Hierarchy:
            - None: process(...)
          Statements:
            ...
      Packages:
      PackageBodies:
      Configurations:
      Contexts:

Teardown

XPASS test_AllVHDLSources[/home/runner/work/extended-tests/extended-tests/ghdl-cosim/vhpidirect/quickstart/random/tb.vhd] 0:00:00.239646

Started 2021-11-23 15:22:14
Ended 2021-11-23 15:22:14
Duration 0:00:00.239646
Markers
xfail
Fixtures file

Setup

Call

Captured stdout call
================================================================================
                         pyGHDL.dom - Test Application                          
================================================================================
Parsing file '/home/runner/work/extended-tests/extended-tests/ghdl-cosim/vhpidirect/quickstart/random/tb.vhd'
libghdl processing time:  75.000 us
DOM translation time:    523.603 us

Design:
  Libraries:
    - Name: pretty
      Entities:
        - tb(arch)
      Packages:
      Configurations:
      Contexts:
  Documents:
    - Path: '/home/runner/work/extended-tests/extended-tests/ghdl-cosim/vhpidirect/quickstart/random/tb.vhd':
      Entities:
        - Name: tb
          File: tb.vhd
          Position: 1:7
          Generics:
          Ports:
          Declared:
          Statements:
          Architecures:
          - arch
      Architectures:
        - Name: arch
          File: tb.vhd
          Position: 4:13
          Entity: tb
          Declared:
            - function rand return integer
            - attribute foreign of ???? : ???? is ????
          Hierarchy:
            - None: process(...)
          Statements:
            ...
      Packages:
      PackageBodies:
      Configurations:
      Contexts:

Teardown

XPASS test_AllVHDLSources[/home/runner/work/extended-tests/extended-tests/ghdl-cosim/vpi/tb.vhd] 0:00:00.245847

Started 2021-11-23 15:22:14
Ended 2021-11-23 15:22:15
Duration 0:00:00.245847
Markers
xfail
Fixtures file

Setup

Call

Captured stdout call
================================================================================
                         pyGHDL.dom - Test Application                          
================================================================================
Parsing file '/home/runner/work/extended-tests/extended-tests/ghdl-cosim/vpi/tb.vhd'
libghdl processing time:  145.200 us
DOM translation time:    1825.909 us

Design:
  Libraries:
    - Name: pretty
      Entities:
        - tb(arch)
      Packages:
      Configurations:
      Contexts:
  Documents:
    - Path: '/home/runner/work/extended-tests/extended-tests/ghdl-cosim/vpi/tb.vhd':
      Entities:
        - Name: tb
          File: tb.vhd
          Position: 5:7
          Generics:
            - G_WIDTH : in natural := 4
            - G_INST : in natural := 4
          Ports:
          Declared:
          Statements:
          Architecures:
          - arch
      Architectures:
        - Name: arch
          File: tb.vhd
          Position: 12:13
          Entity: tb
          Declared:
            - signal a, b : std_logic_vector(G_INST * G_WIDTH - 1 downto 0)
            - signal c : std_logic_vector(G_INST downto 0)
          Hierarchy:
            - i_ent: for x in 0 to G_INST - 1 generate
                - w_ent: entity work.ent
            - None: process(...)
          Statements:
            ...
            ...
      Packages:
      PackageBodies:
      Configurations:
      Contexts:

Teardown

XPASS test_AllVHDLSources[/home/runner/work/extended-tests/extended-tests/ghdl-cosim/vpi/ent.vhd] 0:00:00.239872

Started 2021-11-23 15:22:14
Ended 2021-11-23 15:22:15
Duration 0:00:00.239872
Markers
xfail
Fixtures file

Setup

Call

Captured stdout call
================================================================================
                         pyGHDL.dom - Test Application                          
================================================================================
Parsing file '/home/runner/work/extended-tests/extended-tests/ghdl-cosim/vpi/ent.vhd'
[NOT IMPLEMENTED] Concurrent (conditional) signal assignment (label: 'None') at line 23
libghdl processing time:  93.301 us
DOM translation time:    1013.705 us

Design:
  Libraries:
    - Name: pretty
      Entities:
        - ent(arch)
      Packages:
      Configurations:
      Contexts:
  Documents:
    - Path: '/home/runner/work/extended-tests/extended-tests/ghdl-cosim/vpi/ent.vhd':
      Entities:
        - Name: ent
          File: ent.vhd
          Position: 5:7
          Generics:
            - G_WIDTH : in natural := 4
          Ports:
            - A : in std_logic_vector(G_WIDTH - 1 downto 0)
            - B : in std_logic_vector(G_WIDTH - 1 downto 0)
            - C : in std_logic
            - Q : out std_logic_vector(G_WIDTH downto 0)
          Declared:
          Statements:
          Architecures:
          - arch
      Architectures:
        - Name: arch
          File: ent.vhd
          Position: 17:13
          Entity: ent
          Declared:
            - signal c_in : unsigned(0 downto 0)
          Hierarchy:
          Statements:
            ...
      Packages:
      PackageBodies:
      Configurations:
      Contexts:

Teardown

XPASS test_AllVHDLSources[/home/runner/work/extended-tests/extended-tests/NEORV32/setups/osflow/devices/ice40/sb_ice40_components.vhd] 0:00:00.256440

Started 2021-11-23 15:22:15
Ended 2021-11-23 15:22:15
Duration 0:00:00.256440
Markers
xfail
Fixtures file

Setup

Call

Captured stdout call
================================================================================
                         pyGHDL.dom - Test Application                          
================================================================================
Parsing file '/home/runner/work/extended-tests/extended-tests/NEORV32/setups/osflow/devices/ice40/sb_ice40_components.vhd'
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
libghdl processing time:  240.201 us
DOM translation time:    3905.820 us

Design:
  Libraries:
    - Name: pretty
      Entities:
      Packages:
        - components
      Configurations:
      Contexts:
  Documents:
    - Path: '/home/runner/work/extended-tests/extended-tests/NEORV32/setups/osflow/devices/ice40/sb_ice40_components.vhd':
      Entities:
      Architectures:
      Packages:
        - Name: components
          File: sb_ice40_components.vhd
          Position: 4:8
          Declared:
          - Component: SB_GB
            Generics:
            Ports:
              - GLOBAL_BUFFER_OUTPUT : out std_logic
              - USER_SIGNAL_TO_GLOBAL_BUFFER : in std_logic
          - Component: SB_HFOSC
            Generics:
              - CLKHF_DIV : in string
            Ports:
              - CLKHFPU : in std_logic
              - CLKHFEN : in std_logic
              - CLKHF : out std_logic
          - Component: SB_PLL40_CORE
            Generics:
              - FEEDBACK_PATH : in string := "SIMPLE"
              - DELAY_ADJUSTMENT_MODE_FEEDBACK : in string := "FIXED"
              - DELAY_ADJUSTMENT_MODE_RELATIVE : in string := "FIXED"
              - SHIFTREG_DIV_MODE : in std_logic := 0
              - FDA_FEEDBACK : in std_logic_vector(3 downto 0)
              - FDA_RELATIVE : in std_logic_vector(3 downto 0)
              - PLLOUT_SELECT : in string := "GENCLK"
              - DIVR : in std_logic_vector(3 downto 0)
              - DIVF : in std_logic_vector(6 downto 0) := "0000000"
              - DIVQ : in std_logic_vector(2 downto 0) := "000"
              - FILTER_RANGE : in std_logic_vector(2 downto 0) := "000"
              - ENABLE_ICEGATE : in bit := 0
              - TEST_MODE : in bit := 0
              - EXTERNAL_DIVIDE_FACTOR : in integer := 1
            Ports:
              - REFERENCECLK : in std_logic
              - PLLOUTCORE : out std_logic
              - PLLOUTGLOBAL : out std_logic
              - EXTFEEDBACK : in std_logic
              - DYNAMICDELAY : in std_logic_vector(7 downto 0)
              - LOCK : out std_logic
              - BYPASS : in std_logic
              - RESETB : in std_logic
              - LATCHINPUTVALUE : in std_logic
              - SDO : out std_logic
              - SDI : in std_logic
              - SCLK : in std_logic
          - Component: SB_PLL40_PAD
            Generics:
              - FEEDBACK_PATH : in string := "SIMPLE"
              - DELAY_ADJUSTMENT_MODE_FEEDBACK : in string := "FIXED"
              - DELAY_ADJUSTMENT_MODE_RELATIVE : in string := "FIXED"
              - SHIFTREG_DIV_MODE : in bit_vector(1 downto 0) := "00"
              - FDA_FEEDBACK : in bit_vector(3 downto 0) := "0000"
              - FDA_RELATIVE : in bit_vector(3 downto 0) := "0000"
              - PLLOUT_SELECT : in string := "GENCLK"
              - DIVR : in bit_vector(3 downto 0)
              - DIVF : in bit_vector(6 downto 0) := "0000000"
              - DIVQ : in bit_vector(2 downto 0) := "000"
              - FILTER_RANGE : in bit_vector(2 downto 0) := "000"
              - ENABLE_ICEGATE : in bit := 0
              - TEST_MODE : in bit := 0
              - EXTERNAL_DIVIDE_FACTOR : in integer := 1
            Ports:
              - PACKAGEPIN : in std_logic
              - PLLOUTCORE : out std_logic
              - PLLOUTGLOBAL : out std_logic
              - EXTFEEDBACK : in std_logic
              - DYNAMICDELAY : in std_logic_vector(7 downto 0)
              - LOCK : out std_logic
              - BYPASS : in std_logic
              - RESETB : in std_logic
              - LATCHINPUTVALUE : in std_logic
              - SDO : out std_logic
              - SDI : in std_logic
              - SCLK : in std_logic
          - Component: SB_RGBA_DRV
            Generics:
              - CURRENT_MODE : in string := "0b0"
              - RGB0_CURRENT : in string := "0b000000"
              - RGB1_CURRENT : in string := "0b000000"
              - RGB2_CURRENT : in string := "0b000000"
            Ports:
              - RGB0PWM : in std_logic
              - RGB1PWM : in std_logic
              - RGB2PWM : in std_logic
              - CURREN : in std_logic
              - RGBLEDEN : in std_logic
              - RGB0 : out std_logic
              - RGB1 : out std_logic
              - RGB2 : out std_logic
          - Component: SB_SPRAM256KA
            Generics:
            Ports:
              - ADDRESS : in std_logic_vector(13 downto 0)
              - DATAIN : in std_logic_vector(15 downto 0)
              - MASKWREN : in std_logic_vector(3 downto 0)
              - WREN : in std_logic
              - CHIPSELECT : in std_logic
              - CLOCK : in std_logic
              - STANDBY : in std_logic
              - SLEEP : in std_logic
              - POWEROFF : in std_logic
              - DATAOUT : out std_logic_vector(15 downto 0)
      PackageBodies:
      Configurations:
      Contexts:

Teardown

XPASS test_AllVHDLSources[/home/runner/work/extended-tests/extended-tests/NEORV32/setups/osflow/devices/ice40/neorv32_dmem.ice40up_spram.vhd] 0:00:00.254638

Started 2021-11-23 15:22:15
Ended 2021-11-23 15:22:15
Duration 0:00:00.254638
Markers
xfail
Fixtures file

Setup

Call

Captured stdout call
================================================================================
                         pyGHDL.dom - Test Application                          
================================================================================
Parsing file '/home/runner/work/extended-tests/extended-tests/NEORV32/setups/osflow/devices/ice40/neorv32_dmem.ice40up_spram.vhd'
[NOT IMPLEMENTED] Concurrent (conditional) signal assignment (label: 'None') at line 87
[NOT IMPLEMENTED] Concurrent (conditional) signal assignment (label: 'None') at line 126
[NOT IMPLEMENTED] Concurrent (conditional) signal assignment (label: 'None') at line 130
[NOT IMPLEMENTED] Concurrent (conditional) signal assignment (label: 'None') at line 142
libghdl processing time:  358.802 us
DOM translation time:    4307.421 us

Design:
  Libraries:
    - Name: pretty
      Entities:
      Packages:
      Configurations:
      Contexts:
  Documents:
    - Path: '/home/runner/work/extended-tests/extended-tests/NEORV32/setups/osflow/devices/ice40/neorv32_dmem.ice40up_spram.vhd':
      Entities:
      Architectures:
        - Name: neorv32_dmem_rtl
          File: neorv32_dmem.ice40up_spram.vhd
          Position: 48:13
          Entity: neorv32_dmem
          Declared:
            - constant spram_sleep_mode_en_c : boolean := false
            - constant hi_abb_c : natural := 31
            - constant lo_abb_c : natural := index_size_f(64 * 1024)
            - signal acc_en : std_ulogic
            - signal mem_cs : std_ulogic
            - signal rdata : std_ulogic_vector(31 downto 0)
            - signal rden : std_ulogic
            - signal spram_clk : std_logic
            - signal spram_addr : std_logic_vector(13 downto 0)
            - signal spram_di_lo : std_logic_vector(15 downto 0)
            - signal spram_di_hi : std_logic_vector(15 downto 0)
            - signal spram_do_lo : std_logic_vector(15 downto 0)
            - signal spram_do_hi : std_logic_vector(15 downto 0)
            - signal spram_be_lo : std_logic_vector(3 downto 0)
            - signal spram_be_hi : std_logic_vector(3 downto 0)
            - signal spram_we : std_logic
            - signal spram_pwr_n : std_logic
            - signal spram_cs : std_logic
          Hierarchy:
            - imem_spram_lo_inst: component SB_SPRAM256KA
            - imem_spram_hi_inst: component SB_SPRAM256KA
            - buffer_ff: process(...)
          Statements:
            ...
            ...
            ...
            ...
            ...
            ...
            ...
            ...
            ...
            ...
            ...
            ...
            ...
            ...
      Packages:
      PackageBodies:
      Configurations:
      Contexts:

Teardown

XPASS test_AllVHDLSources[/home/runner/work/extended-tests/extended-tests/NEORV32/setups/osflow/devices/ice40/neorv32_imem.ice40up_spram.vhd] 0:00:00.246831

Started 2021-11-23 15:22:15
Ended 2021-11-23 15:22:15
Duration 0:00:00.246831
Markers
xfail
Fixtures file

Setup

Call

Captured stdout call
================================================================================
                         pyGHDL.dom - Test Application                          
================================================================================
Parsing file '/home/runner/work/extended-tests/extended-tests/NEORV32/setups/osflow/devices/ice40/neorv32_imem.ice40up_spram.vhd'
[NOT IMPLEMENTED] Concurrent (conditional) signal assignment (label: 'None') at line 88
[NOT IMPLEMENTED] Concurrent (conditional) signal assignment (label: 'None') at line 127
[NOT IMPLEMENTED] Concurrent (conditional) signal assignment (label: 'None') at line 131
[NOT IMPLEMENTED] Concurrent (conditional) signal assignment (label: 'None') at line 143
libghdl processing time:  270.001 us
DOM translation time:    4234.621 us

Design:
  Libraries:
    - Name: pretty
      Entities:
      Packages:
      Configurations:
      Contexts:
  Documents:
    - Path: '/home/runner/work/extended-tests/extended-tests/NEORV32/setups/osflow/devices/ice40/neorv32_imem.ice40up_spram.vhd':
      Entities:
      Architectures:
        - Name: neorv32_imem_rtl
          File: neorv32_imem.ice40up_spram.vhd
          Position: 48:13
          Entity: neorv32_imem
          Declared:
            - constant spram_sleep_mode_en_c : boolean := false
            - constant hi_abb_c : natural := 31
            - constant lo_abb_c : natural := index_size_f(64 * 1024)
            - signal acc_en : std_ulogic
            - signal mem_cs : std_ulogic
            - signal rdata : std_ulogic_vector(31 downto 0)
            - signal rden : std_ulogic
            - signal spram_clk : std_logic
            - signal spram_addr : std_logic_vector(13 downto 0)
            - signal spram_di_lo : std_logic_vector(15 downto 0)
            - signal spram_di_hi : std_logic_vector(15 downto 0)
            - signal spram_do_lo : std_logic_vector(15 downto 0)
            - signal spram_do_hi : std_logic_vector(15 downto 0)
            - signal spram_be_lo : std_logic_vector(3 downto 0)
            - signal spram_be_hi : std_logic_vector(3 downto 0)
            - signal spram_we : std_logic
            - signal spram_pwr_n : std_logic
            - signal spram_cs : std_logic
          Hierarchy:
            - imem_spram_lo_inst: component SB_SPRAM256KA
            - imem_spram_hi_inst: component SB_SPRAM256KA
            - buffer_ff: process(...)
          Statements:
            ...
            ...
            ...
            ...
            ...
            ...
            ...
            ...
            ...
            ...
            ...
            ...
            ...
            ...
            ...
      Packages:
      PackageBodies:
      Configurations:
      Contexts:

Teardown

XPASS test_AllVHDLSources[/home/runner/work/extended-tests/extended-tests/NEORV32/setups/osflow/devices/ecp5/ecp5_components.vhd] 0:00:00.246023

Started 2021-11-23 15:22:15
Ended 2021-11-23 15:22:15
Duration 0:00:00.246023
Markers
xfail
Fixtures file

Setup

Call

Captured stdout call
================================================================================
                         pyGHDL.dom - Test Application                          
================================================================================
Parsing file '/home/runner/work/extended-tests/extended-tests/NEORV32/setups/osflow/devices/ecp5/ecp5_components.vhd'
libghdl processing time:  199.201 us
DOM translation time:    2287.612 us

Design:
  Libraries:
    - Name: pretty
      Entities:
      Packages:
        - components
      Configurations:
      Contexts:
  Documents:
    - Path: '/home/runner/work/extended-tests/extended-tests/NEORV32/setups/osflow/devices/ecp5/ecp5_components.vhd':
      Entities:
      Architectures:
      Packages:
        - Name: components
          File: ecp5_components.vhd
          Position: 4:8
          Declared:
          - Component: EHXPLLL
            Generics:
              - CLKI_DIV : in integer := 1
              - CLKFB_DIV : in integer := 1
              - CLKOP_DIV : in integer := 8
              - CLKOS_DIV : in integer := 8
              - CLKOS2_DIV : in integer := 8
              - CLKOS3_DIV : in integer := 8
              - CLKOP_ENABLE : in string := "ENABLED"
              - CLKOS_ENABLE : in string := "DISABLED"
              - CLKOS2_ENABLE : in string := "DISABLED"
              - CLKOS3_ENABLE : in string := "DISABLED"
              - CLKOP_CPHASE : in integer := 0
              - CLKOS_CPHASE : in integer := 0
              - CLKOS2_CPHASE : in integer := 0
              - CLKOS3_CPHASE : in integer := 0
              - CLKOP_FPHASE : in integer := 0
              - CLKOS_FPHASE : in integer := 0
              - CLKOS2_FPHASE : in integer := 0
              - CLKOS3_FPHASE : in integer := 0
              - FEEDBK_PATH : in string := "CLKOP"
              - CLKOP_TRIM_POL : in string := "RISING"
              - CLKOP_TRIM_DELAY : in integer := 0
              - CLKOS_TRIM_POL : in string := "RISING"
              - CLKOS_TRIM_DELAY : in integer := 0
              - OUTDIVIDER_MUXA : in string := "DIVA"
              - OUTDIVIDER_MUXB : in string := "DIVB"
              - OUTDIVIDER_MUXC : in string := "DIVC"
              - OUTDIVIDER_MUXD : in string := "DIVD"
              - PLL_LOCK_MODE : in integer := 0
              - PLL_LOCK_DELAY : in integer := 200
              - STDBY_ENABLE : in string := "DISABLED"
              - REFIN_RESET : in string := "DISABLED"
              - SYNC_ENABLE : in string := "DISABLED"
              - INT_LOCK_STICKY : in string := "ENABLED"
              - DPHASE_SOURCE : in string := "DISABLED"
              - PLLRST_ENA : in string := "DISABLED"
              - INTFB_WAKE : in string := "DISABLED"
            Ports:
              - CLKI : in std_logic := X
              - CLKFB : in std_logic := X
              - RST : in std_logic := X
              - STDBY : in std_logic := X
              - PLLWAKESYNC : in std_logic := X
              - PHASESEL1 : in std_logic := X
              - PHASESEL0 : in std_logic := X
              - PHASEDIR : in std_logic := X
              - PHASESTEP : in std_logic := X
              - PHASELOADREG : in std_logic := X
              - ENCLKOP : in std_logic := X
              - ENCLKOS : in std_logic := X
              - ENCLKOS2 : in std_logic := X
              - ENCLKOS3 : in std_logic := X
              - CLKOP : out std_logic := X
              - CLKOS : out std_logic := X
              - CLKOS2 : out std_logic := X
              - CLKOS3 : out std_logic := X
              - LOCK : out std_logic := X
              - INTLOCK : out std_logic := X
              - REFCLK : out std_logic := X
              - CLKINTFB : out std_logic := X
      PackageBodies:
      Configurations:
      Contexts:

Teardown

XPASS test_AllVHDLSources[/home/runner/work/extended-tests/extended-tests/NEORV32/setups/osflow/board_tops/neorv32_Fomu_BoardTop_UP5KDemo.vhd] 0:00:00.257451

Started 2021-11-23 15:22:15
Ended 2021-11-23 15:22:15
Duration 0:00:00.257451
Markers
xfail
Fixtures file

Setup

Call

Captured stdout call
================================================================================
                         pyGHDL.dom - Test Application                          
================================================================================
Parsing file '/home/runner/work/extended-tests/extended-tests/NEORV32/setups/osflow/board_tops/neorv32_Fomu_BoardTop_UP5KDemo.vhd'
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
libghdl processing time:  375.502 us
DOM translation time:    2742.114 us

Design:
  Libraries:
    - Name: pretty
      Entities:
        - neorv32_Fomu_BoardTop_UP5KDemo(neorv32_Fomu_BoardTop_UP5KDemo_rtl)
      Packages:
      Configurations:
      Contexts:
  Documents:
    - Path: '/home/runner/work/extended-tests/extended-tests/NEORV32/setups/osflow/board_tops/neorv32_Fomu_BoardTop_UP5KDemo.vhd':
      Entities:
        - Name: neorv32_Fomu_BoardTop_UP5KDemo
          File: neorv32_Fomu_BoardTop_UP5KDemo.vhd
          Position: 42:7
          Generics:
          Ports:
            - clki : in std_logic
            - rgb : out std_logic_vector(2 downto 0)
            - usb_dp : out std_logic
            - usb_dn : out std_logic
            - usb_dp_pu : out std_logic
          Declared:
          Statements:
          Architecures:
          - neorv32_Fomu_BoardTop_UP5KDemo_rtl
      Architectures:
        - Name: neorv32_Fomu_BoardTop_UP5KDemo_rtl
          File: neorv32_Fomu_BoardTop_UP5KDemo.vhd
          Position: 55:13
          Entity: neorv32_Fomu_BoardTop_UP5KDemo
          Declared:
            - constant f_clock_c : natural := 18000000
            - signal hf_osc_clk : std_logic
            - signal pll_rstn : std_logic
            - signal pll_clk : std_logic
            - signal con_pwm : std_ulogic_vector(2 downto 0)
            - signal con_gpio_o : std_ulogic_vector(3 downto 0)
          Hierarchy:
            - hsosc_inst: component SB_HFOSC
            - pll_inst: component SB_PLL40_CORE
            - neorv32_inst: entity work.neorv32_ProcessorTop_UP5KDemo
            - rgb_inst: component SB_RGBA_DRV
          Statements:
            ...
            ...
            ...
            ...
            ...
            ...
            ...
      Packages:
      PackageBodies:
      Configurations:
      Contexts:

Teardown

XPASS test_AllVHDLSources[/home/runner/work/extended-tests/extended-tests/NEORV32/setups/osflow/board_tops/neorv32_Fomu_BoardTop_MinimalBoot.vhd] 0:00:00.247995

Started 2021-11-23 15:22:15
Ended 2021-11-23 15:22:15
Duration 0:00:00.247995
Markers
xfail
Fixtures file

Setup

Call

Captured stdout call
================================================================================
                         pyGHDL.dom - Test Application                          
================================================================================
Parsing file '/home/runner/work/extended-tests/extended-tests/NEORV32/setups/osflow/board_tops/neorv32_Fomu_BoardTop_MinimalBoot.vhd'
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
libghdl processing time:  239.301 us
DOM translation time:    2339.412 us

Design:
  Libraries:
    - Name: pretty
      Entities:
        - neorv32_Fomu_BoardTop_MinimalBoot(neorv32_Fomu_BoardTop_MinimalBoot_rtl)
      Packages:
      Configurations:
      Contexts:
  Documents:
    - Path: '/home/runner/work/extended-tests/extended-tests/NEORV32/setups/osflow/board_tops/neorv32_Fomu_BoardTop_MinimalBoot.vhd':
      Entities:
        - Name: neorv32_Fomu_BoardTop_MinimalBoot
          File: neorv32_Fomu_BoardTop_MinimalBoot.vhd
          Position: 42:7
          Generics:
          Ports:
            - clki : in std_logic
            - rgb : out std_logic_vector(2 downto 0)
            - usb_dp : out std_logic
            - usb_dn : out std_logic
            - usb_dp_pu : out std_logic
          Declared:
          Statements:
          Architecures:
          - neorv32_Fomu_BoardTop_MinimalBoot_rtl
      Architectures:
        - Name: neorv32_Fomu_BoardTop_MinimalBoot_rtl
          File: neorv32_Fomu_BoardTop_MinimalBoot.vhd
          Position: 55:13
          Entity: neorv32_Fomu_BoardTop_MinimalBoot
          Declared:
            - constant f_clock_c : natural := 18000000
            - signal hf_osc_clk : std_logic
            - signal pll_rstn : std_logic
            - signal pll_clk : std_logic
            - signal con_gpio_o : std_ulogic_vector(3 downto 0)
            - signal con_pwm : std_logic_vector(2 downto 0)
          Hierarchy:
            - hsosc_inst: component SB_HFOSC
            - pll_inst: component SB_PLL40_CORE
            - neorv32_inst: entity work.neorv32_ProcessorTop_MinimalBoot
            - rgb_inst: component SB_RGBA_DRV
          Statements:
            ...
            ...
            ...
            ...
            ...
            ...
            ...
      Packages:
      PackageBodies:
      Configurations:
      Contexts:

Teardown

XPASS test_AllVHDLSources[/home/runner/work/extended-tests/extended-tests/NEORV32/setups/osflow/board_tops/neorv32_ULX3S_BoardTop_MinimalBoot.vhd] 0:00:00.253276

Started 2021-11-23 15:22:15
Ended 2021-11-23 15:22:16
Duration 0:00:00.253276
Markers
xfail
Fixtures file

Setup

Call

Captured stdout call
================================================================================
                         pyGHDL.dom - Test Application                          
================================================================================
Parsing file '/home/runner/work/extended-tests/extended-tests/NEORV32/setups/osflow/board_tops/neorv32_ULX3S_BoardTop_MinimalBoot.vhd'
libghdl processing time:  171.301 us
DOM translation time:    1948.310 us

Design:
  Libraries:
    - Name: pretty
      Entities:
        - neorv32_ULX3S_BoardTop_MinimalBoot(neorv32_ULX3S_BoardTop_MinimalBoot_rtl)
      Packages:
      Configurations:
      Contexts:
  Documents:
    - Path: '/home/runner/work/extended-tests/extended-tests/NEORV32/setups/osflow/board_tops/neorv32_ULX3S_BoardTop_MinimalBoot.vhd':
      Entities:
        - Name: neorv32_ULX3S_BoardTop_MinimalBoot
          File: neorv32_ULX3S_BoardTop_MinimalBoot.vhd
          Position: 42:7
          Generics:
          Ports:
            - ULX3S_CLK : in std_logic
            - ULX3S_RST_N : in std_logic
            - ULX3S_LED0 : out std_logic
            - ULX3S_LED1 : out std_logic
            - ULX3S_LED2 : out std_logic
            - ULX3S_LED3 : out std_logic
            - ULX3S_LED4 : out std_logic
            - ULX3S_LED5 : out std_logic
            - ULX3S_LED6 : out std_logic
            - ULX3S_LED7 : out std_logic
            - ULX3S_RX : in std_logic
            - ULX3S_TX : out std_logic
          Declared:
          Statements:
          Architecures:
          - neorv32_ULX3S_BoardTop_MinimalBoot_rtl
      Architectures:
        - Name: neorv32_ULX3S_BoardTop_MinimalBoot_rtl
          File: neorv32_ULX3S_BoardTop_MinimalBoot.vhd
          Position: 62:13
          Entity: neorv32_ULX3S_BoardTop_MinimalBoot
          Declared:
            - constant f_clock_c : natural := 25000000
            - signal con_pwm : std_logic_vector(2 downto 0)
            - signal con_gpio_o : std_ulogic_vector(3 downto 0)
          Hierarchy:
            - neorv32_inst: entity work.neorv32_ProcessorTop_MinimalBoot
          Statements:
            ...
            ...
            ...
            ...
            ...
            ...
            ...
            ...
            ...
      Packages:
      PackageBodies:
      Configurations:
      Contexts:

Teardown

XPASS test_AllVHDLSources[/home/runner/work/extended-tests/extended-tests/NEORV32/setups/osflow/board_tops/neorv32_AlhambraII_BoardTop_MinimalBoot.vhd] 0:00:00.252820

Started 2021-11-23 15:22:15
Ended 2021-11-23 15:22:16
Duration 0:00:00.252820
Markers
xfail
Fixtures file

Setup

Call

Captured stdout call
================================================================================
                         pyGHDL.dom - Test Application                          
================================================================================
Parsing file '/home/runner/work/extended-tests/extended-tests/NEORV32/setups/osflow/board_tops/neorv32_AlhambraII_BoardTop_MinimalBoot.vhd'
libghdl processing time:  216.201 us
DOM translation time:    2602.913 us

Design:
  Libraries:
    - Name: pretty
      Entities:
        - neorv32_AlhambraII_BoardTop_MinimalBoot(neorv32_AlhambraII_BoardTop_MinimalBoot_rtl)
      Packages:
      Configurations:
      Contexts:
  Documents:
    - Path: '/home/runner/work/extended-tests/extended-tests/NEORV32/setups/osflow/board_tops/neorv32_AlhambraII_BoardTop_MinimalBoot.vhd':
      Entities:
        - Name: neorv32_AlhambraII_BoardTop_MinimalBoot
          File: neorv32_AlhambraII_BoardTop_MinimalBoot.vhd
          Position: 42:7
          Generics:
          Ports:
            - AlhambraII_CLK : in std_logic
            - AlhambraII_LED0 : out std_logic
            - AlhambraII_LED1 : out std_logic
            - AlhambraII_LED2 : out std_logic
            - AlhambraII_LED3 : out std_logic
            - AlhambraII_LED4 : out std_logic
            - AlhambraII_LED5 : out std_logic
            - AlhambraII_LED6 : out std_logic
            - AlhambraII_LED7 : out std_logic
            - AlhambraII_RX : in std_logic
            - AlhambraII_TX : out std_logic
          Declared:
          Statements:
          Architecures:
          - neorv32_AlhambraII_BoardTop_MinimalBoot_rtl
      Architectures:
        - Name: neorv32_AlhambraII_BoardTop_MinimalBoot_rtl
          File: neorv32_AlhambraII_BoardTop_MinimalBoot.vhd
          Position: 61:13
          Entity: neorv32_AlhambraII_BoardTop_MinimalBoot
          Declared:
            - constant f_clock_c : natural := 12000000
            - signal rst_cnt : std_logic_vector(8 downto 0) := (others => 0)
            - signal sys_rstn : std_logic
            - signal con_gpio_o : std_ulogic_vector(3 downto 0)
            - signal con_pwm : std_logic_vector(2 downto 0)
          Hierarchy:
            - reset_generator: process(...)
            - neorv32_inst: entity work.neorv32_ProcessorTop_MinimalBoot
          Statements:
            ...
            ...
            ...
            ...
            ...
            ...
            ...
            ...
            ...
            ...
            ...
      Packages:
      PackageBodies:
      Configurations:
      Contexts:

Teardown

XPASS test_AllVHDLSources[/home/runner/work/extended-tests/extended-tests/NEORV32/setups/osflow/board_tops/neorv32_UPduino_BoardTop_UP5KDemo.vhd] 0:00:00.248277

Started 2021-11-23 15:22:16
Ended 2021-11-23 15:22:16
Duration 0:00:00.248277
Markers
xfail
Fixtures file

Setup

Call

Captured stdout call
================================================================================
                         pyGHDL.dom - Test Application                          
================================================================================
Parsing file '/home/runner/work/extended-tests/extended-tests/NEORV32/setups/osflow/board_tops/neorv32_UPduino_BoardTop_UP5KDemo.vhd'
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Concurrent (conditional) signal assignment (label: 'None') at line 183
libghdl processing time:  300.502 us
DOM translation time:    3334.516 us

Design:
  Libraries:
    - Name: pretty
      Entities:
        - neorv32_UPduino_BoardTop_UP5KDemo(neorv32_UPduino_BoardTop_UP5KDemo_rtl)
      Packages:
      Configurations:
      Contexts:
  Documents:
    - Path: '/home/runner/work/extended-tests/extended-tests/NEORV32/setups/osflow/board_tops/neorv32_UPduino_BoardTop_UP5KDemo.vhd':
      Entities:
        - Name: neorv32_UPduino_BoardTop_UP5KDemo
          File: neorv32_UPduino_BoardTop_UP5KDemo.vhd
          Position: 42:7
          Generics:
          Ports:
            - uart_txd_o : out std_ulogic
            - uart_rxd_i : in std_ulogic
            - flash_sck_o : out std_ulogic
            - flash_sdo_o : out std_ulogic
            - flash_sdi_i : in std_ulogic
            - flash_csn_o : out std_ulogic
            - spi_sck_o : out std_ulogic
            - spi_sdo_o : out std_ulogic
            - spi_sdi_i : in std_ulogic
            - spi_csn_o : out std_ulogic
            - twi_sda_io : inout std_logic
            - twi_scl_io : inout std_logic
            - gpio_i : in std_ulogic_vector(3 downto 0)
            - gpio_o : out std_ulogic_vector(3 downto 0)
            - pwm_o : out std_ulogic_vector(2 downto 0)
          Declared:
          Statements:
          Architecures:
          - neorv32_UPduino_BoardTop_UP5KDemo_rtl
      Architectures:
        - Name: neorv32_UPduino_BoardTop_UP5KDemo_rtl
          File: neorv32_UPduino_BoardTop_UP5KDemo.vhd
          Position: 68:13
          Entity: neorv32_UPduino_BoardTop_UP5KDemo
          Declared:
            - constant f_clock_c : natural := 18000000
            - signal hf_osc_clk : std_logic
            - signal pll_rstn : std_logic
            - signal pll_clk : std_logic
            - signal con_pwm : std_ulogic_vector(2 downto 0)
            - signal con_spi_sdi : std_ulogic
            - signal con_spi_csn : std_ulogic
          Hierarchy:
            - hsosc_inst: component SB_HFOSC
            - pll_inst: component SB_PLL40_CORE
            - neorv32_inst: entity work.neorv32_ProcessorTop_UP5KDemo
            - rgb_inst: component SB_RGBA_DRV
          Statements:
            ...
            ...
            ...
            ...
            ...
      Packages:
      PackageBodies:
      Configurations:
      Contexts:

Teardown

XPASS test_AllVHDLSources[/home/runner/work/extended-tests/extended-tests/NEORV32/setups/osflow/board_tops/neorv32_UPduino_BoardTop_MinimalBoot.vhd] 0:00:00.257619

Started 2021-11-23 15:22:16
Ended 2021-11-23 15:22:16
Duration 0:00:00.257619
Markers
xfail
Fixtures file

Setup

Call

Captured stdout call
================================================================================
                         pyGHDL.dom - Test Application                          
================================================================================
Parsing file '/home/runner/work/extended-tests/extended-tests/NEORV32/setups/osflow/board_tops/neorv32_UPduino_BoardTop_MinimalBoot.vhd'
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
libghdl processing time:  223.401 us
DOM translation time:    2226.711 us

Design:
  Libraries:
    - Name: pretty
      Entities:
        - neorv32_UPduino_BoardTop_MinimalBoot(neorv32_UPduino_BoardTop_MinimalBoot_rtl)
      Packages:
      Configurations:
      Contexts:
  Documents:
    - Path: '/home/runner/work/extended-tests/extended-tests/NEORV32/setups/osflow/board_tops/neorv32_UPduino_BoardTop_MinimalBoot.vhd':
      Entities:
        - Name: neorv32_UPduino_BoardTop_MinimalBoot
          File: neorv32_UPduino_BoardTop_MinimalBoot.vhd
          Position: 42:7
          Generics:
          Ports:
            - uart_txd_o : out std_ulogic
            - uart_rxd_i : in std_ulogic
            - gpio_o : out std_ulogic_vector(3 downto 0)
            - pwm_o : out std_logic_vector(2 downto 0)
          Declared:
          Statements:
          Architecures:
          - neorv32_UPduino_BoardTop_MinimalBoot_rtl
      Architectures:
        - Name: neorv32_UPduino_BoardTop_MinimalBoot_rtl
          File: neorv32_UPduino_BoardTop_MinimalBoot.vhd
          Position: 54:13
          Entity: neorv32_UPduino_BoardTop_MinimalBoot
          Declared:
            - constant f_clock_c : natural := 18000000
            - signal hf_osc_clk : std_logic
            - signal pll_rstn : std_logic
            - signal pll_clk : std_logic
            - signal con_pwm : std_logic_vector(2 downto 0)
          Hierarchy:
            - hsosc_inst: component SB_HFOSC
            - pll_inst: component SB_PLL40_CORE
            - neorv32_inst: entity work.neorv32_ProcessorTop_MinimalBoot
            - rgb_inst: component SB_RGBA_DRV
          Statements:
            ...
            ...
            ...
            ...
      Packages:
      PackageBodies:
      Configurations:
      Contexts:

Teardown

XPASS test_AllVHDLSources[/home/runner/work/extended-tests/extended-tests/NEORV32/setups/osflow/board_tops/neorv32_Fomu_BoardTop_MixedLanguage.vhd] 0:00:00.254693

Started 2021-11-23 15:22:16
Ended 2021-11-23 15:22:16
Duration 0:00:00.254693
Markers
xfail
Fixtures file

Setup

Call

Captured stdout call
================================================================================
                         pyGHDL.dom - Test Application                          
================================================================================
Parsing file '/home/runner/work/extended-tests/extended-tests/NEORV32/setups/osflow/board_tops/neorv32_Fomu_BoardTop_MixedLanguage.vhd'
libghdl processing time:  223.201 us
DOM translation time:    2115.210 us

Design:
  Libraries:
    - Name: pretty
      Entities:
        - neorv32_Fomu_BoardTop_MixedLanguage(neorv32_Fomu_BoardTop_MixedLanguage_rtl)
      Packages:
      Configurations:
      Contexts:
  Documents:
    - Path: '/home/runner/work/extended-tests/extended-tests/NEORV32/setups/osflow/board_tops/neorv32_Fomu_BoardTop_MixedLanguage.vhd':
      Entities:
        - Name: neorv32_Fomu_BoardTop_MixedLanguage
          File: neorv32_Fomu_BoardTop_MixedLanguage.vhd
          Position: 42:7
          Generics:
          Ports:
            - clki : in std_logic
            - rgb : out std_logic_vector(2 downto 0)
            - usb_dp : out std_logic
            - usb_dn : out std_logic
            - usb_dp_pu : out std_logic
          Declared:
          Statements:
          Architecures:
          - neorv32_Fomu_BoardTop_MixedLanguage_rtl
      Architectures:
        - Name: neorv32_Fomu_BoardTop_MixedLanguage_rtl
          File: neorv32_Fomu_BoardTop_MixedLanguage.vhd
          Position: 55:13
          Entity: neorv32_Fomu_BoardTop_MixedLanguage
          Declared:
            - constant f_clock_c : natural := 18000000
            - Component: neorv32_Fomu_MixedLanguage_ClkGen
              Generics:
              Ports:
                - clk_o : out std_logic
                - rstn_o : out std_logic
            - signal pll_rstn : std_logic
            - signal pll_clk : std_logic
            - signal con_gpio_o : std_ulogic_vector(3 downto 0)
            - signal con_pwm : std_logic_vector(2 downto 0)
          Hierarchy:
            - clk_inst: component neorv32_Fomu_MixedLanguage_ClkGen
            - neorv32_inst: entity work.neorv32_ProcessorTop_MinimalBoot
            - rgb_inst: component SB_RGBA_DRV
          Statements:
            ...
            ...
            ...
            ...
            ...
            ...
      Packages:
      PackageBodies:
      Configurations:
      Contexts:

Teardown

XPASS test_AllVHDLSources[/home/runner/work/extended-tests/extended-tests/NEORV32/setups/osflow/board_tops/neorv32_iCESugar_BoardTop_Minimal.vhd] 0:00:00.260364

Started 2021-11-23 15:22:16
Ended 2021-11-23 15:22:16
Duration 0:00:00.260364
Markers
xfail
Fixtures file

Setup

Call

Captured stdout call
================================================================================
                         pyGHDL.dom - Test Application                          
================================================================================
Parsing file '/home/runner/work/extended-tests/extended-tests/NEORV32/setups/osflow/board_tops/neorv32_iCESugar_BoardTop_Minimal.vhd'
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
libghdl processing time:  254.201 us
DOM translation time:    2400.612 us

Design:
  Libraries:
    - Name: pretty
      Entities:
        - neorv32_iCESugar_BoardTop_Minimal(neorv32_iCESugar_BoardTop_Minimal_rtl)
      Packages:
      Configurations:
      Contexts:
  Documents:
    - Path: '/home/runner/work/extended-tests/extended-tests/NEORV32/setups/osflow/board_tops/neorv32_iCESugar_BoardTop_Minimal.vhd':
      Entities:
        - Name: neorv32_iCESugar_BoardTop_Minimal
          File: neorv32_iCESugar_BoardTop_Minimal.vhd
          Position: 42:7
          Generics:
          Ports:
            - iCESugarv15_CLK : in std_logic
            - iCESugarv15_RX : in std_logic
            - iCESugarv15_TX : out std_logic
            - iCESugarv15_LED_R : out std_logic
            - iCESugarv15_LED_G : out std_logic
            - iCESugarv15_LED_B : out std_logic
            - iCESugarv15_USB_DP : out std_logic
            - iCESugarv15_USB_DN : out std_logic
            - iCESugarv15_USB_DP_PU : out std_logic
          Declared:
          Statements:
          Architecures:
          - neorv32_iCESugar_BoardTop_Minimal_rtl
      Architectures:
        - Name: neorv32_iCESugar_BoardTop_Minimal_rtl
          File: neorv32_iCESugar_BoardTop_Minimal.vhd
          Position: 60:13
          Entity: neorv32_iCESugar_BoardTop_Minimal
          Declared:
            - constant f_clock_c : natural := 22000000
            - signal pll_rstn : std_logic
            - signal pll_clk : std_logic
            - signal con_gpio_o : std_ulogic_vector(3 downto 0)
            - signal con_pwm : std_logic_vector(2 downto 0)
          Hierarchy:
            - pll_inst: component SB_PLL40_PAD
            - neorv32_inst: entity work.neorv32_ProcessorTop_MinimalBoot
            - rgb_inst: component SB_RGBA_DRV
          Statements:
            ...
            ...
            ...
            ...
            ...
            ...
      Packages:
      PackageBodies:
      Configurations:
      Contexts:

Teardown

XPASS test_AllVHDLSources[/home/runner/work/extended-tests/extended-tests/NEORV32/setups/osflow/board_tops/neorv32_iCESugar_BoardTop_MinimalBoot.vhd] 0:00:00.255125

Started 2021-11-23 15:22:16
Ended 2021-11-23 15:22:16
Duration 0:00:00.255125
Markers
xfail
Fixtures file

Setup

Call

Captured stdout call
================================================================================
                         pyGHDL.dom - Test Application                          
================================================================================
Parsing file '/home/runner/work/extended-tests/extended-tests/NEORV32/setups/osflow/board_tops/neorv32_iCESugar_BoardTop_MinimalBoot.vhd'
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
libghdl processing time:  321.702 us
DOM translation time:    2528.512 us

Design:
  Libraries:
    - Name: pretty
      Entities:
        - neorv32_iCESugar_BoardTop_MinimalBoot(neorv32_iCESugar_BoardTop_MinimalBoot_rtl)
      Packages:
      Configurations:
      Contexts:
  Documents:
    - Path: '/home/runner/work/extended-tests/extended-tests/NEORV32/setups/osflow/board_tops/neorv32_iCESugar_BoardTop_MinimalBoot.vhd':
      Entities:
        - Name: neorv32_iCESugar_BoardTop_MinimalBoot
          File: neorv32_iCESugar_BoardTop_MinimalBoot.vhd
          Position: 42:7
          Generics:
          Ports:
            - iCESugarv15_LED_R : out std_logic
            - iCESugarv15_LED_G : out std_logic
            - iCESugarv15_LED_B : out std_logic
            - iCESugarv15_RX : in std_logic
            - iCESugarv15_TX : out std_logic
            - iCESugarv15_USB_DP : out std_logic
            - iCESugarv15_USB_DN : out std_logic
            - iCESugarv15_USB_DP_PU : out std_logic
          Declared:
          Statements:
          Architecures:
          - neorv32_iCESugar_BoardTop_MinimalBoot_rtl
      Architectures:
        - Name: neorv32_iCESugar_BoardTop_MinimalBoot_rtl
          File: neorv32_iCESugar_BoardTop_MinimalBoot.vhd
          Position: 58:13
          Entity: neorv32_iCESugar_BoardTop_MinimalBoot
          Declared:
            - constant f_clock_c : natural := 18000000
            - signal hf_osc_clk : std_logic
            - signal pll_rstn : std_logic
            - signal pll_clk : std_logic
            - signal con_gpio_o : std_ulogic_vector(3 downto 0)
            - signal con_pwm : std_logic_vector(2 downto 0)
          Hierarchy:
            - hsosc_inst: component SB_HFOSC
            - pll_inst: component SB_PLL40_CORE
            - neorv32_inst: entity work.neorv32_ProcessorTop_MinimalBoot
            - rgb_inst: component SB_RGBA_DRV
          Statements:
            ...
            ...
            ...
            ...
            ...
            ...
            ...
      Packages:
      PackageBodies:
      Configurations:
      Contexts:

Teardown

XPASS test_AllVHDLSources[/home/runner/work/extended-tests/extended-tests/NEORV32/setups/osflow/board_tops/neorv32_Fomu_BoardTop_Minimal.vhd] 0:00:00.243943

Started 2021-11-23 15:22:16
Ended 2021-11-23 15:22:17
Duration 0:00:00.243943
Markers
xfail
Fixtures file

Setup

Call

Captured stdout call
================================================================================
                         pyGHDL.dom - Test Application                          
================================================================================
Parsing file '/home/runner/work/extended-tests/extended-tests/NEORV32/setups/osflow/board_tops/neorv32_Fomu_BoardTop_Minimal.vhd'
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
libghdl processing time:  198.601 us
DOM translation time:    2141.711 us

Design:
  Libraries:
    - Name: pretty
      Entities:
        - neorv32_Fomu_BoardTop_Minimal(neorv32_Fomu_BoardTop_Minimal_rtl)
      Packages:
      Configurations:
      Contexts:
  Documents:
    - Path: '/home/runner/work/extended-tests/extended-tests/NEORV32/setups/osflow/board_tops/neorv32_Fomu_BoardTop_Minimal.vhd':
      Entities:
        - Name: neorv32_Fomu_BoardTop_Minimal
          File: neorv32_Fomu_BoardTop_Minimal.vhd
          Position: 42:7
          Generics:
          Ports:
            - clki : in std_logic
            - rgb : out std_logic_vector(2 downto 0)
            - usb_dp : out std_logic
            - usb_dn : out std_logic
            - usb_dp_pu : out std_logic
          Declared:
          Statements:
          Architecures:
          - neorv32_Fomu_BoardTop_Minimal_rtl
      Architectures:
        - Name: neorv32_Fomu_BoardTop_Minimal_rtl
          File: neorv32_Fomu_BoardTop_Minimal.vhd
          Position: 55:13
          Entity: neorv32_Fomu_BoardTop_Minimal
          Declared:
            - constant f_clock_c : natural := 22000000
            - signal pll_rstn : std_logic
            - signal pll_clk : std_logic
            - signal con_pwm : std_logic_vector(2 downto 0)
          Hierarchy:
            - pll_inst: component SB_PLL40_CORE
            - neorv32_inst: entity work.neorv32_ProcessorTop_Minimal
            - rgb_inst: component SB_RGBA_DRV
          Statements:
            ...
            ...
            ...
            ...
            ...
            ...
      Packages:
      PackageBodies:
      Configurations:
      Contexts:

Teardown

XPASS test_AllVHDLSources[/home/runner/work/extended-tests/extended-tests/NEORV32/setups/osflow/board_tops/neorv32_OrangeCrab_BoardTop_MinimalBoot.vhd] 0:00:00.247032

Started 2021-11-23 15:22:16
Ended 2021-11-23 15:22:17
Duration 0:00:00.247032
Markers
xfail
Fixtures file

Setup

Call

Captured stdout call
================================================================================
                         pyGHDL.dom - Test Application                          
================================================================================
Parsing file '/home/runner/work/extended-tests/extended-tests/NEORV32/setups/osflow/board_tops/neorv32_OrangeCrab_BoardTop_MinimalBoot.vhd'
libghdl processing time:  210.501 us
DOM translation time:    2273.912 us

Design:
  Libraries:
    - Name: pretty
      Entities:
        - neorv32_OrangeCrab_BoardTop_MinimalBoot(neorv32_OrangeCrab_BoardTop_MinimalBoot_rtl)
      Packages:
      Configurations:
      Contexts:
  Documents:
    - Path: '/home/runner/work/extended-tests/extended-tests/NEORV32/setups/osflow/board_tops/neorv32_OrangeCrab_BoardTop_MinimalBoot.vhd':
      Entities:
        - Name: neorv32_OrangeCrab_BoardTop_MinimalBoot
          File: neorv32_OrangeCrab_BoardTop_MinimalBoot.vhd
          Position: 42:7
          Generics:
          Ports:
            - OrangeCrab_CLK : in std_logic
            - OrangeCrab_RST_N : in std_logic
            - OrangeCrab_LED_RGB_R : out std_logic
            - OrangeCrab_LED_RGB_G : out std_logic
            - OrangeCrab_LED_RGB_B : out std_logic
            - OrangeCrab_GPIO_0 : in std_logic
            - OrangeCrab_GPIO_1 : out std_logic
            - OrangeCrab_GPIO_9 : out std_logic
            - OrangeCrab_USB_D_P : out std_logic
            - OrangeCrab_USB_D_N : out std_logic
            - OrangeCrab_USB_DP_PU : out std_logic
          Declared:
          Statements:
          Architecures:
          - neorv32_OrangeCrab_BoardTop_MinimalBoot_rtl
      Architectures:
        - Name: neorv32_OrangeCrab_BoardTop_MinimalBoot_rtl
          File: neorv32_OrangeCrab_BoardTop_MinimalBoot.vhd
          Position: 62:13
          Entity: neorv32_OrangeCrab_BoardTop_MinimalBoot
          Declared:
            - constant f_clock_c : natural := 24000000
            - signal pll_clk : std_logic
            - signal con_pwm : std_logic_vector(2 downto 0)
            - signal con_gpio_o : std_ulogic_vector(3 downto 0)
          Hierarchy:
            - pll_inst: component EHXPLLL
            - neorv32_inst: entity work.neorv32_ProcessorTop_MinimalBoot
          Statements:
            ...
            ...
            ...
            ...
            ...
            ...
            ...
            ...
      Packages:
      PackageBodies:
      Configurations:
      Contexts:

Teardown

XPASS test_AllVHDLSources[/home/runner/work/extended-tests/extended-tests/NEORV32/setups/quartus/neorv32_qsys_component/neorv32_qsys.vhd] 0:00:00.256823

Started 2021-11-23 15:22:17
Ended 2021-11-23 15:22:17
Duration 0:00:00.256823
Markers
xfail
Fixtures file

Setup

Call

Captured stdout call
================================================================================
                         pyGHDL.dom - Test Application                          
================================================================================
Parsing file '/home/runner/work/extended-tests/extended-tests/NEORV32/setups/quartus/neorv32_qsys_component/neorv32_qsys.vhd'
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Concurrent (conditional) signal assignment (label: 'None') at line 269
[NOT IMPLEMENTED] Concurrent (conditional) signal assignment (label: 'None') at line 270
libghdl processing time:  466.402 us
DOM translation time:    7420.137 us

Design:
  Libraries:
    - Name: pretty
      Entities:
        - neorv32_qsys(neorv32_qsys_rtl)
      Packages:
      Configurations:
      Contexts:
  Documents:
    - Path: '/home/runner/work/extended-tests/extended-tests/NEORV32/setups/quartus/neorv32_qsys_component/neorv32_qsys.vhd':
      Entities:
        - Name: neorv32_qsys
          File: neorv32_qsys.vhd
          Position: 44:7
          Generics:
            - GUI_CLOCK_FREQUENCY : in integer := 100000000
            - GUI_EMABLE_INTERNAL_IMEM : in integer := 1
            - GUI_IMEM_SIZE : in integer := 16
            - GUI_EMABLE_INTERNAL_DMEM : in integer := 1
            - GUI_DMEM_SIZE : in integer := 8
            - GUI_ENABLE_BOOTLOADER : in integer := 0
            - GUI_ENABLE_AVALONMM : in integer := 1
            - GUI_ENABLE_UART0 : in integer := 1
            - GUI_ENABLE_UART1 : in integer := 0
            - GUI_ENABLE_GPIO : in integer := 0
          Ports:
            - clk_i : in std_logic := 0
            - rstn_i : in std_logic := 0
            - gpio_o : out std_logic_vector(63 downto 0)
            - gpio_i : in std_logic_vector(63 downto 0) := (others => 0)
            - uart0_txd_o : out std_logic
            - uart0_rxd_i : in std_logic := 0
            - uart1_txd_o : out std_logic
            - uart1_rxd_i : in std_logic := 0
            - read : out std_logic
            - write : out std_logic
            - waitrequest : in std_logic := 0
            - byteenable : out std_logic_vector(3 downto 0)
            - address : out std_logic_vector(31 downto 0)
            - writedata : out std_logic_vector(31 downto 0)
            - readdata : in std_logic_vector(31 downto 0) := (others => 0)
          Declared:
          Statements:
          Architecures:
          - neorv32_qsys_rtl
      Architectures:
        - Name: neorv32_qsys_rtl
          File: neorv32_qsys.vhd
          Position: 84:13
          Entity: neorv32_qsys
          Declared:
            - signal gpio_i_ulogic : std_ulogic_vector(63 downto 0)
            - signal gpio_o_ulogic : std_ulogic_vector(63 downto 0)
            - signal wb_tag_o : std_ulogic_vector(2 downto 0)
            - signal wb_adr_o : std_ulogic_vector(31 downto 0)
            - signal wb_dat_i : std_ulogic_vector(31 downto 0)
            - signal wb_dat_o : std_ulogic_vector(31 downto 0)
            - signal wb_we_o : std_ulogic
            - signal wb_sel_o : std_ulogic_vector(3 downto 0)
            - signal wb_stb_o : std_ulogic
            - signal wb_cyc_o : std_ulogic
            - signal wb_lock_o : std_ulogic
            - signal wb_ack_i : std_ulogic
            - signal wb_err_i : std_ulogic
            - signal reset : std_logic
            - function integer2bool return boolean
          Hierarchy:
            - neorv32_top_inst: component neorv32_top
          Statements:
            ...
            ...
            ...
            ...
            ...
            ...
            ...
            ...
            ...
            ...
      Packages:
      PackageBodies:
      Configurations:
      Contexts:

Teardown

XPASS test_AllVHDLSources[/home/runner/work/extended-tests/extended-tests/NEORV32/setups/quartus/de0-nano-test-setup-qsys/neorv32_ProcessorTop_Test.vhd] 0:00:00.248735

Started 2021-11-23 15:22:17
Ended 2021-11-23 15:22:17
Duration 0:00:00.248735
Markers
xfail
Fixtures file

Setup

Call

Captured stdout call
================================================================================
                         pyGHDL.dom - Test Application                          
================================================================================
Parsing file '/home/runner/work/extended-tests/extended-tests/NEORV32/setups/quartus/de0-nano-test-setup-qsys/neorv32_ProcessorTop_Test.vhd'
libghdl processing time:  187.601 us
DOM translation time:    1523.308 us

Design:
  Libraries:
    - Name: pretty
      Entities:
        - neorv32_ProcessorTop_Test(rtl)
      Packages:
      Configurations:
      Contexts:
  Documents:
    - Path: '/home/runner/work/extended-tests/extended-tests/NEORV32/setups/quartus/de0-nano-test-setup-qsys/neorv32_ProcessorTop_Test.vhd':
      Entities:
        - Name: neorv32_ProcessorTop_Test
          File: neorv32_ProcessorTop_Test.vhd
          Position: 7:7
          Generics:
          Ports:
            - clk_i : in std_logic
            - rstn_i : in std_logic
            - gpio_o : out std_logic_vector(7 downto 0)
            - uart0_txd_o : out std_logic
            - uart0_rxd_i : in std_logic
          Declared:
          Statements:
          Architecures:
          - rtl
      Architectures:
        - Name: rtl
          File: neorv32_ProcessorTop_Test.vhd
          Position: 16:13
          Entity: neorv32_ProcessorTop_Test
          Declared:
            - Component: neorv32_test_qsys
              Generics:
              Ports:
                - clk_clk : in std_logic
                - perf_uart0_uart0_txd_o : out std_logic
                - perf_uart0_uart0_rxd_i : in std_logic
                - perf_gpio_gpio_o : out std_logic_vector(31 downto 0)
                - perf_gpio_gpio_i : in std_logic_vector(31 downto 0)
                - reset_reset_n : in std_logic
            - signal perf_gpio_gpio_o : std_logic_vector(31 downto 0)
          Hierarchy:
            - my_riscv_core: component neorv32_test_qsys
          Statements:
            ...
            ...
      Packages:
      PackageBodies:
      Configurations:
      Contexts:

Teardown

XPASS test_AllVHDLSources[/home/runner/work/extended-tests/extended-tests/NEORV32/setups/quartus/de0-nano-test-setup-avalonmm-wrapper/neorv32_test_setup_avalonmm.vhd] 0:00:00.265895

Started 2021-11-23 15:22:17
Ended 2021-11-23 15:22:17
Duration 0:00:00.265895
Markers
xfail
Fixtures file

Setup

Call

Captured stdout call
================================================================================
                         pyGHDL.dom - Test Application                          
================================================================================
Parsing file '/home/runner/work/extended-tests/extended-tests/NEORV32/setups/quartus/de0-nano-test-setup-avalonmm-wrapper/neorv32_test_setup_avalonmm.vhd'
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Concurrent (conditional) signal assignment (label: 'None') at line 314
libghdl processing time:  626.203 us
DOM translation time:    7904.940 us

Design:
  Libraries:
    - Name: pretty
      Entities:
        - neorv32_test_setup_avalonmm(neorv32_test_setup_avalonmm_rtl)
      Packages:
      Configurations:
      Contexts:
  Documents:
    - Path: '/home/runner/work/extended-tests/extended-tests/NEORV32/setups/quartus/de0-nano-test-setup-avalonmm-wrapper/neorv32_test_setup_avalonmm.vhd':
      Entities:
        - Name: neorv32_test_setup_avalonmm
          File: neorv32_test_setup_avalonmm.vhd
          Position: 46:7
          Generics:
            - CLOCK_FREQUENCY : in natural := 50000000
            - MEM_INT_IMEM_SIZE : in natural := 16 * 1024
            - MEM_INT_DMEM_SIZE : in natural := 8 * 1024
          Ports:
            - clk_i : in std_ulogic
            - rstn_i : in std_ulogic
            - gpio_o : out std_ulogic_vector(7 downto 0)
            - uart0_txd_o : out std_ulogic
            - uart0_rxd_i : in std_ulogic
          Declared:
          Statements:
          Architecures:
          - neorv32_test_setup_avalonmm_rtl
      Architectures:
        - Name: neorv32_test_setup_avalonmm_rtl
          File: neorv32_test_setup_avalonmm.vhd
          Position: 65:13
          Entity: neorv32_test_setup_avalonmm
          Declared:
            - Component: neorv32_top_avalonmm
              Generics:
                - CLOCK_FREQUENCY : in natural
                - HW_THREAD_ID : in natural := 0
                - INT_BOOTLOADER_EN : in boolean := false
                - ON_CHIP_DEBUGGER_EN : in boolean := false
                - CPU_EXTENSION_RISCV_A : in boolean := false
                - CPU_EXTENSION_RISCV_B : in boolean := false
                - CPU_EXTENSION_RISCV_C : in boolean := false
                - CPU_EXTENSION_RISCV_E : in boolean := false
                - CPU_EXTENSION_RISCV_M : in boolean := false
                - CPU_EXTENSION_RISCV_U : in boolean := false
                - CPU_EXTENSION_RISCV_Zfinx : in boolean := false
                - CPU_EXTENSION_RISCV_Zicsr : in boolean := true
                - CPU_EXTENSION_RISCV_Zifencei : in boolean := false
                - CPU_EXTENSION_RISCV_Zmmul : in boolean := false
                - FAST_MUL_EN : in boolean := false
                - FAST_SHIFT_EN : in boolean := false
                - CPU_CNT_WIDTH : in natural := 64
                - CPU_IPB_ENTRIES : in natural := 2
                - PMP_NUM_REGIONS : in natural := 0
                - PMP_MIN_GRANULARITY : in natural := 64 * 1024
                - HPM_NUM_CNTS : in natural := 0
                - HPM_CNT_WIDTH : in natural := 40
                - MEM_INT_IMEM_EN : in boolean := false
                - MEM_INT_IMEM_SIZE : in natural := 16 * 1024
                - MEM_INT_DMEM_EN : in boolean := false
                - MEM_INT_DMEM_SIZE : in natural := 8 * 1024
                - ICACHE_EN : in boolean := false
                - ICACHE_NUM_BLOCKS : in natural := 4
                - ICACHE_BLOCK_SIZE : in natural := 64
                - ICACHE_ASSOCIATIVITY : in natural := 1
                - SLINK_NUM_TX : in natural := 0
                - SLINK_NUM_RX : in natural := 0
                - SLINK_TX_FIFO : in natural := 1
                - SLINK_RX_FIFO : in natural := 1
                - XIRQ_NUM_CH : in natural := 0
                - XIRQ_TRIGGER_TYPE : in std_ulogic_vector(31 downto 0)
                - XIRQ_TRIGGER_POLARITY : in std_ulogic_vector(31 downto 0)
                - IO_GPIO_EN : in boolean := false
                - IO_MTIME_EN : in boolean := false
                - IO_UART0_EN : in boolean := false
                - IO_UART1_EN : in boolean := false
                - IO_SPI_EN : in boolean := false
                - IO_TWI_EN : in boolean := false
                - IO_PWM_NUM_CH : in natural := 0
                - IO_WDT_EN : in boolean := false
                - IO_TRNG_EN : in boolean := false
                - IO_CFS_EN : in boolean := false
                - IO_CFS_CONFIG : in std_ulogic_vector(31 downto 0)
                - IO_CFS_IN_SIZE : in positive := 32
                - IO_CFS_OUT_SIZE : in positive := 32
                - IO_NEOLED_EN : in boolean := false
                - IO_NEOLED_TX_FIFO : in natural := 1
              Ports:
                - clk_i : in std_ulogic
                - rstn_i : in std_ulogic
                - jtag_trst_i : in std_ulogic := U
                - jtag_tck_i : in std_ulogic := U
                - jtag_tdi_i : in std_ulogic := U
                - jtag_tdo_o : out std_ulogic
                - jtag_tms_i : in std_ulogic := U
                - read_o : out std_logic
                - write_o : out std_logic
                - waitrequest_i : in std_logic := 0
                - byteenable_o : out std_logic_vector(3 downto 0)
                - address_o : out std_logic_vector(31 downto 0)
                - writedata_o : out std_logic_vector(31 downto 0)
                - readdata_i : in std_logic_vector(31 downto 0) := (others => 0)
                - fence_o : out std_ulogic
                - fencei_o : out std_ulogic
                - slink_tx_dat_o : out sdata_8x32_t
                - slink_tx_val_o : out std_ulogic_vector(7 downto 0)
                - slink_tx_rdy_i : in std_ulogic_vector(7 downto 0) := (others => L)
                - slink_rx_dat_i : in sdata_8x32_t := (others => (others => U))
                - slink_rx_val_i : in std_ulogic_vector(7 downto 0) := (others => L)
                - slink_rx_rdy_o : out std_ulogic_vector(7 downto 0)
                - gpio_o : out std_ulogic_vector(63 downto 0)
                - gpio_i : in std_ulogic_vector(63 downto 0) := (others => U)
                - uart0_txd_o : out std_ulogic
                - uart0_rxd_i : in std_ulogic := U
                - uart0_rts_o : out std_ulogic
                - uart0_cts_i : in std_ulogic := L
                - uart1_txd_o : out std_ulogic
                - uart1_rxd_i : in std_ulogic := U
                - uart1_rts_o : out std_ulogic
                - uart1_cts_i : in std_ulogic := L
                - spi_sck_o : out std_ulogic
                - spi_sdo_o : out std_ulogic
                - spi_sdi_i : in std_ulogic := U
                - spi_csn_o : out std_ulogic_vector(7 downto 0)
                - twi_sda_io : inout std_logic := U
                - twi_scl_io : inout std_logic := U
                - pwm_o : out std_ulogic_vector(IO_PWM_NUM_CH - 1 downto 0)
                - cfs_in_i : in std_ulogic_vector(IO_CFS_IN_SIZE - 1 downto 0) := (others => U)
                - cfs_out_o : out std_ulogic_vector(IO_CFS_OUT_SIZE - 1 downto 0)
                - neoled_o : out std_ulogic
                - mtime_i : in std_ulogic_vector(63 downto 0) := (others => U)
                - mtime_o : out std_ulogic_vector(63 downto 0)
                - xirq_i : in std_ulogic_vector(XIRQ_NUM_CH - 1 downto 0) := (others => L)
                - mtime_irq_i : in std_ulogic := L
                - msw_irq_i : in std_ulogic := L
                - mext_irq_i : in std_ulogic := L
            - Component: dmem_ram
              Generics:
              Ports:
                - address : in STD_LOGIC_VECTOR(10 downto 0)
                - byteena : in STD_LOGIC_VECTOR(3 downto 0) := (others => 1)
                - clock : in STD_LOGIC := 1
                - data : in STD_LOGIC_VECTOR(31 downto 0)
                - wren : in STD_LOGIC
                - q : out STD_LOGIC_VECTOR(31 downto 0)
            - signal con_gpio_o : std_ulogic_vector(63 downto 0)
            - signal read_o : std_logic
            - signal write_o : std_logic
            - signal waitrequest_i : std_logic
            - signal byteenable_o : std_logic_vector(3 downto 0)
            - signal address_o : std_logic_vector(31 downto 0)
            - signal writedata_o : std_logic_vector(31 downto 0)
            - signal readdata_i : std_logic_vector(31 downto 0)
            - signal read_wait_cnt : std_logic_vector(1 downto 0)
          Hierarchy:
            - neorv32_top_inst: component neorv32_top_avalonmm
            - my_dmem_ram: component dmem_ram
            - None: process(...)
          Statements:
            ...
            ...
            ...
            ...
      Packages:
      PackageBodies:
      Configurations:
      Contexts:

Teardown

XPASS test_AllVHDLSources[/home/runner/work/extended-tests/extended-tests/NEORV32/setups/quartus/de0-nano-test-setup-avalonmm-wrapper/dmem_ram.vhd] 0:00:00.245428

Started 2021-11-23 15:22:17
Ended 2021-11-23 15:22:17
Duration 0:00:00.245428
Markers
xfail
Fixtures file

Setup

Call

Captured stdout call
================================================================================
                         pyGHDL.dom - Test Application                          
================================================================================
Parsing file '/home/runner/work/extended-tests/extended-tests/NEORV32/setups/quartus/de0-nano-test-setup-avalonmm-wrapper/dmem_ram.vhd'
libghdl processing time:  206.401 us
DOM translation time:    1477.207 us

Design:
  Libraries:
    - Name: pretty
      Entities:
        - dmem_ram(SYN)
      Packages:
      Configurations:
      Contexts:
  Documents:
    - Path: '/home/runner/work/extended-tests/extended-tests/NEORV32/setups/quartus/de0-nano-test-setup-avalonmm-wrapper/dmem_ram.vhd':
      Entities:
        - Name: dmem_ram
          File: dmem_ram.vhd
          Position: 43:7
          Generics:
          Ports:
            - address : in STD_LOGIC_VECTOR(10 downto 0)
            - byteena : in STD_LOGIC_VECTOR(3 downto 0) := (others => 1)
            - clock : in STD_LOGIC := 1
            - data : in STD_LOGIC_VECTOR(31 downto 0)
            - wren : in STD_LOGIC
            - q : out STD_LOGIC_VECTOR(31 downto 0)
          Declared:
          Statements:
          Architecures:
          - SYN
      Architectures:
        - Name: SYN
          File: dmem_ram.vhd
          Position: 56:13
          Entity: dmem_ram
          Declared:
            - signal sub_wire0 : STD_LOGIC_VECTOR(31 downto 0)
          Hierarchy:
            - altsyncram_component: component altsyncram
          Statements:
            ...
            ...
      Packages:
      PackageBodies:
      Configurations:
      Contexts:

Teardown

XPASS test_AllVHDLSources[/home/runner/work/extended-tests/extended-tests/NEORV32/setups/radiant/UPduino_v3/neorv32_dmem.ice40up_spram.vhd] 0:00:00.257988

Started 2021-11-23 15:22:17
Ended 2021-11-23 15:22:17
Duration 0:00:00.257988
Markers
xfail
Fixtures file

Setup

Call

Captured stdout call
================================================================================
                         pyGHDL.dom - Test Application                          
================================================================================
Parsing file '/home/runner/work/extended-tests/extended-tests/NEORV32/setups/radiant/UPduino_v3/neorv32_dmem.ice40up_spram.vhd'
[NOT IMPLEMENTED] Concurrent (conditional) signal assignment (label: 'None') at line 87
[NOT IMPLEMENTED] Concurrent (conditional) signal assignment (label: 'None') at line 126
[NOT IMPLEMENTED] Concurrent (conditional) signal assignment (label: 'None') at line 130
[NOT IMPLEMENTED] Concurrent (conditional) signal assignment (label: 'None') at line 142
libghdl processing time:  297.701 us
DOM translation time:    4355.222 us

Design:
  Libraries:
    - Name: pretty
      Entities:
      Packages:
      Configurations:
      Contexts:
  Documents:
    - Path: '/home/runner/work/extended-tests/extended-tests/NEORV32/setups/radiant/UPduino_v3/neorv32_dmem.ice40up_spram.vhd':
      Entities:
      Architectures:
        - Name: neorv32_dmem_rtl
          File: neorv32_dmem.ice40up_spram.vhd
          Position: 48:13
          Entity: neorv32_dmem
          Declared:
            - constant spram_sleep_mode_en_c : boolean := false
            - constant hi_abb_c : natural := 31
            - constant lo_abb_c : natural := index_size_f(64 * 1024)
            - signal acc_en : std_ulogic
            - signal mem_cs : std_ulogic
            - signal rdata : std_ulogic_vector(31 downto 0)
            - signal rden : std_ulogic
            - signal spram_clk : std_logic
            - signal spram_addr : std_logic_vector(13 downto 0)
            - signal spram_di_lo : std_logic_vector(15 downto 0)
            - signal spram_di_hi : std_logic_vector(15 downto 0)
            - signal spram_do_lo : std_logic_vector(15 downto 0)
            - signal spram_do_hi : std_logic_vector(15 downto 0)
            - signal spram_be_lo : std_logic_vector(3 downto 0)
            - signal spram_be_hi : std_logic_vector(3 downto 0)
            - signal spram_we : std_logic
            - signal spram_pwr_n : std_logic
            - signal spram_cs : std_logic
          Hierarchy:
            - dmem_spram_lo_inst: component SP256K
            - dmem_spram_hi_inst: component SP256K
            - buffer_ff: process(...)
          Statements:
            ...
            ...
            ...
            ...
            ...
            ...
            ...
            ...
            ...
            ...
            ...
            ...
            ...
            ...
      Packages:
      PackageBodies:
      Configurations:
      Contexts:

Teardown

XPASS test_AllVHDLSources[/home/runner/work/extended-tests/extended-tests/NEORV32/setups/radiant/UPduino_v3/neorv32_imem.ice40up_spram.vhd] 0:00:00.248420

Started 2021-11-23 15:22:17
Ended 2021-11-23 15:22:17
Duration 0:00:00.248420
Markers
xfail
Fixtures file

Setup

Call

Captured stdout call
================================================================================
                         pyGHDL.dom - Test Application                          
================================================================================
Parsing file '/home/runner/work/extended-tests/extended-tests/NEORV32/setups/radiant/UPduino_v3/neorv32_imem.ice40up_spram.vhd'
[NOT IMPLEMENTED] Concurrent (conditional) signal assignment (label: 'None') at line 88
[NOT IMPLEMENTED] Concurrent (conditional) signal assignment (label: 'None') at line 127
[NOT IMPLEMENTED] Concurrent (conditional) signal assignment (label: 'None') at line 131
[NOT IMPLEMENTED] Concurrent (conditional) signal assignment (label: 'None') at line 143
libghdl processing time:  302.001 us
DOM translation time:    3883.920 us

Design:
  Libraries:
    - Name: pretty
      Entities:
      Packages:
      Configurations:
      Contexts:
  Documents:
    - Path: '/home/runner/work/extended-tests/extended-tests/NEORV32/setups/radiant/UPduino_v3/neorv32_imem.ice40up_spram.vhd':
      Entities:
      Architectures:
        - Name: neorv32_imem_rtl
          File: neorv32_imem.ice40up_spram.vhd
          Position: 48:13
          Entity: neorv32_imem
          Declared:
            - constant spram_sleep_mode_en_c : boolean := false
            - constant hi_abb_c : natural := 31
            - constant lo_abb_c : natural := index_size_f(64 * 1024)
            - signal acc_en : std_ulogic
            - signal mem_cs : std_ulogic
            - signal rdata : std_ulogic_vector(31 downto 0)
            - signal rden : std_ulogic
            - signal spram_clk : std_logic
            - signal spram_addr : std_logic_vector(13 downto 0)
            - signal spram_di_lo : std_logic_vector(15 downto 0)
            - signal spram_di_hi : std_logic_vector(15 downto 0)
            - signal spram_do_lo : std_logic_vector(15 downto 0)
            - signal spram_do_hi : std_logic_vector(15 downto 0)
            - signal spram_be_lo : std_logic_vector(3 downto 0)
            - signal spram_be_hi : std_logic_vector(3 downto 0)
            - signal spram_we : std_logic
            - signal spram_pwr_n : std_logic
            - signal spram_cs : std_logic
          Hierarchy:
            - imem_spram_lo_inst: component SP256K
            - imem_spram_hi_inst: component SP256K
            - buffer_ff: process(...)
          Statements:
            ...
            ...
            ...
            ...
            ...
            ...
            ...
            ...
            ...
            ...
            ...
            ...
            ...
            ...
            ...
      Packages:
      PackageBodies:
      Configurations:
      Contexts:

Teardown

XPASS test_AllVHDLSources[/home/runner/work/extended-tests/extended-tests/NEORV32/setups/radiant/UPduino_v3/neorv32_upduino_v3_top.vhd] 0:00:00.256312

Started 2021-11-23 15:22:17
Ended 2021-11-23 15:22:18
Duration 0:00:00.256312
Markers
xfail
Fixtures file

Setup

Call

Captured stdout call
================================================================================
                         pyGHDL.dom - Test Application                          
================================================================================
Parsing file '/home/runner/work/extended-tests/extended-tests/NEORV32/setups/radiant/UPduino_v3/neorv32_upduino_v3_top.vhd'
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Concurrent (conditional) signal assignment (label: 'None') at line 220
libghdl processing time:  421.602 us
DOM translation time:    5191.026 us

Design:
  Libraries:
    - Name: pretty
      Entities:
        - neorv32_upduino_v3_top(neorv32_upduino_v3_top_rtl)
      Packages:
      Configurations:
      Contexts:
  Documents:
    - Path: '/home/runner/work/extended-tests/extended-tests/NEORV32/setups/radiant/UPduino_v3/neorv32_upduino_v3_top.vhd':
      Entities:
        - Name: neorv32_upduino_v3_top
          File: neorv32_upduino_v3_top.vhd
          Position: 48:7
          Generics:
          Ports:
            - uart_txd_o : out std_ulogic
            - uart_rxd_i : in std_ulogic
            - flash_sck_o : out std_ulogic
            - flash_sdo_o : out std_ulogic
            - flash_sdi_i : in std_ulogic
            - flash_csn_o : out std_ulogic
            - spi_sck_o : out std_ulogic
            - spi_sdo_o : out std_ulogic
            - spi_sdi_i : in std_ulogic
            - spi_csn_o : out std_ulogic
            - twi_sda_io : inout std_logic
            - twi_scl_io : inout std_logic
            - gpio_i : in std_ulogic_vector(3 downto 0)
            - gpio_o : out std_ulogic_vector(3 downto 0)
            - pwm_o : out std_ulogic_vector(2 downto 0)
          Declared:
          Statements:
          Architecures:
          - neorv32_upduino_v3_top_rtl
      Architectures:
        - Name: neorv32_upduino_v3_top_rtl
          File: neorv32_upduino_v3_top.vhd
          Position: 74:13
          Entity: neorv32_upduino_v3_top
          Declared:
            - constant f_clock_c : natural := 24000000
            - signal hf_osc_clk : std_logic
            - Component: system_pll
              Generics:
              Ports:
                - ref_clk_i : in std_logic
                - rst_n_i : in std_logic
                - lock_o : out std_logic
                - outcore_o : out std_logic
                - outglobal_o : out std_logic
            - signal pll_rstn : std_logic
            - signal pll_clk : std_logic
            - signal cpu_clk : std_ulogic
            - signal cpu_rstn : std_ulogic
            - signal con_pwm : std_ulogic_vector(2 downto 0)
            - signal con_spi_sck : std_ulogic
            - signal con_spi_sdi : std_ulogic
            - signal con_spi_sdo : std_ulogic
            - signal con_spi_csn : std_ulogic_vector(7 downto 0)
            - signal con_gpio_i : std_ulogic_vector(63 downto 0)
            - signal con_gpio_o : std_ulogic_vector(63 downto 0)
            - signal pwm_drive : std_logic_vector(2 downto 0)
            - signal pwm_driven : std_ulogic_vector(2 downto 0)
          Hierarchy:
            - hsosc_inst: component HSOSC
            - system_pll_inst: component system_pll
            - neorv32_inst: component neorv32_top
            - rgb_inst: component RGB
          Statements:
            ...
            ...
            ...
            ...
            ...
            ...
            ...
            ...
            ...
            ...
            ...
            ...
            ...
            ...
            ...
            ...
            ...
            ...
      Packages:
      PackageBodies:
      Configurations:
      Contexts:

Teardown

XPASS test_AllVHDLSources[/home/runner/work/extended-tests/extended-tests/NEORV32/rtl/processor_templates/neorv32_ProcessorTop_UP5KDemo.vhd] 0:00:00.260562

Started 2021-11-23 15:22:17
Ended 2021-11-23 15:22:18
Duration 0:00:00.260562
Markers
xfail
Fixtures file

Setup

Call

Captured stdout call
================================================================================
                         pyGHDL.dom - Test Application                          
================================================================================
Parsing file '/home/runner/work/extended-tests/extended-tests/NEORV32/rtl/processor_templates/neorv32_ProcessorTop_UP5KDemo.vhd'
[NOT IMPLEMENTED] Concurrent (conditional) signal assignment (label: 'None') at line 155
[NOT IMPLEMENTED] Bit String Literal not supported yet
libghdl processing time:  481.902 us
DOM translation time:    6376.532 us

Design:
  Libraries:
    - Name: pretty
      Entities:
        - neorv32_ProcessorTop_UP5KDemo(neorv32_ProcessorTop_UP5KDemo_rtl)
      Packages:
      Configurations:
      Contexts:
  Documents:
    - Path: '/home/runner/work/extended-tests/extended-tests/NEORV32/rtl/processor_templates/neorv32_ProcessorTop_UP5KDemo.vhd':
      Entities:
        - Name: neorv32_ProcessorTop_UP5KDemo
          File: neorv32_ProcessorTop_UP5KDemo.vhd
          Position: 41:7
          Generics:
            - CLOCK_FREQUENCY : in natural := 0
            - HW_THREAD_ID : in natural := 0
            - ON_CHIP_DEBUGGER_EN : in boolean := false
            - CPU_EXTENSION_RISCV_A : in boolean := true
            - CPU_EXTENSION_RISCV_C : in boolean := true
            - CPU_EXTENSION_RISCV_E : in boolean := false
            - CPU_EXTENSION_RISCV_M : in boolean := true
            - CPU_EXTENSION_RISCV_U : in boolean := false
            - CPU_EXTENSION_RISCV_Zfinx : in boolean := false
            - CPU_EXTENSION_RISCV_Zicsr : in boolean := true
            - CPU_EXTENSION_RISCV_Zifencei : in boolean := false
            - FAST_MUL_EN : in boolean := false
            - FAST_SHIFT_EN : in boolean := false
            - CPU_CNT_WIDTH : in natural := 34
            - PMP_NUM_REGIONS : in natural := 0
            - PMP_MIN_GRANULARITY : in natural := 64 * 1024
            - HPM_NUM_CNTS : in natural := 0
            - HPM_CNT_WIDTH : in natural := 40
            - MEM_INT_IMEM_EN : in boolean := true
            - MEM_INT_IMEM_SIZE : in natural := 64 * 1024
            - MEM_INT_DMEM_EN : in boolean := true
            - MEM_INT_DMEM_SIZE : in natural := 64 * 1024
            - ICACHE_EN : in boolean := false
            - ICACHE_NUM_BLOCKS : in natural := 4
            - ICACHE_BLOCK_SIZE : in natural := 64
            - ICACHE_ASSOCIATIVITY : in natural := 1
            - IO_GPIO_EN : in boolean := true
            - IO_MTIME_EN : in boolean := true
            - IO_UART0_EN : in boolean := true
            - IO_SPI_EN : in boolean := true
            - IO_TWI_EN : in boolean := true
            - IO_PWM_NUM_CH : in natural := 3
            - IO_WDT_EN : in boolean := true
          Ports:
            - clk_i : in std_logic
            - rstn_i : in std_logic
            - gpio_i : in std_ulogic_vector(3 downto 0)
            - gpio_o : out std_ulogic_vector(3 downto 0)
            - uart_txd_o : out std_ulogic
            - uart_rxd_i : in std_ulogic := 0
            - uart_rts_o : out std_ulogic
            - uart_cts_i : in std_ulogic := 0
            - flash_sck_o : out std_ulogic
            - flash_sdo_o : out std_ulogic
            - flash_sdi_i : in std_ulogic
            - flash_csn_o : out std_ulogic
            - spi_sck_o : out std_ulogic
            - spi_sdo_o : out std_ulogic
            - spi_sdi_i : in std_ulogic
            - spi_csn_o : out std_ulogic
            - twi_sda_io : inout std_logic
            - twi_scl_io : inout std_logic
            - pwm_o : out std_ulogic_vector(IO_PWM_NUM_CH - 1 downto 0)
          Declared:
          Statements:
          Architecures:
          - neorv32_ProcessorTop_UP5KDemo_rtl
      Architectures:
        - Name: neorv32_ProcessorTop_UP5KDemo_rtl
          File: neorv32_ProcessorTop_UP5KDemo.vhd
          Position: 130:13
          Entity: neorv32_ProcessorTop_UP5KDemo
          Declared:
            - signal con_gpio_o : std_ulogic_vector(63 downto 0)
            - signal con_gpio_i : std_ulogic_vector(63 downto 0)
            - signal con_spi_sck : std_ulogic
            - signal con_spi_sdi : std_ulogic
            - signal con_spi_sdo : std_ulogic
            - signal con_spi_csn : std_ulogic_vector(7 downto 0)
          Hierarchy:
            - neorv32_inst: entity neorv32.neorv32_top
          Statements:
            ...
            ...
            ...
            ...
            ...
            ...
            ...
            ...
            ...
            ...
      Packages:
      PackageBodies:
      Configurations:
      Contexts:

Teardown

XPASS test_AllVHDLSources[/home/runner/work/extended-tests/extended-tests/NEORV32/rtl/processor_templates/neorv32_ProcessorTop_Minimal.vhd] 0:00:00.249848

Started 2021-11-23 15:22:18
Ended 2021-11-23 15:22:18
Duration 0:00:00.249848
Markers
xfail
Fixtures file

Setup

Call

Captured stdout call
================================================================================
                         pyGHDL.dom - Test Application                          
================================================================================
Parsing file '/home/runner/work/extended-tests/extended-tests/NEORV32/rtl/processor_templates/neorv32_ProcessorTop_Minimal.vhd'
[NOT IMPLEMENTED] Bit String Literal not supported yet
libghdl processing time:  508.003 us
DOM translation time:    4191.921 us

Design:
  Libraries:
    - Name: pretty
      Entities:
        - neorv32_ProcessorTop_Minimal(neorv32_ProcessorTop_Minimal_rtl)
      Packages:
      Configurations:
      Contexts:
  Documents:
    - Path: '/home/runner/work/extended-tests/extended-tests/NEORV32/rtl/processor_templates/neorv32_ProcessorTop_Minimal.vhd':
      Entities:
        - Name: neorv32_ProcessorTop_Minimal
          File: neorv32_ProcessorTop_Minimal.vhd
          Position: 41:7
          Generics:
            - CLOCK_FREQUENCY : in natural := 0
            - HW_THREAD_ID : in natural := 0
            - CPU_EXTENSION_RISCV_A : in boolean := false
            - CPU_EXTENSION_RISCV_C : in boolean := false
            - CPU_EXTENSION_RISCV_E : in boolean := false
            - CPU_EXTENSION_RISCV_M : in boolean := false
            - CPU_EXTENSION_RISCV_U : in boolean := false
            - CPU_EXTENSION_RISCV_Zfinx : in boolean := false
            - CPU_EXTENSION_RISCV_Zicsr : in boolean := true
            - CPU_EXTENSION_RISCV_Zifencei : in boolean := false
            - FAST_MUL_EN : in boolean := false
            - FAST_SHIFT_EN : in boolean := false
            - CPU_CNT_WIDTH : in natural := 34
            - PMP_NUM_REGIONS : in natural := 0
            - PMP_MIN_GRANULARITY : in natural := 8 * 1024
            - HPM_NUM_CNTS : in natural := 0
            - HPM_CNT_WIDTH : in natural := 40
            - MEM_INT_IMEM_EN : in boolean := true
            - MEM_INT_IMEM_SIZE : in natural := 8 * 1024
            - MEM_INT_DMEM_EN : in boolean := true
            - MEM_INT_DMEM_SIZE : in natural := 64 * 1024
            - ICACHE_EN : in boolean := false
            - ICACHE_NUM_BLOCKS : in natural := 4
            - ICACHE_BLOCK_SIZE : in natural := 64
            - ICACHE_ASSOCIATIVITY : in natural := 1
            - IO_MTIME_EN : in boolean := false
            - IO_PWM_NUM_CH : in natural := 3
            - IO_WDT_EN : in boolean := false
          Ports:
            - clk_i : in std_logic
            - rstn_i : in std_logic
            - pwm_o : out std_ulogic_vector(IO_PWM_NUM_CH - 1 downto 0)
          Declared:
          Statements:
          Architecures:
          - neorv32_ProcessorTop_Minimal_rtl
      Architectures:
        - Name: neorv32_ProcessorTop_Minimal_rtl
          File: neorv32_ProcessorTop_Minimal.vhd
          Position: 97:13
          Entity: neorv32_ProcessorTop_Minimal
          Declared:
          Hierarchy:
            - neorv32_inst: entity neorv32.neorv32_top
          Statements:
            ...
      Packages:
      PackageBodies:
      Configurations:
      Contexts:

Teardown

XPASS test_AllVHDLSources[/home/runner/work/extended-tests/extended-tests/NEORV32/rtl/processor_templates/neorv32_ProcessorTop_MinimalBoot.vhd] 0:00:00.251612

Started 2021-11-23 15:22:18
Ended 2021-11-23 15:22:18
Duration 0:00:00.251612
Markers
xfail
Fixtures file

Setup

Call

Captured stdout call
================================================================================
                         pyGHDL.dom - Test Application                          
================================================================================
Parsing file '/home/runner/work/extended-tests/extended-tests/NEORV32/rtl/processor_templates/neorv32_ProcessorTop_MinimalBoot.vhd'
[NOT IMPLEMENTED] Bit String Literal not supported yet
libghdl processing time:  449.002 us
DOM translation time:    4171.521 us

Design:
  Libraries:
    - Name: pretty
      Entities:
        - neorv32_ProcessorTop_MinimalBoot(neorv32_ProcessorTop_MinimalBoot_rtl)
      Packages:
      Configurations:
      Contexts:
  Documents:
    - Path: '/home/runner/work/extended-tests/extended-tests/NEORV32/rtl/processor_templates/neorv32_ProcessorTop_MinimalBoot.vhd':
      Entities:
        - Name: neorv32_ProcessorTop_MinimalBoot
          File: neorv32_ProcessorTop_MinimalBoot.vhd
          Position: 41:7
          Generics:
            - CLOCK_FREQUENCY : in natural := 0
            - INT_BOOTLOADER_EN : in boolean := true
            - HW_THREAD_ID : in natural := 0
            - CPU_EXTENSION_RISCV_A : in boolean := true
            - CPU_EXTENSION_RISCV_C : in boolean := true
            - CPU_EXTENSION_RISCV_E : in boolean := false
            - CPU_EXTENSION_RISCV_M : in boolean := true
            - CPU_EXTENSION_RISCV_U : in boolean := false
            - CPU_EXTENSION_RISCV_Zfinx : in boolean := false
            - CPU_EXTENSION_RISCV_Zicsr : in boolean := true
            - CPU_EXTENSION_RISCV_Zifencei : in boolean := false
            - FAST_MUL_EN : in boolean := false
            - FAST_SHIFT_EN : in boolean := false
            - CPU_CNT_WIDTH : in natural := 34
            - PMP_NUM_REGIONS : in natural := 0
            - PMP_MIN_GRANULARITY : in natural := 64 * 1024
            - HPM_NUM_CNTS : in natural := 0
            - HPM_CNT_WIDTH : in natural := 40
            - MEM_INT_IMEM_EN : in boolean := true
            - MEM_INT_IMEM_SIZE : in natural := 64 * 1024
            - MEM_INT_DMEM_EN : in boolean := true
            - MEM_INT_DMEM_SIZE : in natural := 64 * 1024
            - ICACHE_EN : in boolean := false
            - ICACHE_NUM_BLOCKS : in natural := 4
            - ICACHE_BLOCK_SIZE : in natural := 64
            - ICACHE_ASSOCIATIVITY : in natural := 1
            - IO_GPIO_EN : in boolean := true
            - IO_MTIME_EN : in boolean := true
            - IO_UART0_EN : in boolean := true
            - IO_PWM_NUM_CH : in natural := 3
            - IO_WDT_EN : in boolean := true
          Ports:
            - clk_i : in std_logic
            - rstn_i : in std_logic
            - gpio_o : out std_ulogic_vector(3 downto 0)
            - uart_txd_o : out std_ulogic
            - uart_rxd_i : in std_ulogic := 0
            - uart_rts_o : out std_ulogic
            - uart_cts_i : in std_ulogic := 0
            - pwm_o : out std_ulogic_vector(IO_PWM_NUM_CH - 1 downto 0)
          Declared:
          Statements:
          Architecures:
          - neorv32_ProcessorTop_MinimalBoot_rtl
      Architectures:
        - Name: neorv32_ProcessorTop_MinimalBoot_rtl
          File: neorv32_ProcessorTop_MinimalBoot.vhd
          Position: 109:13
          Entity: neorv32_ProcessorTop_MinimalBoot
          Declared:
            - signal con_gpio_o : std_ulogic_vector(63 downto 0)
          Hierarchy:
            - neorv32_inst: entity neorv32.neorv32_top
          Statements:
            ...
            ...
      Packages:
      PackageBodies:
      Configurations:
      Contexts:

Teardown

XPASS test_AllVHDLSources[/home/runner/work/extended-tests/extended-tests/NEORV32/rtl/system_integration/neorv32_SystemTop_axi4lite.vhd] 0:00:00.269515

Started 2021-11-23 15:22:18
Ended 2021-11-23 15:22:18
Duration 0:00:00.269515
Markers
xfail
Fixtures file

Setup

Call

Captured stdout call
================================================================================
                         pyGHDL.dom - Test Application                          
================================================================================
Parsing file '/home/runner/work/extended-tests/extended-tests/NEORV32/rtl/system_integration/neorv32_SystemTop_axi4lite.vhd'
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Concurrent (conditional) signal assignment (label: 'None') at line 505
[NOT IMPLEMENTED] Concurrent (conditional) signal assignment (label: 'None') at line 524
libghdl processing time:  1237.506 us
DOM translation time:    15978.080 us

Design:
  Libraries:
    - Name: pretty
      Entities:
        - neorv32_SystemTop_axi4lite(neorv32_SystemTop_axi4lite_rtl)
      Packages:
      Configurations:
      Contexts:
  Documents:
    - Path: '/home/runner/work/extended-tests/extended-tests/NEORV32/rtl/system_integration/neorv32_SystemTop_axi4lite.vhd':
      Entities:
        - Name: neorv32_SystemTop_axi4lite
          File: neorv32_SystemTop_axi4lite.vhd
          Position: 45:7
          Generics:
            - CLOCK_FREQUENCY : in natural := 0
            - INT_BOOTLOADER_EN : in boolean := true
            - HW_THREAD_ID : in natural := 0
            - ON_CHIP_DEBUGGER_EN : in boolean := false
            - CPU_EXTENSION_RISCV_A : in boolean := false
            - CPU_EXTENSION_RISCV_B : in boolean := false
            - CPU_EXTENSION_RISCV_C : in boolean := false
            - CPU_EXTENSION_RISCV_E : in boolean := false
            - CPU_EXTENSION_RISCV_M : in boolean := false
            - CPU_EXTENSION_RISCV_U : in boolean := false
            - CPU_EXTENSION_RISCV_Zfinx : in boolean := false
            - CPU_EXTENSION_RISCV_Zicsr : in boolean := true
            - CPU_EXTENSION_RISCV_Zicntr : in boolean := true
            - CPU_EXTENSION_RISCV_Zihpm : in boolean := false
            - CPU_EXTENSION_RISCV_Zifencei : in boolean := false
            - FAST_MUL_EN : in boolean := false
            - FAST_SHIFT_EN : in boolean := false
            - CPU_CNT_WIDTH : in natural := 64
            - PMP_NUM_REGIONS : in natural := 0
            - PMP_MIN_GRANULARITY : in natural := 64 * 1024
            - HPM_NUM_CNTS : in natural := 0
            - HPM_CNT_WIDTH : in natural := 40
            - MEM_INT_IMEM_EN : in boolean := true
            - MEM_INT_IMEM_SIZE : in natural := 16 * 1024
            - MEM_INT_DMEM_EN : in boolean := true
            - MEM_INT_DMEM_SIZE : in natural := 8 * 1024
            - ICACHE_EN : in boolean := false
            - ICACHE_NUM_BLOCKS : in natural := 4
            - ICACHE_BLOCK_SIZE : in natural := 64
            - ICACHE_ASSOCIATIVITY : in natural := 1
            - XIRQ_NUM_CH : in natural := 0
            - XIRQ_TRIGGER_TYPE : in std_logic_vector(31 downto 0)
            - XIRQ_TRIGGER_POLARITY : in std_logic_vector(31 downto 0)
            - IO_GPIO_EN : in boolean := true
            - IO_MTIME_EN : in boolean := true
            - IO_UART0_EN : in boolean := true
            - IO_UART0_RX_FIFO : in natural := 1
            - IO_UART0_TX_FIFO : in natural := 1
            - IO_UART1_EN : in boolean := true
            - IO_UART1_RX_FIFO : in natural := 1
            - IO_UART1_TX_FIFO : in natural := 1
            - IO_SPI_EN : in boolean := true
            - IO_TWI_EN : in boolean := true
            - IO_PWM_NUM_CH : in natural := 4
            - IO_WDT_EN : in boolean := true
            - IO_TRNG_EN : in boolean := false
            - IO_CFS_EN : in boolean := false
            - IO_CFS_CONFIG : in std_logic_vector(31 downto 0)
            - IO_CFS_IN_SIZE : in positive := 32
            - IO_CFS_OUT_SIZE : in positive := 32
            - IO_NEOLED_EN : in boolean := true
            - IO_NEOLED_TX_FIFO : in natural := 1
            - IO_GPTMR_EN : in boolean := false
          Ports:
            - m_axi_aclk : in std_logic
            - m_axi_aresetn : in std_logic
            - m_axi_awaddr : out std_logic_vector(31 downto 0)
            - m_axi_awprot : out std_logic_vector(2 downto 0)
            - m_axi_awvalid : out std_logic
            - m_axi_awready : in std_logic
            - m_axi_wdata : out std_logic_vector(31 downto 0)
            - m_axi_wstrb : out std_logic_vector(3 downto 0)
            - m_axi_wvalid : out std_logic
            - m_axi_wready : in std_logic
            - m_axi_araddr : out std_logic_vector(31 downto 0)
            - m_axi_arprot : out std_logic_vector(2 downto 0)
            - m_axi_arvalid : out std_logic
            - m_axi_arready : in std_logic
            - m_axi_rdata : in std_logic_vector(31 downto 0)
            - m_axi_rresp : in std_logic_vector(1 downto 0)
            - m_axi_rvalid : in std_logic
            - m_axi_rready : out std_logic
            - m_axi_bresp : in std_logic_vector(1 downto 0)
            - m_axi_bvalid : in std_logic
            - m_axi_bready : out std_logic
            - jtag_trst_i : in std_logic := 0
            - jtag_tck_i : in std_logic := 0
            - jtag_tdi_i : in std_logic := 0
            - jtag_tdo_o : out std_logic
            - jtag_tms_i : in std_logic := 0
            - gpio_o : out std_logic_vector(63 downto 0)
            - gpio_i : in std_logic_vector(63 downto 0) := (others => 0)
            - uart0_txd_o : out std_logic
            - uart0_rxd_i : in std_logic := 0
            - uart0_rts_o : out std_logic
            - uart0_cts_i : in std_logic := 0
            - uart1_txd_o : out std_logic
            - uart1_rxd_i : in std_logic := 0
            - uart1_rts_o : out std_logic
            - uart1_cts_i : in std_logic := 0
            - spi_sck_o : out std_logic
            - spi_sdo_o : out std_logic
            - spi_sdi_i : in std_logic := 0
            - spi_csn_o : out std_logic_vector(7 downto 0)
            - twi_sda_io : inout std_logic
            - twi_scl_io : inout std_logic
            - pwm_o : out std_logic_vector(IO_PWM_NUM_CH - 1 downto 0)
            - cfs_in_i : in std_logic_vector(IO_CFS_IN_SIZE - 1 downto 0)
            - cfs_out_o : out std_logic_vector(IO_CFS_OUT_SIZE - 1 downto 0)
            - neoled_o : out std_logic
            - xirq_i : in std_logic_vector(XIRQ_NUM_CH - 1 downto 0) := (others => 0)
            - msw_irq_i : in std_logic := 0
            - mext_irq_i : in std_logic := 0
          Declared:
          Statements:
          Architecures:
          - neorv32_SystemTop_axi4lite_rtl
      Architectures:
        - Name: neorv32_SystemTop_axi4lite_rtl
          File: neorv32_SystemTop_axi4lite.vhd
          Position: 193:13
          Entity: neorv32_SystemTop_axi4lite
          Declared:
            - constant IO_CFS_CONFIG_INT : std_ulogic_vector(31 downto 0) := std_ulogic_vector(IO_CFS_CONFIG)
            - constant XIRQ_TRIGGER_TYPE_INT : std_ulogic_vector(31 downto 0) := std_ulogic_vector(XIRQ_TRIGGER_TYPE)
            - constant XIRQ_TRIGGER_POLARITY_INT : std_ulogic_vector(31 downto 0) := std_ulogic_vector(XIRQ_TRIGGER_POLARITY)
            - signal clk_i_int : std_ulogic
            - signal rstn_i_int : std_ulogic
            - signal jtag_trst_i_int : std_ulogic
            - signal jtag_tck_i_int : std_ulogic
            - signal jtag_tdi_i_int : std_ulogic
            - signal jtag_tdo_o_int : std_ulogic
            - signal jtag_tms_i_int : std_ulogic
            - signal gpio_o_int : std_ulogic_vector(63 downto 0)
            - signal gpio_i_int : std_ulogic_vector(63 downto 0)
            - signal uart0_txd_o_int : std_ulogic
            - signal uart0_rxd_i_int : std_ulogic
            - signal uart0_rts_o_int : std_ulogic
            - signal uart0_cts_i_int : std_ulogic
            - signal uart1_txd_o_int : std_ulogic
            - signal uart1_rxd_i_int : std_ulogic
            - signal uart1_rts_o_int : std_ulogic
            - signal uart1_cts_i_int : std_ulogic
            - signal spi_sck_o_int : std_ulogic
            - signal spi_sdo_o_int : std_ulogic
            - signal spi_sdi_i_int : std_ulogic
            - signal spi_csn_o_int : std_ulogic_vector(7 downto 0)
            - signal pwm_o_int : std_ulogic_vector(IO_PWM_NUM_CH - 1 downto 0)
            - signal cfs_in_i_int : std_ulogic_vector(IO_CFS_IN_SIZE - 1 downto 0)
            - signal cfs_out_o_int : std_ulogic_vector(IO_CFS_OUT_SIZE - 1 downto 0)
            - signal neoled_o_int : std_ulogic
            - signal xirq_i_int : std_ulogic_vector(XIRQ_NUM_CH - 1 downto 0)
            - signal msw_irq_i_int : std_ulogic
            - signal mext_irq_i_int : std_ulogic
            - type wb_bus_t is record ..... end record
            - signal wb_core : wb_bus_t
            - type ctrl_t is record ..... end record
            - signal ctrl : ctrl_t
            - signal ack_read, ack_write : std_ulogic
            - signal err_read, err_write : std_ulogic
          Hierarchy:
            - neorv32_top_inst: component neorv32_top
            - axi_access_arbiter: process(...)
          Statements:
            ...
            ...
            ...
            ...
            ...
            ...
            ...
            ...
            ...
            ...
            ...
            ...
            ...
            ...
            ...
            ...
            ...
            ...
            ...
            ...
            ...
            ...
            ...
            ...
            ...
            ...
            ...
            ...
            ...
            ...
            ...
            ...
            ...
            ...
            ...
            ...
            ...
            ...
            ...
            ...
            ...
            ...
            ...
            ...
            ...
            ...
            ...
            ...
            ...
            ...
            ...
      Packages:
      PackageBodies:
      Configurations:
      Contexts:

Teardown

XPASS test_AllVHDLSources[/home/runner/work/extended-tests/extended-tests/NEORV32/rtl/system_integration/neorv32_SystemTop_AvalonMM.vhd] 0:00:00.257251

Started 2021-11-23 15:22:18
Ended 2021-11-23 15:22:18
Duration 0:00:00.257251
Markers
xfail
Fixtures file

Setup

Call

Captured stdout call
================================================================================
                         pyGHDL.dom - Test Application                          
================================================================================
Parsing file '/home/runner/work/extended-tests/extended-tests/NEORV32/rtl/system_integration/neorv32_SystemTop_AvalonMM.vhd'
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Concurrent (conditional) signal assignment (label: 'None') at line 413
[NOT IMPLEMENTED] Concurrent (conditional) signal assignment (label: 'None') at line 414
libghdl processing time:  779.704 us
DOM translation time:    9328.346 us

Design:
  Libraries:
    - Name: pretty
      Entities:
        - neorv32_top_avalonmm(neorv32_top_avalonmm_rtl)
      Packages:
      Configurations:
      Contexts:
  Documents:
    - Path: '/home/runner/work/extended-tests/extended-tests/NEORV32/rtl/system_integration/neorv32_SystemTop_AvalonMM.vhd':
      Entities:
        - Name: neorv32_top_avalonmm
          File: neorv32_SystemTop_AvalonMM.vhd
          Position: 45:7
          Generics:
            - CLOCK_FREQUENCY : in natural
            - HW_THREAD_ID : in natural := 0
            - INT_BOOTLOADER_EN : in boolean := false
            - ON_CHIP_DEBUGGER_EN : in boolean := false
            - CPU_EXTENSION_RISCV_A : in boolean := false
            - CPU_EXTENSION_RISCV_B : in boolean := false
            - CPU_EXTENSION_RISCV_C : in boolean := false
            - CPU_EXTENSION_RISCV_E : in boolean := false
            - CPU_EXTENSION_RISCV_M : in boolean := false
            - CPU_EXTENSION_RISCV_U : in boolean := false
            - CPU_EXTENSION_RISCV_Zfinx : in boolean := false
            - CPU_EXTENSION_RISCV_Zicsr : in boolean := true
            - CPU_EXTENSION_RISCV_Zicntr : in boolean := true
            - CPU_EXTENSION_RISCV_Zihpm : in boolean := false
            - CPU_EXTENSION_RISCV_Zifencei : in boolean := false
            - CPU_EXTENSION_RISCV_Zmmul : in boolean := false
            - FAST_MUL_EN : in boolean := false
            - FAST_SHIFT_EN : in boolean := false
            - CPU_CNT_WIDTH : in natural := 64
            - CPU_IPB_ENTRIES : in natural := 2
            - PMP_NUM_REGIONS : in natural := 0
            - PMP_MIN_GRANULARITY : in natural := 64 * 1024
            - HPM_NUM_CNTS : in natural := 0
            - HPM_CNT_WIDTH : in natural := 40
            - MEM_INT_IMEM_EN : in boolean := false
            - MEM_INT_IMEM_SIZE : in natural := 16 * 1024
            - MEM_INT_DMEM_EN : in boolean := false
            - MEM_INT_DMEM_SIZE : in natural := 8 * 1024
            - ICACHE_EN : in boolean := false
            - ICACHE_NUM_BLOCKS : in natural := 4
            - ICACHE_BLOCK_SIZE : in natural := 64
            - ICACHE_ASSOCIATIVITY : in natural := 1
            - SLINK_NUM_TX : in natural := 0
            - SLINK_NUM_RX : in natural := 0
            - SLINK_TX_FIFO : in natural := 1
            - SLINK_RX_FIFO : in natural := 1
            - XIRQ_NUM_CH : in natural := 0
            - XIRQ_TRIGGER_TYPE : in std_ulogic_vector(31 downto 0)
            - XIRQ_TRIGGER_POLARITY : in std_ulogic_vector(31 downto 0)
            - IO_GPIO_EN : in boolean := false
            - IO_MTIME_EN : in boolean := false
            - IO_UART0_EN : in boolean := false
            - IO_UART0_RX_FIFO : in natural := 1
            - IO_UART0_TX_FIFO : in natural := 1
            - IO_UART1_EN : in boolean := false
            - IO_UART1_RX_FIFO : in natural := 1
            - IO_UART1_TX_FIFO : in natural := 1
            - IO_SPI_EN : in boolean := false
            - IO_TWI_EN : in boolean := false
            - IO_PWM_NUM_CH : in natural := 0
            - IO_WDT_EN : in boolean := false
            - IO_TRNG_EN : in boolean := false
            - IO_CFS_EN : in boolean := false
            - IO_CFS_CONFIG : in std_ulogic_vector(31 downto 0)
            - IO_CFS_IN_SIZE : in positive := 32
            - IO_CFS_OUT_SIZE : in positive := 32
            - IO_NEOLED_EN : in boolean := false
            - IO_NEOLED_TX_FIFO : in natural := 1
            - IO_GPTMR_EN : in boolean := false
          Ports:
            - clk_i : in std_ulogic
            - rstn_i : in std_ulogic
            - jtag_trst_i : in std_ulogic := U
            - jtag_tck_i : in std_ulogic := U
            - jtag_tdi_i : in std_ulogic := U
            - jtag_tdo_o : out std_ulogic
            - jtag_tms_i : in std_ulogic := U
            - read_o : out std_logic
            - write_o : out std_logic
            - waitrequest_i : in std_logic := 0
            - byteenable_o : out std_logic_vector(3 downto 0)
            - address_o : out std_logic_vector(31 downto 0)
            - writedata_o : out std_logic_vector(31 downto 0)
            - readdata_i : in std_logic_vector(31 downto 0) := (others => 0)
            - fence_o : out std_ulogic
            - fencei_o : out std_ulogic
            - slink_tx_dat_o : out sdata_8x32_t
            - slink_tx_val_o : out std_ulogic_vector(7 downto 0)
            - slink_tx_rdy_i : in std_ulogic_vector(7 downto 0) := (others => L)
            - slink_rx_dat_i : in sdata_8x32_t := (others => (others => U))
            - slink_rx_val_i : in std_ulogic_vector(7 downto 0) := (others => L)
            - slink_rx_rdy_o : out std_ulogic_vector(7 downto 0)
            - gpio_o : out std_ulogic_vector(63 downto 0)
            - gpio_i : in std_ulogic_vector(63 downto 0) := (others => U)
            - uart0_txd_o : out std_ulogic
            - uart0_rxd_i : in std_ulogic := U
            - uart0_rts_o : out std_ulogic
            - uart0_cts_i : in std_ulogic := L
            - uart1_txd_o : out std_ulogic
            - uart1_rxd_i : in std_ulogic := U
            - uart1_rts_o : out std_ulogic
            - uart1_cts_i : in std_ulogic := L
            - spi_sck_o : out std_ulogic
            - spi_sdo_o : out std_ulogic
            - spi_sdi_i : in std_ulogic := U
            - spi_csn_o : out std_ulogic_vector(7 downto 0)
            - twi_sda_io : inout std_logic := U
            - twi_scl_io : inout std_logic := U
            - pwm_o : out std_ulogic_vector(IO_PWM_NUM_CH - 1 downto 0)
            - cfs_in_i : in std_ulogic_vector(IO_CFS_IN_SIZE - 1 downto 0) := (others => U)
            - cfs_out_o : out std_ulogic_vector(IO_CFS_OUT_SIZE - 1 downto 0)
            - neoled_o : out std_ulogic
            - mtime_i : in std_ulogic_vector(63 downto 0) := (others => U)
            - mtime_o : out std_ulogic_vector(63 downto 0)
            - xirq_i : in std_ulogic_vector(XIRQ_NUM_CH - 1 downto 0) := (others => L)
            - mtime_irq_i : in std_ulogic := L
            - msw_irq_i : in std_ulogic := L
            - mext_irq_i : in std_ulogic := L
          Declared:
          Statements:
          Architecures:
          - neorv32_top_avalonmm_rtl
      Architectures:
        - Name: neorv32_top_avalonmm_rtl
          File: neorv32_SystemTop_AvalonMM.vhd
          Position: 215:13
          Entity: neorv32_top_avalonmm
          Declared:
            - signal wb_tag_o : std_ulogic_vector(2 downto 0)
            - signal wb_adr_o : std_ulogic_vector(31 downto 0)
            - signal wb_dat_i : std_ulogic_vector(31 downto 0) := (others => U)
            - signal wb_dat_o : std_ulogic_vector(31 downto 0)
            - signal wb_we_o : std_ulogic
            - signal wb_sel_o : std_ulogic_vector(3 downto 0)
            - signal wb_stb_o : std_ulogic
            - signal wb_cyc_o : std_ulogic
            - signal wb_lock_o : std_ulogic
            - signal wb_ack_i : std_ulogic := L
            - signal wb_err_i : std_ulogic := L
          Hierarchy:
            - neorv32_top_map: component neorv32_top
          Statements:
            ...
            ...
            ...
            ...
            ...
            ...
            ...
      Packages:
      PackageBodies:
      Configurations:
      Contexts:

Teardown

XPASS test_AllVHDLSources[/home/runner/work/extended-tests/extended-tests/NEORV32/rtl/system_integration/neorv32_ProcessorTop_stdlogic.vhd] 0:00:00.269073

Started 2021-11-23 15:22:18
Ended 2021-11-23 15:22:18
Duration 0:00:00.269073
Markers
xfail
Fixtures file

Setup

Call

Captured stdout call
================================================================================
                         pyGHDL.dom - Test Application                          
================================================================================
Parsing file '/home/runner/work/extended-tests/extended-tests/NEORV32/rtl/system_integration/neorv32_ProcessorTop_stdlogic.vhd'
libghdl processing time:  1375.407 us
DOM translation time:    14571.973 us

Design:
  Libraries:
    - Name: pretty
      Entities:
        - neorv32_ProcessorTop_stdlogic(neorv32_ProcessorTop_stdlogic_rtl)
      Packages:
      Configurations:
      Contexts:
  Documents:
    - Path: '/home/runner/work/extended-tests/extended-tests/NEORV32/rtl/system_integration/neorv32_ProcessorTop_stdlogic.vhd':
      Entities:
        - Name: neorv32_ProcessorTop_stdlogic
          File: neorv32_ProcessorTop_stdlogic.vhd
          Position: 42:7
          Generics:
            - CLOCK_FREQUENCY : in natural := 0
            - INT_BOOTLOADER_EN : in boolean := true
            - HW_THREAD_ID : in natural := 0
            - ON_CHIP_DEBUGGER_EN : in boolean := false
            - CPU_EXTENSION_RISCV_A : in boolean := false
            - CPU_EXTENSION_RISCV_B : in boolean := false
            - CPU_EXTENSION_RISCV_C : in boolean := false
            - CPU_EXTENSION_RISCV_E : in boolean := false
            - CPU_EXTENSION_RISCV_M : in boolean := false
            - CPU_EXTENSION_RISCV_U : in boolean := false
            - CPU_EXTENSION_RISCV_Zfinx : in boolean := false
            - CPU_EXTENSION_RISCV_Zicsr : in boolean := true
            - CPU_EXTENSION_RISCV_Zicntr : in boolean := true
            - CPU_EXTENSION_RISCV_Zihpm : in boolean := false
            - CPU_EXTENSION_RISCV_Zifencei : in boolean := false
            - FAST_MUL_EN : in boolean := false
            - FAST_SHIFT_EN : in boolean := false
            - CPU_CNT_WIDTH : in natural := 64
            - PMP_NUM_REGIONS : in natural := 0
            - PMP_MIN_GRANULARITY : in natural := 64 * 1024
            - HPM_NUM_CNTS : in natural := 0
            - HPM_CNT_WIDTH : in natural := 40
            - MEM_INT_IMEM_EN : in boolean := true
            - MEM_INT_IMEM_SIZE : in natural := 16 * 1024
            - MEM_INT_DMEM_EN : in boolean := true
            - MEM_INT_DMEM_SIZE : in natural := 8 * 1024
            - ICACHE_EN : in boolean := false
            - ICACHE_NUM_BLOCKS : in natural := 4
            - ICACHE_BLOCK_SIZE : in natural := 64
            - ICACHE_ASSOCIATIVITY : in natural := 1
            - MEM_EXT_EN : in boolean := false
            - MEM_EXT_TIMEOUT : in natural := 255
            - MEM_EXT_PIPE_MODE : in boolean := false
            - MEM_EXT_BIG_ENDIAN : in boolean := false
            - MEM_EXT_ASYNC_RX : in boolean := false
            - SLINK_NUM_TX : in natural := 0
            - SLINK_NUM_RX : in natural := 0
            - SLINK_TX_FIFO : in natural := 1
            - SLINK_RX_FIFO : in natural := 1
            - XIRQ_NUM_CH : in natural := 0
            - XIRQ_TRIGGER_TYPE : in std_logic_vector(31 downto 0) := (others => 1)
            - XIRQ_TRIGGER_POLARITY : in std_logic_vector(31 downto 0) := (others => 1)
            - IO_GPIO_EN : in boolean := true
            - IO_MTIME_EN : in boolean := true
            - IO_UART0_EN : in boolean := true
            - IO_UART0_RX_FIFO : in natural := 1
            - IO_UART0_TX_FIFO : in natural := 1
            - IO_UART1_EN : in boolean := true
            - IO_UART1_RX_FIFO : in natural := 1
            - IO_UART1_TX_FIFO : in natural := 1
            - IO_SPI_EN : in boolean := true
            - IO_TWI_EN : in boolean := true
            - IO_PWM_NUM_CH : in natural := 4
            - IO_WDT_EN : in boolean := true
            - IO_TRNG_EN : in boolean := false
            - IO_CFS_EN : in boolean := false
            - IO_CFS_CONFIG : in std_ulogic_vector(31 downto 0)
            - IO_CFS_IN_SIZE : in positive := 32
            - IO_CFS_OUT_SIZE : in positive := 32
            - IO_NEOLED_EN : in boolean := true
            - IO_GPTMR_EN : in boolean := false
          Ports:
            - clk_i : in std_logic := 0
            - rstn_i : in std_logic := 0
            - jtag_trst_i : in std_logic := 0
            - jtag_tck_i : in std_logic := 0
            - jtag_tdi_i : in std_logic := 0
            - jtag_tdo_o : out std_logic
            - jtag_tms_i : in std_logic := 0
            - wb_tag_o : out std_logic_vector(2 downto 0)
            - wb_adr_o : out std_logic_vector(31 downto 0)
            - wb_dat_i : in std_logic_vector(31 downto 0) := (others => 0)
            - wb_dat_o : out std_logic_vector(31 downto 0)
            - wb_we_o : out std_logic
            - wb_sel_o : out std_logic_vector(3 downto 0)
            - wb_stb_o : out std_logic
            - wb_cyc_o : out std_logic
            - wb_lock_o : out std_logic
            - wb_ack_i : in std_logic := 0
            - wb_err_i : in std_logic := 0
            - fence_o : out std_logic
            - fencei_o : out std_logic
            - slink_tx_dat_o : out sdata_8x32r_t
            - slink_tx_val_o : out std_logic_vector(7 downto 0)
            - slink_tx_rdy_i : in std_logic_vector(7 downto 0) := (others => 0)
            - slink_rx_dat_i : in sdata_8x32r_t := (others => (others => 0))
            - slink_rx_val_i : in std_logic_vector(7 downto 0) := (others => 0)
            - slink_rx_rdy_o : out std_logic_vector(7 downto 0)
            - gpio_o : out std_logic_vector(63 downto 0)
            - gpio_i : in std_logic_vector(63 downto 0) := (others => 0)
            - uart0_txd_o : out std_logic
            - uart0_rxd_i : in std_logic := 0
            - uart0_rts_o : out std_logic
            - uart0_cts_i : in std_logic := 0
            - uart1_txd_o : out std_logic
            - uart1_rxd_i : in std_logic := 0
            - uart1_rts_o : out std_logic
            - uart1_cts_i : in std_logic := 0
            - spi_sck_o : out std_logic
            - spi_sdo_o : out std_logic
            - spi_sdi_i : in std_logic := 0
            - spi_csn_o : out std_logic_vector(7 downto 0)
            - twi_sda_io : inout std_logic
            - twi_scl_io : inout std_logic
            - pwm_o : out std_logic_vector(IO_PWM_NUM_CH - 1 downto 0)
            - cfs_in_i : in std_logic_vector(IO_CFS_IN_SIZE - 1 downto 0)
            - cfs_out_o : out std_logic_vector(IO_CFS_OUT_SIZE - 1 downto 0)
            - neoled_o : out std_logic
            - mtime_i : in std_logic_vector(63 downto 0) := (others => 0)
            - mtime_o : out std_logic_vector(63 downto 0)
            - xirq_i : in std_logic_vector(XIRQ_NUM_CH - 1 downto 0) := (others => 0)
            - mtime_irq_i : in std_logic := 0
            - msw_irq_i : in std_logic := 0
            - mext_irq_i : in std_logic := 0
          Declared:
          Statements:
          Architecures:
          - neorv32_ProcessorTop_stdlogic_rtl
      Architectures:
        - Name: neorv32_ProcessorTop_stdlogic_rtl
          File: neorv32_ProcessorTop_stdlogic.vhd
          Position: 192:13
          Entity: neorv32_ProcessorTop_stdlogic
          Declared:
            - constant IO_CFS_CONFIG_INT : std_ulogic_vector(31 downto 0) := std_ulogic_vector(IO_CFS_CONFIG)
            - constant XIRQ_TRIGGER_TYPE_INT : std_ulogic_vector(31 downto 0) := std_ulogic_vector(XIRQ_TRIGGER_TYPE)
            - constant XIRQ_TRIGGER_POLARITY_INT : std_ulogic_vector(31 downto 0) := std_ulogic_vector(XIRQ_TRIGGER_POLARITY)
            - signal clk_i_int : std_ulogic
            - signal rstn_i_int : std_ulogic
            - signal jtag_trst_i_int : std_ulogic
            - signal jtag_tck_i_int : std_ulogic
            - signal jtag_tdi_i_int : std_ulogic
            - signal jtag_tdo_o_int : std_ulogic
            - signal jtag_tms_i_int : std_ulogic
            - signal wb_tag_o_int : std_ulogic_vector(2 downto 0)
            - signal wb_adr_o_int : std_ulogic_vector(31 downto 0)
            - signal wb_dat_i_int : std_ulogic_vector(31 downto 0)
            - signal wb_dat_o_int : std_ulogic_vector(31 downto 0)
            - signal wb_we_o_int : std_ulogic
            - signal wb_sel_o_int : std_ulogic_vector(3 downto 0)
            - signal wb_stb_o_int : std_ulogic
            - signal wb_cyc_o_int : std_ulogic
            - signal wb_lock_o_int : std_ulogic
            - signal wb_ack_i_int : std_ulogic
            - signal wb_err_i_int : std_ulogic
            - signal fence_o_int : std_ulogic
            - signal fencei_o_int : std_ulogic
            - signal slink_tx_dat_o_int : sdata_8x32_t
            - signal slink_tx_val_o_int : std_logic_vector(7 downto 0)
            - signal slink_tx_rdy_i_int : std_logic_vector(7 downto 0)
            - signal slink_rx_dat_i_int : sdata_8x32_t
            - signal slink_rx_val_i_int : std_logic_vector(7 downto 0)
            - signal slink_rx_rdy_o_int : std_logic_vector(7 downto 0)
            - signal gpio_o_int : std_ulogic_vector(63 downto 0)
            - signal gpio_i_int : std_ulogic_vector(63 downto 0)
            - signal uart0_txd_o_int : std_ulogic
            - signal uart0_rxd_i_int : std_ulogic
            - signal uart0_rts_o_int : std_ulogic
            - signal uart0_cts_i_int : std_ulogic
            - signal uart1_txd_o_int : std_ulogic
            - signal uart1_rxd_i_int : std_ulogic
            - signal uart1_rts_o_int : std_ulogic
            - signal uart1_cts_i_int : std_ulogic
            - signal spi_sck_o_int : std_ulogic
            - signal spi_sdo_o_int : std_ulogic
            - signal spi_sdi_i_int : std_ulogic
            - signal spi_csn_o_int : std_ulogic_vector(7 downto 0)
            - signal pwm_o_int : std_ulogic_vector(IO_PWM_NUM_CH - 1 downto 0)
            - signal cfs_in_i_int : std_ulogic_vector(IO_CFS_IN_SIZE - 1 downto 0)
            - signal cfs_out_o_int : std_ulogic_vector(IO_CFS_OUT_SIZE - 1 downto 0)
            - signal neoled_o_int : std_ulogic
            - signal mtime_i_int : std_ulogic_vector(63 downto 0)
            - signal mtime_o_int : std_ulogic_vector(63 downto 0)
            - signal xirq_i_int : std_ulogic_vector(XIRQ_NUM_CH - 1 downto 0)
            - signal mtime_irq_i_int : std_ulogic
            - signal msw_irq_i_int : std_ulogic
            - signal mext_irq_i_int : std_ulogic
          Hierarchy:
            - neorv32_top_inst: component neorv32_top
            - slink_conv: for i in 0 to 7 generate
          Statements:
            ...
            ...
            ...
            ...
            ...
            ...
            ...
            ...
            ...
            ...
            ...
            ...
            ...
            ...
            ...
            ...
            ...
            ...
            ...
            ...
            ...
            ...
            ...
            ...
            ...
            ...
            ...
            ...
            ...
            ...
            ...
            ...
            ...
            ...
            ...
            ...
            ...
            ...
            ...
            ...
            ...
            ...
            ...
            ...
            ...
            ...
            ...
            ...
            ...
      Packages:
      PackageBodies:
      Configurations:
      Contexts:

Teardown

XPASS test_AllVHDLSources[/home/runner/work/extended-tests/extended-tests/NEORV32/rtl/core/neorv32_slink.vhd] 0:00:00.264586

Started 2021-11-23 15:22:18
Ended 2021-11-23 15:22:18
Duration 0:00:00.264586
Markers
xfail
Fixtures file

Setup

Call

Captured stdout call
================================================================================
                         pyGHDL.dom - Test Application                          
================================================================================
Parsing file '/home/runner/work/extended-tests/extended-tests/NEORV32/rtl/core/neorv32_slink.vhd'
[NOT IMPLEMENTED] Array_Subtype_Definition
[NOT IMPLEMENTED] Array_Subtype_Definition
[NOT IMPLEMENTED] Concurrent (conditional) signal assignment (label: 'None') at line 183
[NOT IMPLEMENTED] Concurrent (conditional) signal assignment (label: 'None') at line 364
[NOT IMPLEMENTED] Concurrent (conditional) signal assignment (label: 'None') at line 365
libghdl processing time:  1036.105 us
DOM translation time:    14104.071 us

Design:
  Libraries:
    - Name: pretty
      Entities:
        - neorv32_slink(neorv32_slink_rtl)
      Packages:
      Configurations:
      Contexts:
  Documents:
    - Path: '/home/runner/work/extended-tests/extended-tests/NEORV32/rtl/core/neorv32_slink.vhd':
      Entities:
        - Name: neorv32_slink
          File: neorv32_slink.vhd
          Position: 47:7
          Generics:
            - SLINK_NUM_TX : in natural
            - SLINK_NUM_RX : in natural
            - SLINK_TX_FIFO : in natural
            - SLINK_RX_FIFO : in natural
          Ports:
            - clk_i : in std_ulogic
            - addr_i : in std_ulogic_vector(31 downto 0)
            - rden_i : in std_ulogic
            - wren_i : in std_ulogic
            - data_i : in std_ulogic_vector(31 downto 0)
            - data_o : out std_ulogic_vector(31 downto 0)
            - ack_o : out std_ulogic
            - irq_tx_o : out std_ulogic
            - irq_rx_o : out std_ulogic
            - slink_tx_dat_o : out sdata_8x32_t
            - slink_tx_val_o : out std_ulogic_vector(7 downto 0)
            - slink_tx_rdy_i : in std_ulogic_vector(7 downto 0)
            - slink_rx_dat_i : in sdata_8x32_t
            - slink_rx_val_i : in std_ulogic_vector(7 downto 0)
            - slink_rx_rdy_o : out std_ulogic_vector(7 downto 0)
          Declared:
          Statements:
          Architecures:
          - neorv32_slink_rtl
      Architectures:
        - Name: neorv32_slink_rtl
          File: neorv32_slink.vhd
          Position: 77:13
          Entity: neorv32_slink
          Declared:
            - constant hi_abb_c : natural := index_size_f(io_size_c) - 1
            - constant lo_abb_c : natural := index_size_f(slink_size_c)
            - constant ctrl_rx_num_lsb_c : natural := 0
            - constant ctrl_rx_num_msb_c : natural := 3
            - constant ctrl_tx_num_lsb_c : natural := 4
            - constant ctrl_tx_num_msb_c : natural := 7
            - constant ctrl_rx_size_lsb_c : natural := 8
            - constant ctrl_rx_size_msb_c : natural := 11
            - constant ctrl_tx_size_lsb_c : natural := 12
            - constant ctrl_tx_size_msb_c : natural := 15
            - constant ctrl_en_c : natural := 31
            - constant irq_rx_en_lsb_c : natural := 0
            - constant irq_rx_en_msb_c : natural := 7
            - constant irq_rx_mode_lsb_c : natural := 8
            - constant irq_rx_mode_msb_c : natural := 15
            - constant irq_tx_en_lsb_c : natural := 16
            - constant irq_tx_en_msb_c : natural := 23
            - constant irq_tx_mode_lsb_c : natural := 24
            - constant irq_tx_mode_msb_c : natural := 31
            - constant status_rx_avail_lsb_c : natural := 0
            - constant status_rx_avail_msb_c : natural := 7
            - constant status_tx_free_lsb_c : natural := 8
            - constant status_tx_free_msb_c : natural := 15
            - constant status_rx_half_lsb_c : natural := 16
            - constant status_rx_half_msb_c : natural := 23
            - constant status_tx_half_lsb_c : natural := 24
            - constant status_tx_half_msb_c : natural := 31
            - signal ack_read : std_ulogic
            - signal ack_write : std_ulogic
            - signal acc_en : std_ulogic
            - signal addr : std_ulogic_vector(31 downto 0)
            - signal wren : std_ulogic
            - signal rden : std_ulogic
            - signal enable : std_ulogic
            - signal irq_rx_en : std_ulogic_vector(7 downto 0)
            - signal irq_rx_mode : std_ulogic_vector(7 downto 0)
            - signal irq_tx_en : std_ulogic_vector(7 downto 0)
            - signal irq_tx_mode : std_ulogic_vector(7 downto 0)
            - type ???? is array(........) of .....
            - signal rx_fifo_rdata : fifo_data_t
            - signal fifo_clear : std_ulogic
            - signal link_sel : std_ulogic_vector(7 downto 0)
            - signal tx_fifo_we : std_ulogic_vector(7 downto 0)
            - signal rx_fifo_re : std_ulogic_vector(7 downto 0)
            - signal rx_fifo_avail : std_ulogic_vector(7 downto 0)
            - signal tx_fifo_free : std_ulogic_vector(7 downto 0)
            - signal rx_fifo_half : std_ulogic_vector(7 downto 0)
            - signal tx_fifo_half : std_ulogic_vector(7 downto 0)
            - type ???? is array(........) of .....
            - type irq_t is record ..... end record
            - signal rx_irq, tx_irq : irq_t
          Hierarchy:
            - rw_access: process(...)
            - irq_type: process(...)
            - irq_trigger_sync: process(...)
            - irq_trigger_comb: process(...)
            - irq_generator: process(...)
            - link_select: process(...)
            - fifo_access_gen: for i in 0 to 7 generate
            - transmit_fifo_gen: for i in 0 to SLINK_NUM_TX - 1 generate
                - transmit_fifo_inst: component neorv32_fifo
            - transmit_fifo_gen_terminate: for i in SLINK_NUM_TX to 7 generate
            - receive_fifo_gen: for i in 0 to SLINK_NUM_RX - 1 generate
                - receive_fifo_inst: component neorv32_fifo
            - receive_fifo_gen_terminate: for i in SLINK_NUM_RX to 7 generate
          Statements:
            ...
            ...
            ...
            ...
            ...
            ...
            ...
            ...
            ...
            ...
            ...
            ...
            ...
            ...
            ...
            ...
            ...
            ...
            ...
            ...
            ...
            ...
            ...
            ...
            ...
      Packages:
      PackageBodies:
      Configurations:
      Contexts:

Teardown

XPASS test_AllVHDLSources[/home/runner/work/extended-tests/extended-tests/NEORV32/rtl/core/neorv32_cpu_cp_fpu.vhd] 0:00:00.329299

Started 2021-11-23 15:22:18
Ended 2021-11-23 15:22:19
Duration 0:00:00.329299
Markers
xfail
Fixtures file

Setup

Call

Captured stdout call
================================================================================
                         pyGHDL.dom - Test Application                          
================================================================================
Parsing file '/home/runner/work/extended-tests/extended-tests/NEORV32/rtl/core/neorv32_cpu_cp_fpu.vhd'
[NOT IMPLEMENTED] Array_Subtype_Definition
[NOT IMPLEMENTED] Array_Subtype_Definition
[NOT IMPLEMENTED] Concurrent (conditional) signal assignment (label: 'None') at line 274
[NOT IMPLEMENTED] Concurrent (conditional) signal assignment (label: 'None') at line 275
[NOT IMPLEMENTED] Concurrent (conditional) signal assignment (label: 'None') at line 276
[NOT IMPLEMENTED] Concurrent (conditional) signal assignment (label: 'None') at line 277
[NOT IMPLEMENTED] Concurrent (conditional) signal assignment (label: 'None') at line 278
[NOT IMPLEMENTED] Concurrent (conditional) signal assignment (label: 'None') at line 279
[NOT IMPLEMENTED] Concurrent (conditional) signal assignment (label: 'None') at line 280
[NOT IMPLEMENTED] Concurrent (conditional) signal assignment (label: 'None') at line 281
[NOT IMPLEMENTED] Concurrent (conditional) signal assignment (label: 'None') at line 284
[NOT IMPLEMENTED] Concurrent (conditional) signal assignment (label: 'None') at line 300
[NOT IMPLEMENTED] Concurrent (conditional) signal assignment (label: 'None') at line 304
[NOT IMPLEMENTED] Variable assignment (label: 'None') at line 457
[NOT IMPLEMENTED] Variable assignment (label: 'None') at line 481
[NOT IMPLEMENTED] Variable assignment (label: 'None') at line 482
[NOT IMPLEMENTED] Variable assignment (label: 'None') at line 512
[NOT IMPLEMENTED] Variable assignment (label: 'None') at line 514
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[NOT IMPLEMENTED] Variable assignment (label: 'None') at line 520
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[NOT IMPLEMENTED] Variable assignment (label: 'None') at line 682
[NOT IMPLEMENTED] Variable assignment (label: 'None') at line 682
[NOT IMPLEMENTED] Variable assignment (label: 'None') at line 683
[NOT IMPLEMENTED] Variable assignment (label: 'None') at line 683
[NOT IMPLEMENTED] Variable assignment (label: 'None') at line 684
[NOT IMPLEMENTED] Variable assignment (label: 'None') at line 684
[NOT IMPLEMENTED] Variable assignment (label: 'None') at line 685
[NOT IMPLEMENTED] Variable assignment (label: 'None') at line 685
[NOT IMPLEMENTED] Variable assignment (label: 'None') at line 686
[NOT IMPLEMENTED] Variable assignment (label: 'None') at line 686
[NOT IMPLEMENTED] Variable assignment (label: 'None') at line 687
[NOT IMPLEMENTED] Variable assignment (label: 'None') at line 687
[NOT IMPLEMENTED] Variable assignment (label: 'None') at line 688
[NOT IMPLEMENTED] Variable assignment (label: 'None') at line 688
[NOT IMPLEMENTED] Variable assignment (label: 'None') at line 689
[NOT IMPLEMENTED] Variable assignment (label: 'None') at line 689
[NOT IMPLEMENTED] Variable assignment (label: 'None') at line 690
[NOT IMPLEMENTED] Variable assignment (label: 'None') at line 690
[NOT IMPLEMENTED] Variable assignment (label: 'None') at line 691
[NOT IMPLEMENTED] Variable assignment (label: 'None') at line 691
[NOT IMPLEMENTED] Concurrent (conditional) signal assignment (label: 'None') at line 886
[NOT IMPLEMENTED] Concurrent (conditional) signal assignment (label: 'None') at line 887
[NOT IMPLEMENTED] Concurrent (conditional) signal assignment (label: 'None') at line 888
[NOT IMPLEMENTED] Concurrent (conditional) signal assignment (label: 'None') at line 889
[NOT IMPLEMENTED] Concurrent (conditional) signal assignment (label: 'None') at line 892
[NOT IMPLEMENTED] Concurrent (conditional) signal assignment (label: 'None') at line 893
[NOT IMPLEMENTED] Variable assignment (label: 'None') at line 920
[NOT IMPLEMENTED] Variable assignment (label: 'None') at line 920
[NOT IMPLEMENTED] Variable assignment (label: 'None') at line 921
[NOT IMPLEMENTED] Variable assignment (label: 'None') at line 921
[NOT IMPLEMENTED] Variable assignment (label: 'None') at line 922
[NOT IMPLEMENTED] Variable assignment (label: 'None') at line 922
[NOT IMPLEMENTED] Variable assignment (label: 'None') at line 923
[NOT IMPLEMENTED] Variable assignment (label: 'None') at line 923
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[NOT IMPLEMENTED] Variable assignment (label: 'None') at line 924
[NOT IMPLEMENTED] Variable assignment (label: 'None') at line 925
[NOT IMPLEMENTED] Variable assignment (label: 'None') at line 925
[NOT IMPLEMENTED] Variable assignment (label: 'None') at line 926
[NOT IMPLEMENTED] Variable assignment (label: 'None') at line 926
[NOT IMPLEMENTED] Variable assignment (label: 'None') at line 927
[NOT IMPLEMENTED] Variable assignment (label: 'None') at line 927
[NOT IMPLEMENTED] Variable assignment (label: 'None') at line 928
[NOT IMPLEMENTED] Variable assignment (label: 'None') at line 928
[NOT IMPLEMENTED] Variable assignment (label: 'None') at line 929
[NOT IMPLEMENTED] Variable assignment (label: 'None') at line 929
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Variable assignment (label: 'None') at line 1535
[NOT IMPLEMENTED] Variable assignment (label: 'None') at line 1834
libghdl processing time:  3950.220 us
DOM translation time:    74044.472 us

Design:
  Libraries:
    - Name: pretty
      Entities:
        - neorv32_cpu_cp_fpu(neorv32_cpu_cp_fpu_rtl)
        - neorv32_cpu_cp_fpu_normalizer(neorv32_cpu_cp_fpu_normalizer_rtl)
        - neorv32_cpu_cp_fpu_f2i(neorv32_cpu_cp_fpu_f2i_rtl)
      Packages:
      Configurations:
      Contexts:
  Documents:
    - Path: '/home/runner/work/extended-tests/extended-tests/NEORV32/rtl/core/neorv32_cpu_cp_fpu.vhd':
      Entities:
        - Name: neorv32_cpu_cp_fpu
          File: neorv32_cpu_cp_fpu.vhd
          Position: 58:7
          Generics:
          Ports:
            - clk_i : in std_ulogic
            - rstn_i : in std_ulogic
            - ctrl_i : in std_ulogic_vector(ctrl_width_c - 1 downto 0)
            - start_i : in std_ulogic
            - cmp_i : in std_ulogic_vector(1 downto 0)
            - rs1_i : in std_ulogic_vector(data_width_c - 1 downto 0)
            - rs2_i : in std_ulogic_vector(data_width_c - 1 downto 0)
            - res_o : out std_ulogic_vector(data_width_c - 1 downto 0)
            - fflags_o : out std_ulogic_vector(4 downto 0)
            - valid_o : out std_ulogic
          Declared:
          Statements:
          Architecures:
          - neorv32_cpu_cp_fpu_rtl
        - Name: neorv32_cpu_cp_fpu_normalizer
          File: neorv32_cpu_cp_fpu.vhd
          Position: 1211:7
          Generics:
          Ports:
            - clk_i : in std_ulogic
            - rstn_i : in std_ulogic
            - start_i : in std_ulogic
            - rmode_i : in std_ulogic_vector(2 downto 0)
            - funct_i : in std_ulogic
            - sign_i : in std_ulogic
            - exponent_i : in std_ulogic_vector(8 downto 0)
            - mantissa_i : in std_ulogic_vector(47 downto 0)
            - integer_i : in std_ulogic_vector(31 downto 0)
            - class_i : in std_ulogic_vector(9 downto 0)
            - flags_i : in std_ulogic_vector(4 downto 0)
            - result_o : out std_ulogic_vector(31 downto 0)
            - flags_o : out std_ulogic_vector(4 downto 0)
            - done_o : out std_ulogic
          Declared:
          Statements:
          Architecures:
          - neorv32_cpu_cp_fpu_normalizer_rtl
        - Name: neorv32_cpu_cp_fpu_f2i
          File: neorv32_cpu_cp_fpu.vhd
          Position: 1594:7
          Generics:
          Ports:
            - clk_i : in std_ulogic
            - rstn_i : in std_ulogic
            - start_i : in std_ulogic
            - rmode_i : in std_ulogic_vector(2 downto 0)
            - funct_i : in std_ulogic
            - sign_i : in std_ulogic
            - exponent_i : in std_ulogic_vector(7 downto 0)
            - mantissa_i : in std_ulogic_vector(22 downto 0)
            - class_i : in std_ulogic_vector(9 downto 0)
            - result_o : out std_ulogic_vector(31 downto 0)
            - flags_o : out std_ulogic_vector(4 downto 0)
            - done_o : out std_ulogic
          Declared:
          Statements:
          Architecures:
          - neorv32_cpu_cp_fpu_f2i_rtl
      Architectures:
        - Name: neorv32_cpu_cp_fpu_rtl
          File: neorv32_cpu_cp_fpu.vhd
          Position: 76:13
          Entity: neorv32_cpu_cp_fpu
          Declared:
            - constant op_class_c : std_ulogic_vector(2 downto 0) := "000"
            - constant op_comp_c : std_ulogic_vector(2 downto 0) := "001"
            - constant op_i2f_c : std_ulogic_vector(2 downto 0) := "010"
            - constant op_f2i_c : std_ulogic_vector(2 downto 0) := "011"
            - constant op_sgnj_c : std_ulogic_vector(2 downto 0) := "100"
            - constant op_minmax_c : std_ulogic_vector(2 downto 0) := "101"
            - constant op_addsub_c : std_ulogic_vector(2 downto 0) := "110"
            - constant op_mul_c : std_ulogic_vector(2 downto 0) := "111"
            - Component: neorv32_cpu_cp_fpu_f2i
              Generics:
              Ports:
                - clk_i : in std_ulogic
                - rstn_i : in std_ulogic
                - start_i : in std_ulogic
                - rmode_i : in std_ulogic_vector(2 downto 0)
                - funct_i : in std_ulogic
                - sign_i : in std_ulogic
                - exponent_i : in std_ulogic_vector(7 downto 0)
                - mantissa_i : in std_ulogic_vector(22 downto 0)
                - class_i : in std_ulogic_vector(9 downto 0)
                - result_o : out std_ulogic_vector(31 downto 0)
                - flags_o : out std_ulogic_vector(4 downto 0)
                - done_o : out std_ulogic
            - Component: neorv32_cpu_cp_fpu_normalizer
              Generics:
              Ports:
                - clk_i : in std_ulogic
                - rstn_i : in std_ulogic
                - start_i : in std_ulogic
                - rmode_i : in std_ulogic_vector(2 downto 0)
                - funct_i : in std_ulogic
                - sign_i : in std_ulogic
                - exponent_i : in std_ulogic_vector(8 downto 0)
                - mantissa_i : in std_ulogic_vector(47 downto 0)
                - integer_i : in std_ulogic_vector(31 downto 0)
                - class_i : in std_ulogic_vector(9 downto 0)
                - flags_i : in std_ulogic_vector(4 downto 0)
                - result_o : out std_ulogic_vector(31 downto 0)
                - flags_o : out std_ulogic_vector(4 downto 0)
                - done_o : out std_ulogic
            - type cmd_t is record ..... end record
            - signal cmd : cmd_t
            - signal funct_ff : std_ulogic_vector(2 downto 0)
            - type ctrl_state_t is (........)
            - type ctrl_engine_t is record ..... end record
            - signal ctrl_engine : ctrl_engine_t
            - type ???? is array(........) of .....
            - type ???? is array(........) of .....
            - type fpu_operands_t is record ..... end record
            - signal op_data : op_data_t
            - signal op_class : op_class_t
            - signal fpu_operands : fpu_operands_t
            - signal cmp_ff : std_ulogic_vector(1 downto 0)
            - signal comp_equal_ff : std_ulogic
            - signal comp_less_ff : std_ulogic
            - type fu_interface_t is record ..... end record
            - signal fu_classify : fu_interface_t
            - signal fu_compare : fu_interface_t
            - signal fu_sign_inject : fu_interface_t
            - signal fu_min_max : fu_interface_t
            - signal fu_conv_f2i : fu_interface_t
            - signal fu_addsub : fu_interface_t
            - signal fu_mul : fu_interface_t
            - signal fu_core_done : std_ulogic
            - type fu_i2f_interface_t is record ..... end record
            - signal fu_conv_i2f : fu_i2f_interface_t
            - type multiplier_t is record ..... end record
            - signal multiplier : multiplier_t
            - type addsub_t is record ..... end record
            - signal addsub : addsub_t
            - type normalizer_t is record ..... end record
            - signal normalizer : normalizer_t
          Hierarchy:
            - number_classifier: process(...)
            - control_engine_fsm: process(...)
            - float_comparator: process(...)
            - float_comparison: process(...)
            - min_max_select: process(...)
            - neorv32_cpu_cp_fpu_f2i_inst: component neorv32_cpu_cp_fpu_f2i
            - sign_injector: process(...)
            - convert_i2f: process(...)
            - multiplier_core: process(...)
            - multiplier_class_core: process(...)
            - adder_subtractor_core: process(...)
            - adder_subtractor_class_core: process(...)
            - normalizer_input_select: process(...)
            - neorv32_cpu_cp_fpu_normalizer_inst: component neorv32_cpu_cp_fpu_normalizer
            - output_gate: process(...)
          Statements:
            ...
            ...
            ...
            ...
            ...
            ...
            ...
            ...
            ...
            ...
            ...
            ...
            ...
            ...
            ...
            ...
            ...
            ...
            ...
            ...
            ...
            ...
            ...
            ...
            ...
            ...
            ...
            ...
            ...
            ...
            ...
            ...
            ...
            ...
            ...
            ...
            ...
            ...
            ...
            ...
            ...
            ...
            ...
            ...
            ...
            ...
            ...
            ...
            ...
            ...
            ...
            ...
            ...
            ...
            ...
            ...
            ...
            ...
        - Name: neorv32_cpu_cp_fpu_normalizer_rtl
          File: neorv32_cpu_cp_fpu.vhd
          Position: 1233:13
          Entity: neorv32_cpu_cp_fpu_normalizer
          Declared:
            - type ctrl_engine_state_t is (........)
            - type ctrl_t is record ..... end record
            - signal ctrl : ctrl_t
            - type sreg_t is record ..... end record
            - signal sreg : sreg_t
            - type round_t is record ..... end record
            - signal round : round_t
          Hierarchy:
            - ctrl_engine: process(...)
            - rounding_unit_ctrl: process(...)
            - rounding_unit_add: process(...)
          Statements:
            ...
            ...
            ...
            ...
            ...
            ...
            ...
            ...
            ...
            ...
            ...
            ...
            ...
        - Name: neorv32_cpu_cp_fpu_f2i_rtl
          File: neorv32_cpu_cp_fpu.vhd
          Position: 1614:13
          Entity: neorv32_cpu_cp_fpu_f2i
          Declared:
            - type ctrl_engine_state_t is (........)
            - type ctrl_t is record ..... end record
            - signal ctrl : ctrl_t
            - type sreg_t is record ..... end record
            - signal sreg : sreg_t
            - type round_t is record ..... end record
            - signal round : round_t
          Hierarchy:
            - ctrl_engine: process(...)
            - rounding_unit_ctrl: process(...)
            - rounding_unit_add: process(...)
          Statements:
            ...
            ...
            ...
            ...
            ...
            ...
            ...
            ...
            ...
            ...
            ...
      Packages:
      PackageBodies:
      Configurations:
      Contexts:

Teardown

XPASS test_AllVHDLSources[/home/runner/work/extended-tests/extended-tests/NEORV32/rtl/core/neorv32_top.vhd] 0:00:00.301952

Started 2021-11-23 15:22:18
Ended 2021-11-23 15:22:19
Duration 0:00:00.301952
Markers
xfail
Fixtures file

Setup

Call

Captured stdout call
================================================================================
                         pyGHDL.dom - Test Application                          
================================================================================
Parsing file '/home/runner/work/extended-tests/extended-tests/NEORV32/rtl/core/neorv32_top.vhd'
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Array_Subtype_Definition
[NOT IMPLEMENTED] Variable assignment (label: 'None') at line 668
[NOT IMPLEMENTED] Variable assignment (label: 'None') at line 669
[NOT IMPLEMENTED] Variable assignment (label: 'None') at line 670
[NOT IMPLEMENTED] Concurrent (conditional) signal assignment (label: 'None') at line 860
[NOT IMPLEMENTED] Concurrent (conditional) signal assignment (label: 'None') at line 1016
libghdl processing time:  2710.014 us
DOM translation time:    45647.929 us

Design:
  Libraries:
    - Name: pretty
      Entities:
        - neorv32_top(neorv32_top_rtl)
      Packages:
      Configurations:
      Contexts:
  Documents:
    - Path: '/home/runner/work/extended-tests/extended-tests/NEORV32/rtl/core/neorv32_top.vhd':
      Entities:
        - Name: neorv32_top
          File: neorv32_top.vhd
          Position: 47:7
          Generics:
            - CLOCK_FREQUENCY : in natural
            - HW_THREAD_ID : in natural := 0
            - INT_BOOTLOADER_EN : in boolean := false
            - ON_CHIP_DEBUGGER_EN : in boolean := false
            - CPU_EXTENSION_RISCV_A : in boolean := false
            - CPU_EXTENSION_RISCV_B : in boolean := false
            - CPU_EXTENSION_RISCV_C : in boolean := false
            - CPU_EXTENSION_RISCV_E : in boolean := false
            - CPU_EXTENSION_RISCV_M : in boolean := false
            - CPU_EXTENSION_RISCV_U : in boolean := false
            - CPU_EXTENSION_RISCV_Zfinx : in boolean := false
            - CPU_EXTENSION_RISCV_Zicsr : in boolean := true
            - CPU_EXTENSION_RISCV_Zicntr : in boolean := true
            - CPU_EXTENSION_RISCV_Zihpm : in boolean := false
            - CPU_EXTENSION_RISCV_Zifencei : in boolean := false
            - CPU_EXTENSION_RISCV_Zmmul : in boolean := false
            - FAST_MUL_EN : in boolean := false
            - FAST_SHIFT_EN : in boolean := false
            - CPU_CNT_WIDTH : in natural := 64
            - CPU_IPB_ENTRIES : in natural := 2
            - PMP_NUM_REGIONS : in natural := 0
            - PMP_MIN_GRANULARITY : in natural := 64 * 1024
            - HPM_NUM_CNTS : in natural := 0
            - HPM_CNT_WIDTH : in natural := 40
            - MEM_INT_IMEM_EN : in boolean := false
            - MEM_INT_IMEM_SIZE : in natural := 16 * 1024
            - MEM_INT_DMEM_EN : in boolean := false
            - MEM_INT_DMEM_SIZE : in natural := 8 * 1024
            - ICACHE_EN : in boolean := false
            - ICACHE_NUM_BLOCKS : in natural := 4
            - ICACHE_BLOCK_SIZE : in natural := 64
            - ICACHE_ASSOCIATIVITY : in natural := 1
            - MEM_EXT_EN : in boolean := false
            - MEM_EXT_TIMEOUT : in natural := 255
            - MEM_EXT_PIPE_MODE : in boolean := false
            - MEM_EXT_BIG_ENDIAN : in boolean := false
            - MEM_EXT_ASYNC_RX : in boolean := false
            - SLINK_NUM_TX : in natural := 0
            - SLINK_NUM_RX : in natural := 0
            - SLINK_TX_FIFO : in natural := 1
            - SLINK_RX_FIFO : in natural := 1
            - XIRQ_NUM_CH : in natural := 0
            - XIRQ_TRIGGER_TYPE : in std_ulogic_vector(31 downto 0)
            - XIRQ_TRIGGER_POLARITY : in std_ulogic_vector(31 downto 0)
            - IO_GPIO_EN : in boolean := false
            - IO_MTIME_EN : in boolean := false
            - IO_UART0_EN : in boolean := false
            - IO_UART0_RX_FIFO : in natural := 1
            - IO_UART0_TX_FIFO : in natural := 1
            - IO_UART1_EN : in boolean := false
            - IO_UART1_RX_FIFO : in natural := 1
            - IO_UART1_TX_FIFO : in natural := 1
            - IO_SPI_EN : in boolean := false
            - IO_TWI_EN : in boolean := false
            - IO_PWM_NUM_CH : in natural := 0
            - IO_WDT_EN : in boolean := false
            - IO_TRNG_EN : in boolean := false
            - IO_CFS_EN : in boolean := false
            - IO_CFS_CONFIG : in std_ulogic_vector(31 downto 0)
            - IO_CFS_IN_SIZE : in positive := 32
            - IO_CFS_OUT_SIZE : in positive := 32
            - IO_NEOLED_EN : in boolean := false
            - IO_NEOLED_TX_FIFO : in natural := 1
            - IO_GPTMR_EN : in boolean := false
          Ports:
            - clk_i : in std_ulogic
            - rstn_i : in std_ulogic
            - jtag_trst_i : in std_ulogic := U
            - jtag_tck_i : in std_ulogic := U
            - jtag_tdi_i : in std_ulogic := U
            - jtag_tdo_o : out std_ulogic
            - jtag_tms_i : in std_ulogic := U
            - wb_tag_o : out std_ulogic_vector(2 downto 0)
            - wb_adr_o : out std_ulogic_vector(31 downto 0)
            - wb_dat_i : in std_ulogic_vector(31 downto 0) := (others => U)
            - wb_dat_o : out std_ulogic_vector(31 downto 0)
            - wb_we_o : out std_ulogic
            - wb_sel_o : out std_ulogic_vector(3 downto 0)
            - wb_stb_o : out std_ulogic
            - wb_cyc_o : out std_ulogic
            - wb_lock_o : out std_ulogic
            - wb_ack_i : in std_ulogic := L
            - wb_err_i : in std_ulogic := L
            - fence_o : out std_ulogic
            - fencei_o : out std_ulogic
            - slink_tx_dat_o : out sdata_8x32_t
            - slink_tx_val_o : out std_ulogic_vector(7 downto 0)
            - slink_tx_rdy_i : in std_ulogic_vector(7 downto 0) := (others => L)
            - slink_rx_dat_i : in sdata_8x32_t := (others => (others => U))
            - slink_rx_val_i : in std_ulogic_vector(7 downto 0) := (others => L)
            - slink_rx_rdy_o : out std_ulogic_vector(7 downto 0)
            - gpio_o : out std_ulogic_vector(63 downto 0)
            - gpio_i : in std_ulogic_vector(63 downto 0) := (others => U)
            - uart0_txd_o : out std_ulogic
            - uart0_rxd_i : in std_ulogic := U
            - uart0_rts_o : out std_ulogic
            - uart0_cts_i : in std_ulogic := L
            - uart1_txd_o : out std_ulogic
            - uart1_rxd_i : in std_ulogic := U
            - uart1_rts_o : out std_ulogic
            - uart1_cts_i : in std_ulogic := L
            - spi_sck_o : out std_ulogic
            - spi_sdo_o : out std_ulogic
            - spi_sdi_i : in std_ulogic := U
            - spi_csn_o : out std_ulogic_vector(7 downto 0)
            - twi_sda_io : inout std_logic := U
            - twi_scl_io : inout std_logic := U
            - pwm_o : out std_ulogic_vector(IO_PWM_NUM_CH - 1 downto 0)
            - cfs_in_i : in std_ulogic_vector(IO_CFS_IN_SIZE - 1 downto 0) := (others => U)
            - cfs_out_o : out std_ulogic_vector(IO_CFS_OUT_SIZE - 1 downto 0)
            - neoled_o : out std_ulogic
            - mtime_i : in std_ulogic_vector(63 downto 0) := (others => U)
            - mtime_o : out std_ulogic_vector(63 downto 0)
            - xirq_i : in std_ulogic_vector(XIRQ_NUM_CH - 1 downto 0) := (others => L)
            - mtime_irq_i : in std_ulogic := L
            - msw_irq_i : in std_ulogic := L
            - mext_irq_i : in std_ulogic := L
          Declared:
          Statements:
          Architecures:
          - neorv32_top_rtl
      Architectures:
        - Name: neorv32_top_rtl
          File: neorv32_top.vhd
          Position: 228:13
          Entity: neorv32_top
          Declared:
            - constant cpu_boot_addr_c : std_ulogic_vector(31 downto 0) := cond_sel_stdulogicvector_f(INT_BOOTLOADER_EN, boot_rom_base_c, ispace_base_c)
            - constant imem_align_check_c : std_ulogic_vector(index_size_f(MEM_INT_IMEM_SIZE) - 1 downto 0) := (others => 0)
            - constant dmem_align_check_c : std_ulogic_vector(index_size_f(MEM_INT_DMEM_SIZE) - 1 downto 0) := (others => 0)
            - constant io_slink_en_c : boolean := boolean(SLINK_NUM_RX > 0) or boolean(SLINK_NUM_TX > 0)
            - signal rstn_gen : std_ulogic_vector(7 downto 0) := (others => 0)
            - signal ext_rstn : std_ulogic
            - signal sys_rstn : std_ulogic
            - signal wdt_rstn : std_ulogic
            - signal clk_div : std_ulogic_vector(11 downto 0)
            - signal clk_div_ff : std_ulogic_vector(11 downto 0)
            - signal clk_gen : std_ulogic_vector(7 downto 0)
            - signal clk_gen_en : std_ulogic_vector(8 downto 0)
            - signal wdt_cg_en : std_ulogic
            - signal uart0_cg_en : std_ulogic
            - signal uart1_cg_en : std_ulogic
            - signal spi_cg_en : std_ulogic
            - signal twi_cg_en : std_ulogic
            - signal pwm_cg_en : std_ulogic
            - signal cfs_cg_en : std_ulogic
            - signal neoled_cg_en : std_ulogic
            - signal gptmr_cg_en : std_ulogic
            - type bus_interface_t is record ..... end record
            - signal cpu_i, i_cache, cpu_d, p_bus : bus_interface_t
            - signal bus_error : std_ulogic
            - signal dci_ndmrstn : std_ulogic
            - signal dci_halt_req : std_ulogic
            - type dmi_t is record ..... end record
            - signal dmi : dmi_t
            - signal io_acc : std_ulogic
            - signal io_rden : std_ulogic
            - signal io_wren : std_ulogic
            - type resp_bus_entry_t is record ..... end record
            - constant resp_bus_entry_terminate_c : resp_bus_entry_t := (rdata => (others => 0), ack => 0, err => 0)
            - type resp_bus_id_t is (........)
            - type ???? is array(........) of .....
            - signal resp_bus : resp_bus_t := (others => resp_bus_entry_terminate_c)
            - signal fast_irq : std_ulogic_vector(15 downto 0)
            - signal mtime_irq : std_ulogic
            - signal wdt_irq : std_ulogic
            - signal uart0_rxd_irq : std_ulogic
            - signal uart0_txd_irq : std_ulogic
            - signal uart1_rxd_irq : std_ulogic
            - signal uart1_txd_irq : std_ulogic
            - signal spi_irq : std_ulogic
            - signal twi_irq : std_ulogic
            - signal cfs_irq : std_ulogic
            - signal neoled_irq : std_ulogic
            - signal slink_tx_irq : std_ulogic
            - signal slink_rx_irq : std_ulogic
            - signal xirq_irq : std_ulogic
            - signal gptmr_irq : std_ulogic
            - signal mtime_time : std_ulogic_vector(63 downto 0)
            - signal ext_timeout : std_ulogic
            - signal ext_access : std_ulogic
          Hierarchy:
            - reset_generator: process(...)
            - clock_generator: process(...)
            - neorv32_cpu_inst: component neorv32_cpu
            - neorv32_icache_inst_true: if (ICACHE_EN = true) generate
                - neorv32_icache_inst: component neorv32_icache
            - neorv32_icache_inst_false: if (ICACHE_EN = false) generate
            - neorv32_busswitch_inst: component neorv32_busswitch
            - bus_response: process(...)
            - neorv32_bus_keeper_inst: component neorv32_bus_keeper
            - neorv32_int_imem_inst_true: if (MEM_INT_IMEM_EN = true) and (MEM_INT_IMEM_SIZE > 0) generate
                - neorv32_int_imem_inst: component neorv32_imem
            - neorv32_int_imem_inst_false: if (MEM_INT_IMEM_EN = false) or (MEM_INT_IMEM_SIZE = 0) generate
            - neorv32_int_dmem_inst_true: if (MEM_INT_DMEM_EN = true) and (MEM_INT_DMEM_SIZE > 0) generate
                - neorv32_int_dmem_inst: component neorv32_dmem
            - neorv32_int_dmem_inst_false: if (MEM_INT_DMEM_EN = false) or (MEM_INT_DMEM_SIZE = 0) generate
            - neorv32_boot_rom_inst_true: if (INT_BOOTLOADER_EN = true) generate
                - neorv32_boot_rom_inst: component neorv32_boot_rom
            - neorv32_boot_rom_inst_false: if (INT_BOOTLOADER_EN = false) generate
            - neorv32_wishbone_inst_true: if (MEM_EXT_EN = true) generate
                - neorv32_wishbone_inst: component neorv32_wishbone
            - neorv32_wishbone_inst_false: if (MEM_EXT_EN = false) generate
            - neorv32_cfs_inst_true: if (IO_CFS_EN = true) generate
                - neorv32_cfs_inst: component neorv32_cfs
            - neorv32_cfs_inst_false: if (IO_CFS_EN = false) generate
            - neorv32_gpio_inst_true: if (IO_GPIO_EN = true) generate
                - neorv32_gpio_inst: component neorv32_gpio
            - neorv32_gpio_inst_false: if (IO_GPIO_EN = false) generate
            - neorv32_wdt_inst_true: if (IO_WDT_EN = true) generate
                - neorv32_wdt_inst: component neorv32_wdt
            - neorv32_wdt_inst_false: if (IO_WDT_EN = false) generate
            - neorv32_mtime_inst_true: if (IO_MTIME_EN = true) generate
                - neorv32_mtime_inst: component neorv32_mtime
            - neorv32_mtime_inst_false: if (IO_MTIME_EN = false) generate
            - mtime_sync: process(...)
            - neorv32_uart0_inst_true: if (IO_UART0_EN = true) generate
                - neorv32_uart0_inst: component neorv32_uart
            - neorv32_uart0_inst_false: if (IO_UART0_EN = false) generate
            - neorv32_uart1_inst_true: if (IO_UART1_EN = true) generate
                - neorv32_uart1_inst: component neorv32_uart
            - neorv32_uart1_inst_false: if (IO_UART1_EN = false) generate
            - neorv32_spi_inst_true: if (IO_SPI_EN = true) generate
                - neorv32_spi_inst: component neorv32_spi
            - neorv32_spi_inst_false: if (IO_SPI_EN = false) generate
            - neorv32_twi_inst_true: if (IO_TWI_EN = true) generate
                - neorv32_twi_inst: component neorv32_twi
            - neorv32_twi_inst_false: if (IO_TWI_EN = false) generate
            - neorv32_pwm_inst_true: if (IO_PWM_NUM_CH > 0) generate
                - neorv32_pwm_inst: component neorv32_pwm
            - neorv32_pwm_inst_false: if (IO_PWM_NUM_CH = 0) generate
            - neorv32_trng_inst_true: if (IO_TRNG_EN = true) generate
                - neorv32_trng_inst: component neorv32_trng
            - neorv32_trng_inst_false: if (IO_TRNG_EN = false) generate
            - neorv32_neoled_inst_true: if (IO_NEOLED_EN = true) generate
                - neorv32_neoled_inst: component neorv32_neoled
            - neorv32_neoled_inst_false: if (IO_NEOLED_EN = false) generate
            - neorv32_slink_inst_true: if (io_slink_en_c = true) generate
                - neorv32_slink_inst: component neorv32_slink
            - neorv32_slink_inst_false: if (io_slink_en_c = false) generate
            - neorv32_xirq_inst_true: if (XIRQ_NUM_CH > 0) generate
                - neorv32_slink_inst: component neorv32_xirq
            - neorv32_xirq_inst_false: if (XIRQ_NUM_CH = 0) generate
            - neorv32_gptmr_inst_true: if (IO_GPTMR_EN = true) generate
                - neorv32_gptmr_inst: component neorv32_gptmr
            - neorv32_gptmr_inst_false: if (IO_GPTMR_EN = false) generate
            - neorv32_sysinfo_inst: component neorv32_sysinfo
            - neorv32_neorv32_debug_dm_true: if (ON_CHIP_DEBUGGER_EN = true) generate
                - neorv32_debug_dm_inst: component neorv32_debug_dm
            - neorv32_debug_dm_false: if (ON_CHIP_DEBUGGER_EN = false) generate
            - neorv32_neorv32_debug_dtm_true: if (ON_CHIP_DEBUGGER_EN = true) generate
                - neorv32_debug_dtm_inst: component neorv32_debug_dtm
            - neorv32_debug_dtm_false: if (ON_CHIP_DEBUGGER_EN = false) generate
          Statements:
            ...
            ...
            ...
            ...
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            ...
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      Packages:
      PackageBodies:
      Configurations:
      Contexts:

Teardown

XPASS test_AllVHDLSources[/home/runner/work/extended-tests/extended-tests/NEORV32/rtl/core/neorv32_cpu.vhd] 0:00:00.250065

Started 2021-11-23 15:22:19
Ended 2021-11-23 15:22:19
Duration 0:00:00.250065
Markers
xfail
Fixtures file

Setup

Call

Captured stdout call
================================================================================
                         pyGHDL.dom - Test Application                          
================================================================================
Parsing file '/home/runner/work/extended-tests/extended-tests/NEORV32/rtl/core/neorv32_cpu.vhd'
libghdl processing time:  852.804 us
DOM translation time:    11264.557 us

Design:
  Libraries:
    - Name: pretty
      Entities:
        - neorv32_cpu(neorv32_cpu_rtl)
      Packages:
      Configurations:
      Contexts:
  Documents:
    - Path: '/home/runner/work/extended-tests/extended-tests/NEORV32/rtl/core/neorv32_cpu.vhd':
      Entities:
        - Name: neorv32_cpu
          File: neorv32_cpu.vhd
          Position: 60:7
          Generics:
            - HW_THREAD_ID : in natural
            - CPU_BOOT_ADDR : in std_ulogic_vector(31 downto 0)
            - CPU_DEBUG_ADDR : in std_ulogic_vector(31 downto 0)
            - CPU_EXTENSION_RISCV_A : in boolean
            - CPU_EXTENSION_RISCV_B : in boolean
            - CPU_EXTENSION_RISCV_C : in boolean
            - CPU_EXTENSION_RISCV_E : in boolean
            - CPU_EXTENSION_RISCV_M : in boolean
            - CPU_EXTENSION_RISCV_U : in boolean
            - CPU_EXTENSION_RISCV_Zfinx : in boolean
            - CPU_EXTENSION_RISCV_Zicsr : in boolean
            - CPU_EXTENSION_RISCV_Zicntr : in boolean
            - CPU_EXTENSION_RISCV_Zihpm : in boolean
            - CPU_EXTENSION_RISCV_Zifencei : in boolean
            - CPU_EXTENSION_RISCV_Zmmul : in boolean
            - CPU_EXTENSION_RISCV_DEBUG : in boolean
            - FAST_MUL_EN : in boolean
            - FAST_SHIFT_EN : in boolean
            - CPU_CNT_WIDTH : in natural
            - CPU_IPB_ENTRIES : in natural
            - PMP_NUM_REGIONS : in natural
            - PMP_MIN_GRANULARITY : in natural
            - HPM_NUM_CNTS : in natural
            - HPM_CNT_WIDTH : in natural
          Ports:
            - clk_i : in std_ulogic
            - rstn_i : in std_ulogic
            - sleep_o : out std_ulogic
            - i_bus_addr_o : out std_ulogic_vector(data_width_c - 1 downto 0)
            - i_bus_rdata_i : in std_ulogic_vector(data_width_c - 1 downto 0)
            - i_bus_wdata_o : out std_ulogic_vector(data_width_c - 1 downto 0)
            - i_bus_ben_o : out std_ulogic_vector(3 downto 0)
            - i_bus_we_o : out std_ulogic
            - i_bus_re_o : out std_ulogic
            - i_bus_lock_o : out std_ulogic
            - i_bus_ack_i : in std_ulogic
            - i_bus_err_i : in std_ulogic
            - i_bus_fence_o : out std_ulogic
            - i_bus_priv_o : out std_ulogic_vector(1 downto 0)
            - d_bus_addr_o : out std_ulogic_vector(data_width_c - 1 downto 0)
            - d_bus_rdata_i : in std_ulogic_vector(data_width_c - 1 downto 0)
            - d_bus_wdata_o : out std_ulogic_vector(data_width_c - 1 downto 0)
            - d_bus_ben_o : out std_ulogic_vector(3 downto 0)
            - d_bus_we_o : out std_ulogic
            - d_bus_re_o : out std_ulogic
            - d_bus_lock_o : out std_ulogic
            - d_bus_ack_i : in std_ulogic
            - d_bus_err_i : in std_ulogic
            - d_bus_fence_o : out std_ulogic
            - d_bus_priv_o : out std_ulogic_vector(1 downto 0)
            - time_i : in std_ulogic_vector(63 downto 0)
            - msw_irq_i : in std_ulogic
            - mext_irq_i : in std_ulogic
            - mtime_irq_i : in std_ulogic
            - firq_i : in std_ulogic_vector(15 downto 0)
            - db_halt_req_i : in std_ulogic
          Declared:
          Statements:
          Architecures:
          - neorv32_cpu_rtl
      Architectures:
        - Name: neorv32_cpu_rtl
          File: neorv32_cpu.vhd
          Position: 134:13
          Entity: neorv32_cpu
          Declared:
            - signal ctrl : std_ulogic_vector(ctrl_width_c - 1 downto 0)
            - signal comparator : std_ulogic_vector(1 downto 0)
            - signal imm : std_ulogic_vector(data_width_c - 1 downto 0)
            - signal instr : std_ulogic_vector(data_width_c - 1 downto 0)
            - signal rs1, rs2 : std_ulogic_vector(data_width_c - 1 downto 0)
            - signal alu_res : std_ulogic_vector(data_width_c - 1 downto 0)
            - signal alu_add : std_ulogic_vector(data_width_c - 1 downto 0)
            - signal mem_rdata : std_ulogic_vector(data_width_c - 1 downto 0)
            - signal alu_idone : std_ulogic
            - signal bus_i_wait : std_ulogic
            - signal bus_d_wait : std_ulogic
            - signal csr_rdata : std_ulogic_vector(data_width_c - 1 downto 0)
            - signal mar : std_ulogic_vector(data_width_c - 1 downto 0)
            - signal ma_instr : std_ulogic
            - signal ma_load : std_ulogic
            - signal ma_store : std_ulogic
            - signal excl_state : std_ulogic
            - signal be_instr : std_ulogic
            - signal be_load : std_ulogic
            - signal be_store : std_ulogic
            - signal fetch_pc : std_ulogic_vector(data_width_c - 1 downto 0)
            - signal curr_pc : std_ulogic_vector(data_width_c - 1 downto 0)
            - signal next_pc : std_ulogic_vector(data_width_c - 1 downto 0)
            - signal fpu_flags : std_ulogic_vector(4 downto 0)
            - signal pmp_addr : pmp_addr_if_t
            - signal pmp_ctrl : pmp_ctrl_if_t
          Hierarchy:
            - neorv32_cpu_control_inst: component neorv32_cpu_control
            - neorv32_cpu_regfile_inst: component neorv32_cpu_regfile
            - neorv32_cpu_alu_inst: component neorv32_cpu_alu
            - neorv32_cpu_bus_inst: component neorv32_cpu_bus
          Statements:
            ...
            ...
            ...
            ...
            ...
            ...
            ...
            ...
            ...
            ...
            ...
            ...
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            ...
            ...
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            ...
            ...
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            ...
            ...
            ...
            ...
      Packages:
      PackageBodies:
      Configurations:
      Contexts:

Teardown

XPASS test_AllVHDLSources[/home/runner/work/extended-tests/extended-tests/NEORV32/rtl/core/neorv32_bootloader_image.vhd] 0:00:00.287376

Started 2021-11-23 15:22:19
Ended 2021-11-23 15:22:19
Duration 0:00:00.287376
Markers
xfail
Fixtures file

Setup

Call

Captured stdout call
================================================================================
                         pyGHDL.dom - Test Application                          
================================================================================
Parsing file '/home/runner/work/extended-tests/extended-tests/NEORV32/rtl/core/neorv32_bootloader_image.vhd'
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[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
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libghdl processing time:  2109.810 us
DOM translation time:    34022.471 us

Design:
  Libraries:
    - Name: pretty
      Entities:
      Packages:
        - neorv32_bootloader_image
      Configurations:
      Contexts:
  Documents:
    - Path: '/home/runner/work/extended-tests/extended-tests/NEORV32/rtl/core/neorv32_bootloader_image.vhd':
      Entities:
      Architectures:
      Packages:
        - Name: neorv32_bootloader_image
          File: neorv32_bootloader_image.vhd
          Position: 11:8
          Declared:
          - constant bootloader_init_image : mem32_t := (0 => None, 1 => None, 2 => None, 3 => None, 4 => None, 5 => None, 6 => None, 7 => None, 8 => None, 9 => None, 10 => None, 11 => None, 12 => None, 13 => None, 14 => None, 15 => None, 16 => None, 17 => None, 18 => None, 19 => None, 20 => None, 21 => None, 22 => None, 23 => None, 24 => None, 25 => None, 26 => None, 27 => None, 28 => None, 29 => None, 30 => None, 31 => None, 32 => None, 33 => None, 34 => None, 35 => None, 36 => None, 37 => None, 38 => None, 39 => None, 40 => None, 41 => None, 42 => None, 43 => None, 44 => None, 45 => None, 46 => None, 47 => None, 48 => None, 49 => None, 50 => None, 51 => None, 52 => None, 53 => None, 54 => None, 55 => None, 56 => None, 57 => None, 58 => None, 59 => None, 60 => None, 61 => None, 62 => None, 63 => None, 64 => None, 65 => None, 66 => None, 67 => None, 68 => None, 69 => None, 70 => None, 71 => None, 72 => None, 73 => None, 74 => None, 75 => None, 76 => None, 77 => None, 78 => None, 79 => None, 80 => None, 81 => None, 82 => None, 83 => None, 84 => None, 85 => None, 86 => None, 87 => None, 88 => None, 89 => None, 90 => None, 91 => None, 92 => None, 93 => None, 94 => None, 95 => None, 96 => None, 97 => None, 98 => None, 99 => None, 100 => None, 101 => None, 102 => None, 103 => None, 104 => None, 105 => None, 106 => None, 107 => None, 108 => None, 109 => None, 110 => None, 111 => None, 112 => None, 113 => None, 114 => None, 115 => None, 116 => None, 117 => None, 118 => None, 119 => None, 120 => None, 121 => None, 122 => None, 123 => None, 124 => None, 125 => None, 126 => None, 127 => None, 128 => None, 129 => None, 130 => None, 131 => None, 132 => None, 133 => None, 134 => None, 135 => None, 136 => None, 137 => None, 138 => None, 139 => None, 140 => None, 141 => None, 142 => None, 143 => None, 144 => None, 145 => None, 146 => None, 147 => None, 148 => None, 149 => None, 150 => None, 151 => None, 152 => None, 153 => None, 154 => None, 155 => None, 156 => None, 157 => None, 158 => None, 159 => None, 160 => None, 161 => None, 162 => None, 163 => None, 164 => None, 165 => None, 166 => None, 167 => None, 168 => None, 169 => None, 170 => None, 171 => None, 172 => None, 173 => None, 174 => None, 175 => None, 176 => None, 177 => None, 178 => None, 179 => None, 180 => None, 181 => None, 182 => None, 183 => None, 184 => None, 185 => None, 186 => None, 187 => None, 188 => None, 189 => None, 190 => None, 191 => None, 192 => None, 193 => None, 194 => None, 195 => None, 196 => None, 197 => None, 198 => None, 199 => None, 200 => None, 201 => None, 202 => None, 203 => None, 204 => None, 205 => None, 206 => None, 207 => None, 208 => None, 209 => None, 210 => None, 211 => None, 212 => None, 213 => None, 214 => None, 215 => None, 216 => None, 217 => None, 218 => None, 219 => None, 220 => None, 221 => None, 222 => None, 223 => None, 224 => None, 225 => None, 226 => None, 227 => None, 228 => None, 229 => None, 230 => None, 231 => None, 232 => None, 233 => None, 234 => None, 235 => None, 236 => None, 237 => None, 238 => None, 239 => None, 240 => None, 241 => None, 242 => None, 243 => None, 244 => None, 245 => None, 246 => None, 247 => None, 248 => None, 249 => None, 250 => None, 251 => None, 252 => None, 253 => None, 254 => None, 255 => None, 256 => None, 257 => None, 258 => None, 259 => None, 260 => None, 261 => None, 262 => None, 263 => None, 264 => None, 265 => None, 266 => None, 267 => None, 268 => None, 269 => None, 270 => None, 271 => None, 272 => None, 273 => None, 274 => None, 275 => None, 276 => None, 277 => None, 278 => None, 279 => None, 280 => None, 281 => None, 282 => None, 283 => None, 284 => None, 285 => None, 286 => None, 287 => None, 288 => None, 289 => None, 290 => None, 291 => None, 292 => None, 293 => None, 294 => None, 295 => None, 296 => None, 297 => None, 298 => None, 299 => None, 300 => None, 301 => None, 302 => None, 303 => None, 304 => None, 305 => None, 306 => None, 307 => None, 308 => None, 309 => None, 310 => None, 311 => None, 312 => None, 313 => None, 314 => None, 315 => None, 316 => None, 317 => None, 318 => None, 319 => None, 320 => None, 321 => None, 322 => None, 323 => None, 324 => None, 325 => None, 326 => None, 327 => None, 328 => None, 329 => None, 330 => None, 331 => None, 332 => None, 333 => None, 334 => None, 335 => None, 336 => None, 337 => None, 338 => None, 339 => None, 340 => None, 341 => None, 342 => None, 343 => None, 344 => None, 345 => None, 346 => None, 347 => None, 348 => None, 349 => None, 350 => None, 351 => None, 352 => None, 353 => None, 354 => None, 355 => None, 356 => None, 357 => None, 358 => None, 359 => None, 360 => None, 361 => None, 362 => None, 363 => None, 364 => None, 365 => None, 366 => None, 367 => None, 368 => None, 369 => None, 370 => None, 371 => None, 372 => None, 373 => None, 374 => None, 375 => None, 376 => None, 377 => None, 378 => None, 379 => None, 380 => None, 381 => None, 382 => None, 383 => None, 384 => None, 385 => None, 386 => None, 387 => None, 388 => None, 389 => None, 390 => None, 391 => None, 392 => None, 393 => None, 394 => None, 395 => None, 396 => None, 397 => None, 398 => None, 399 => None, 400 => None, 401 => None, 402 => None, 403 => None, 404 => None, 405 => None, 406 => None, 407 => None, 408 => None, 409 => None, 410 => None, 411 => None, 412 => None, 413 => None, 414 => None, 415 => None, 416 => None, 417 => None, 418 => None, 419 => None, 420 => None, 421 => None, 422 => None, 423 => None, 424 => None, 425 => None, 426 => None, 427 => None, 428 => None, 429 => None, 430 => None, 431 => None, 432 => None, 433 => None, 434 => None, 435 => None, 436 => None, 437 => None, 438 => None, 439 => None, 440 => None, 441 => None, 442 => None, 443 => None, 444 => None, 445 => None, 446 => None, 447 => None, 448 => None, 449 => None, 450 => None, 451 => None, 452 => None, 453 => None, 454 => None, 455 => None, 456 => None, 457 => None, 458 => None, 459 => None, 460 => None, 461 => None, 462 => None, 463 => None, 464 => None, 465 => None, 466 => None, 467 => None, 468 => None, 469 => None, 470 => None, 471 => None, 472 => None, 473 => None, 474 => None, 475 => None, 476 => None, 477 => None, 478 => None, 479 => None, 480 => None, 481 => None, 482 => None, 483 => None, 484 => None, 485 => None, 486 => None, 487 => None, 488 => None, 489 => None, 490 => None, 491 => None, 492 => None, 493 => None, 494 => None, 495 => None, 496 => None, 497 => None, 498 => None, 499 => None, 500 => None, 501 => None, 502 => None, 503 => None, 504 => None, 505 => None, 506 => None, 507 => None, 508 => None, 509 => None, 510 => None, 511 => None, 512 => None, 513 => None, 514 => None, 515 => None, 516 => None, 517 => None, 518 => None, 519 => None, 520 => None, 521 => None, 522 => None, 523 => None, 524 => None, 525 => None, 526 => None, 527 => None, 528 => None, 529 => None, 530 => None, 531 => None, 532 => None, 533 => None, 534 => None, 535 => None, 536 => None, 537 => None, 538 => None, 539 => None, 540 => None, 541 => None, 542 => None, 543 => None, 544 => None, 545 => None, 546 => None, 547 => None, 548 => None, 549 => None, 550 => None, 551 => None, 552 => None, 553 => None, 554 => None, 555 => None, 556 => None, 557 => None, 558 => None, 559 => None, 560 => None, 561 => None, 562 => None, 563 => None, 564 => None, 565 => None, 566 => None, 567 => None, 568 => None, 569 => None, 570 => None, 571 => None, 572 => None, 573 => None, 574 => None, 575 => None, 576 => None, 577 => None, 578 => None, 579 => None, 580 => None, 581 => None, 582 => None, 583 => None, 584 => None, 585 => None, 586 => None, 587 => None, 588 => None, 589 => None, 590 => None, 591 => None, 592 => None, 593 => None, 594 => None, 595 => None, 596 => None, 597 => None, 598 => None, 599 => None, 600 => None, 601 => None, 602 => None, 603 => None, 604 => None, 605 => None, 606 => None, 607 => None, 608 => None, 609 => None, 610 => None, 611 => None, 612 => None, 613 => None, 614 => None, 615 => None, 616 => None, 617 => None, 618 => None, 619 => None, 620 => None, 621 => None, 622 => None, 623 => None, 624 => None, 625 => None, 626 => None, 627 => None, 628 => None, 629 => None, 630 => None, 631 => None, 632 => None, 633 => None, 634 => None, 635 => None, 636 => None, 637 => None, 638 => None, 639 => None, 640 => None, 641 => None, 642 => None, 643 => None, 644 => None, 645 => None, 646 => None, 647 => None, 648 => None, 649 => None, 650 => None, 651 => None, 652 => None, 653 => None, 654 => None, 655 => None, 656 => None, 657 => None, 658 => None, 659 => None, 660 => None, 661 => None, 662 => None, 663 => None, 664 => None, 665 => None, 666 => None, 667 => None, 668 => None, 669 => None, 670 => None, 671 => None, 672 => None, 673 => None, 674 => None, 675 => None, 676 => None, 677 => None, 678 => None, 679 => None, 680 => None, 681 => None, 682 => None, 683 => None, 684 => None, 685 => None, 686 => None, 687 => None, 688 => None, 689 => None, 690 => None, 691 => None, 692 => None, 693 => None, 694 => None, 695 => None, 696 => None, 697 => None, 698 => None, 699 => None, 700 => None, 701 => None, 702 => None, 703 => None, 704 => None, 705 => None, 706 => None, 707 => None, 708 => None, 709 => None, 710 => None, 711 => None, 712 => None, 713 => None, 714 => None, 715 => None, 716 => None, 717 => None, 718 => None, 719 => None, 720 => None, 721 => None, 722 => None, 723 => None, 724 => None, 725 => None, 726 => None, 727 => None, 728 => None, 729 => None, 730 => None, 731 => None, 732 => None, 733 => None, 734 => None, 735 => None, 736 => None, 737 => None, 738 => None, 739 => None, 740 => None, 741 => None, 742 => None, 743 => None, 744 => None, 745 => None, 746 => None, 747 => None, 748 => None, 749 => None, 750 => None, 751 => None, 752 => None, 753 => None, 754 => None, 755 => None, 756 => None, 757 => None, 758 => None, 759 => None, 760 => None, 761 => None, 762 => None, 763 => None, 764 => None, 765 => None, 766 => None, 767 => None, 768 => None, 769 => None, 770 => None, 771 => None, 772 => None, 773 => None, 774 => None, 775 => None, 776 => None, 777 => None, 778 => None, 779 => None, 780 => None, 781 => None, 782 => None, 783 => None, 784 => None, 785 => None, 786 => None, 787 => None, 788 => None, 789 => None, 790 => None, 791 => None, 792 => None, 793 => None, 794 => None, 795 => None, 796 => None, 797 => None, 798 => None, 799 => None, 800 => None, 801 => None, 802 => None, 803 => None, 804 => None, 805 => None, 806 => None, 807 => None, 808 => None, 809 => None, 810 => None, 811 => None, 812 => None, 813 => None, 814 => None, 815 => None, 816 => None, 817 => None, 818 => None, 819 => None, 820 => None, 821 => None, 822 => None, 823 => None, 824 => None, 825 => None, 826 => None, 827 => None, 828 => None, 829 => None, 830 => None, 831 => None, 832 => None, 833 => None, 834 => None, 835 => None, 836 => None, 837 => None, 838 => None, 839 => None, 840 => None, 841 => None, 842 => None, 843 => None, 844 => None, 845 => None, 846 => None, 847 => None, 848 => None, 849 => None, 850 => None, 851 => None, 852 => None, 853 => None, 854 => None, 855 => None, 856 => None, 857 => None, 858 => None, 859 => None, 860 => None, 861 => None, 862 => None, 863 => None, 864 => None, 865 => None, 866 => None, 867 => None, 868 => None, 869 => None, 870 => None, 871 => None, 872 => None, 873 => None, 874 => None, 875 => None, 876 => None, 877 => None, 878 => None, 879 => None, 880 => None, 881 => None, 882 => None, 883 => None, 884 => None, 885 => None, 886 => None, 887 => None, 888 => None, 889 => None, 890 => None, 891 => None, 892 => None, 893 => None, 894 => None, 895 => None, 896 => None, 897 => None, 898 => None, 899 => None, 900 => None, 901 => None, 902 => None, 903 => None, 904 => None, 905 => None, 906 => None, 907 => None, 908 => None, 909 => None, 910 => None, 911 => None, 912 => None, 913 => None, 914 => None, 915 => None, 916 => None, 917 => None, 918 => None, 919 => None, 920 => None, 921 => None, 922 => None, 923 => None, 924 => None, 925 => None, 926 => None, 927 => None, 928 => None, 929 => None, 930 => None, 931 => None, 932 => None, 933 => None, 934 => None, 935 => None, 936 => None, 937 => None, 938 => None, 939 => None, 940 => None, 941 => None, 942 => None, 943 => None, 944 => None, 945 => None, 946 => None, 947 => None, 948 => None, 949 => None, 950 => None, 951 => None, 952 => None, 953 => None, 954 => None, 955 => None, 956 => None, 957 => None, 958 => None, 959 => None, 960 => None, 961 => None, 962 => None, 963 => None, 964 => None, 965 => None, 966 => None, 967 => None, 968 => None, 969 => None, 970 => None, 971 => None, 972 => None, 973 => None, 974 => None, 975 => None, 976 => None, 977 => None, 978 => None, 979 => None, 980 => None, 981 => None, 982 => None, 983 => None, 984 => None, 985 => None, 986 => None, 987 => None, 988 => None, 989 => None, 990 => None, 991 => None, 992 => None, 993 => None, 994 => None, 995 => None, 996 => None, 997 => None, 998 => None, 999 => None, 1000 => None, 1001 => None, 1002 => None, 1003 => None, 1004 => None, 1005 => None, 1006 => None, 1007 => None, 1008 => None, 1009 => None, 1010 => None, 1011 => None, 1012 => None, 1013 => None, 1014 => None, 1015 => None, 1016 => None)
      PackageBodies:
      Configurations:
      Contexts:

Teardown

XPASS test_AllVHDLSources[/home/runner/work/extended-tests/extended-tests/NEORV32/rtl/core/neorv32_twi.vhd] 0:00:00.263946

Started 2021-11-23 15:22:19
Ended 2021-11-23 15:22:19
Duration 0:00:00.263946
Markers
xfail
Fixtures file

Setup

Call

Captured stdout call
================================================================================
                         pyGHDL.dom - Test Application                          
================================================================================
Parsing file '/home/runner/work/extended-tests/extended-tests/NEORV32/rtl/core/neorv32_twi.vhd'
[NOT IMPLEMENTED] Concurrent (conditional) signal assignment (label: 'None') at line 126
[NOT IMPLEMENTED] Concurrent (conditional) signal assignment (label: 'None') at line 284
[NOT IMPLEMENTED] Concurrent (conditional) signal assignment (label: 'None') at line 290
[NOT IMPLEMENTED] Concurrent (conditional) signal assignment (label: 'None') at line 291
[NOT IMPLEMENTED] Concurrent (conditional) signal assignment (label: 'None') at line 319
libghdl processing time:  747.804 us
DOM translation time:    11086.556 us

Design:
  Libraries:
    - Name: pretty
      Entities:
        - neorv32_twi(neorv32_twi_rtl)
      Packages:
      Configurations:
      Contexts:
  Documents:
    - Path: '/home/runner/work/extended-tests/extended-tests/NEORV32/rtl/core/neorv32_twi.vhd':
      Entities:
        - Name: neorv32_twi
          File: neorv32_twi.vhd
          Position: 46:7
          Generics:
          Ports:
            - clk_i : in std_ulogic
            - addr_i : in std_ulogic_vector(31 downto 0)
            - rden_i : in std_ulogic
            - wren_i : in std_ulogic
            - data_i : in std_ulogic_vector(31 downto 0)
            - data_o : out std_ulogic_vector(31 downto 0)
            - ack_o : out std_ulogic
            - clkgen_en_o : out std_ulogic
            - clkgen_i : in std_ulogic_vector(7 downto 0)
            - twi_sda_io : inout std_logic
            - twi_scl_io : inout std_logic
            - irq_o : out std_ulogic
          Declared:
          Statements:
          Architecures:
          - neorv32_twi_rtl
      Architectures:
        - Name: neorv32_twi_rtl
          File: neorv32_twi.vhd
          Position: 67:13
          Entity: neorv32_twi
          Declared:
            - constant hi_abb_c : natural := index_size_f(io_size_c) - 1
            - constant lo_abb_c : natural := index_size_f(twi_size_c)
            - constant ctrl_en_c : natural := 0
            - constant ctrl_start_c : natural := 1
            - constant ctrl_stop_c : natural := 2
            - constant ctrl_prsc0_c : natural := 3
            - constant ctrl_prsc1_c : natural := 4
            - constant ctrl_prsc2_c : natural := 5
            - constant ctrl_mack_c : natural := 6
            - constant ctrl_ack_c : natural := 30
            - constant ctrl_busy_c : natural := 31
            - signal ctrl : std_ulogic_vector(6 downto 0)
            - signal acc_en : std_ulogic
            - signal addr : std_ulogic_vector(31 downto 0)
            - signal wren : std_ulogic
            - signal rden : std_ulogic
            - signal twi_clk : std_ulogic
            - signal twi_phase_gen : std_ulogic_vector(3 downto 0)
            - signal twi_clk_phase : std_ulogic_vector(3 downto 0)
            - signal twi_clk_halt : std_ulogic
            - signal arbiter : std_ulogic_vector(2 downto 0)
            - signal bitcnt : std_ulogic_vector(3 downto 0)
            - signal rtx_sreg : std_ulogic_vector(8 downto 0)
            - signal twi_sda_in_ff : std_ulogic_vector(1 downto 0)
            - signal twi_scl_in_ff : std_ulogic_vector(1 downto 0)
            - signal twi_sda_in : std_ulogic
            - signal twi_scl_in : std_ulogic
            - signal twi_sda_out : std_ulogic
            - signal twi_scl_out : std_ulogic
            - type irq_t is record ..... end record
            - signal irq : irq_t
          Hierarchy:
            - rw_access: process(...)
            - clock_phase_gen: process(...)
            - twi_rtx_unit: process(...)
            - irq_generator: process(...)
          Statements:
            ...
            ...
            ...
            ...
            ...
            ...
            ...
            ...
            ...
            ...
            ...
            ...
            ...
            ...
            ...
            ...
      Packages:
      PackageBodies:
      Configurations:
      Contexts:

Teardown

XPASS test_AllVHDLSources[/home/runner/work/extended-tests/extended-tests/NEORV32/rtl/core/neorv32_cpu_control.vhd] 0:00:00.469848

Started 2021-11-23 15:22:19
Ended 2021-11-23 15:22:19
Duration 0:00:00.469848
Markers
xfail
Fixtures file

Setup

Call

Captured stdout call
================================================================================
                         pyGHDL.dom - Test Application                          
================================================================================
Parsing file '/home/runner/work/extended-tests/extended-tests/NEORV32/rtl/core/neorv32_cpu_control.vhd'
[NOT IMPLEMENTED] Array_Subtype_Definition
[NOT IMPLEMENTED] Array_Subtype_Definition
[NOT IMPLEMENTED] Array_Subtype_Definition
[NOT IMPLEMENTED] Array_Subtype_Definition
[NOT IMPLEMENTED] Array_Subtype_Definition
[NOT IMPLEMENTED] Array_Subtype_Definition
[NOT IMPLEMENTED] Array_Subtype_Definition
[NOT IMPLEMENTED] Array_Subtype_Definition
[NOT IMPLEMENTED] Concurrent (conditional) signal assignment (label: 'None') at line 588
[NOT IMPLEMENTED] Variable assignment (label: 'None') at line 630
[NOT IMPLEMENTED] Concurrent (conditional) signal assignment (label: 'None') at line 764
[NOT IMPLEMENTED] Variable assignment (label: 'None') at line 888
[NOT IMPLEMENTED] Variable assignment (label: 'None') at line 1018
[NOT IMPLEMENTED] Variable assignment (label: 'None') at line 1280
[NOT IMPLEMENTED] Variable assignment (label: 'None') at line 1283
[NOT IMPLEMENTED] Variable assignment (label: 'None') at line 1387
[NOT IMPLEMENTED] Concurrent (conditional) signal assignment (label: 'None') at line 1661
[NOT IMPLEMENTED] Concurrent (conditional) signal assignment (label: 'None') at line 1662
[NOT IMPLEMENTED] Variable assignment (label: 'None') at line 1843
[NOT IMPLEMENTED] Variable assignment (label: 'None') at line 1844
[NOT IMPLEMENTED] Variable assignment (label: 'None') at line 1846
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Variable assignment (label: 'None') at line 2099
[NOT IMPLEMENTED] Variable assignment (label: 'None') at line 2100
[NOT IMPLEMENTED] Concurrent (conditional) signal assignment (label: 'None') at line 2225
[NOT IMPLEMENTED] Concurrent (conditional) signal assignment (label: 'None') at line 2226
[NOT IMPLEMENTED] Concurrent (conditional) signal assignment (label: 'None') at line 2227
[NOT IMPLEMENTED] Concurrent (conditional) signal assignment (label: 'None') at line 2405
[NOT IMPLEMENTED] Concurrent (conditional) signal assignment (label: 'None') at line 2408
[NOT IMPLEMENTED] Concurrent (conditional) signal assignment (label: 'None') at line 2409
[NOT IMPLEMENTED] Concurrent (conditional) signal assignment (label: 'None') at line 2410
[NOT IMPLEMENTED] Concurrent (conditional) signal assignment (label: 'None') at line 2411
[NOT IMPLEMENTED] Concurrent (conditional) signal assignment (label: 'None') at line 2413
[NOT IMPLEMENTED] Concurrent (conditional) signal assignment (label: 'None') at line 2414
[NOT IMPLEMENTED] Concurrent (conditional) signal assignment (label: 'None') at line 2415
[NOT IMPLEMENTED] Concurrent (conditional) signal assignment (label: 'None') at line 2417
[NOT IMPLEMENTED] Concurrent (conditional) signal assignment (label: 'None') at line 2418
[NOT IMPLEMENTED] Concurrent (conditional) signal assignment (label: 'None') at line 2419
[NOT IMPLEMENTED] Concurrent (conditional) signal assignment (label: 'None') at line 2421
[NOT IMPLEMENTED] Concurrent (conditional) signal assignment (label: 'None') at line 2422
[NOT IMPLEMENTED] Variable assignment (label: 'None') at line 2433
[NOT IMPLEMENTED] Variable assignment (label: 'None') at line 2434
[NOT IMPLEMENTED] Variable assignment (label: 'None') at line 2435
[NOT IMPLEMENTED] Concurrent (conditional) signal assignment (label: 'None') at line 2787
[NOT IMPLEMENTED] Concurrent (conditional) signal assignment (label: 'None') at line 2788
[NOT IMPLEMENTED] Concurrent (conditional) signal assignment (label: 'None') at line 2812
libghdl processing time:  8193.441 us
DOM translation time:    189526.152 us

Design:
  Libraries:
    - Name: pretty
      Entities:
        - neorv32_cpu_control(neorv32_cpu_control_rtl)
      Packages:
      Configurations:
      Contexts:
  Documents:
    - Path: '/home/runner/work/extended-tests/extended-tests/NEORV32/rtl/core/neorv32_cpu_control.vhd':
      Entities:
        - Name: neorv32_cpu_control
          File: neorv32_cpu_control.vhd
          Position: 48:7
          Generics:
            - HW_THREAD_ID : in natural
            - CPU_BOOT_ADDR : in std_ulogic_vector(31 downto 0)
            - CPU_DEBUG_ADDR : in std_ulogic_vector(31 downto 0)
            - CPU_EXTENSION_RISCV_A : in boolean
            - CPU_EXTENSION_RISCV_B : in boolean
            - CPU_EXTENSION_RISCV_C : in boolean
            - CPU_EXTENSION_RISCV_E : in boolean
            - CPU_EXTENSION_RISCV_M : in boolean
            - CPU_EXTENSION_RISCV_U : in boolean
            - CPU_EXTENSION_RISCV_Zfinx : in boolean
            - CPU_EXTENSION_RISCV_Zicsr : in boolean
            - CPU_EXTENSION_RISCV_Zicntr : in boolean
            - CPU_EXTENSION_RISCV_Zihpm : in boolean
            - CPU_EXTENSION_RISCV_Zifencei : in boolean
            - CPU_EXTENSION_RISCV_Zmmul : in boolean
            - CPU_EXTENSION_RISCV_DEBUG : in boolean
            - CPU_CNT_WIDTH : in natural
            - CPU_IPB_ENTRIES : in natural
            - PMP_NUM_REGIONS : in natural
            - PMP_MIN_GRANULARITY : in natural
            - HPM_NUM_CNTS : in natural
            - HPM_CNT_WIDTH : in natural
          Ports:
            - clk_i : in std_ulogic
            - rstn_i : in std_ulogic
            - ctrl_o : out std_ulogic_vector(ctrl_width_c - 1 downto 0)
            - alu_idone_i : in std_ulogic
            - bus_i_wait_i : in std_ulogic
            - bus_d_wait_i : in std_ulogic
            - excl_state_i : in std_ulogic
            - instr_i : in std_ulogic_vector(data_width_c - 1 downto 0)
            - cmp_i : in std_ulogic_vector(1 downto 0)
            - alu_add_i : in std_ulogic_vector(data_width_c - 1 downto 0)
            - rs1_i : in std_ulogic_vector(data_width_c - 1 downto 0)
            - imm_o : out std_ulogic_vector(data_width_c - 1 downto 0)
            - fetch_pc_o : out std_ulogic_vector(data_width_c - 1 downto 0)
            - curr_pc_o : out std_ulogic_vector(data_width_c - 1 downto 0)
            - next_pc_o : out std_ulogic_vector(data_width_c - 1 downto 0)
            - csr_rdata_o : out std_ulogic_vector(data_width_c - 1 downto 0)
            - fpu_flags_i : in std_ulogic_vector(4 downto 0)
            - db_halt_req_i : in std_ulogic
            - msw_irq_i : in std_ulogic
            - mext_irq_i : in std_ulogic
            - mtime_irq_i : in std_ulogic
            - firq_i : in std_ulogic_vector(15 downto 0)
            - time_i : in std_ulogic_vector(63 downto 0)
            - pmp_addr_o : out pmp_addr_if_t
            - pmp_ctrl_o : out pmp_ctrl_if_t
            - mar_i : in std_ulogic_vector(data_width_c - 1 downto 0)
            - ma_instr_i : in std_ulogic
            - ma_load_i : in std_ulogic
            - ma_store_i : in std_ulogic
            - be_instr_i : in std_ulogic
            - be_load_i : in std_ulogic
            - be_store_i : in std_ulogic
          Declared:
          Statements:
          Architecures:
          - neorv32_cpu_control_rtl
      Architectures:
        - Name: neorv32_cpu_control_rtl
          File: neorv32_cpu_control.vhd
          Position: 125:13
          Entity: neorv32_cpu_control
          Declared:
            - constant cpu_cnt_lo_width_c : natural := natural(cond_sel_int_f(boolean(CPU_CNT_WIDTH < 32), CPU_CNT_WIDTH, 32))
            - constant cpu_cnt_hi_width_c : natural := natural(cond_sel_int_f(boolean(CPU_CNT_WIDTH > 32), CPU_CNT_WIDTH - 32, 0))
            - constant hpm_cnt_lo_width_c : natural := natural(cond_sel_int_f(boolean(HPM_CNT_WIDTH < 32), HPM_CNT_WIDTH, 32))
            - constant hpm_cnt_hi_width_c : natural := natural(cond_sel_int_f(boolean(HPM_CNT_WIDTH > 32), HPM_CNT_WIDTH - 32, 0))
            - type fetch_engine_state_t is (........)
            - type fetch_engine_t is record ..... end record
            - signal fetch_engine : fetch_engine_t
            - type ipb_t is record ..... end record
            - signal ipb : ipb_t
            - signal ci_instr16 : std_ulogic_vector(15 downto 0)
            - signal ci_instr32 : std_ulogic_vector(31 downto 0)
            - signal ci_illegal : std_ulogic
            - type issue_engine_state_t is (........)
            - type issue_engine_t is record ..... end record
            - signal issue_engine : issue_engine_t
            - type cmd_issue_t is record ..... end record
            - signal cmd_issue : cmd_issue_t
            - type decode_aux_t is record ..... end record
            - signal decode_aux : decode_aux_t
            - type execute_engine_state_t is (........)
            - type execute_engine_t is record ..... end record
            - signal execute_engine : execute_engine_t
            - type trap_ctrl_t is record ..... end record
            - signal trap_ctrl : trap_ctrl_t
            - signal ctrl_nxt, ctrl : std_ulogic_vector(ctrl_width_c - 1 downto 0)
            - signal bus_fast_ir : std_ulogic
            - type ???? is array(........) of .....
            - type ???? is array(........) of .....
            - type ???? is array(........) of .....
            - type ???? is array(........) of .....
            - type ???? is array(........) of .....
            - type ???? is array(........) of .....
            - type ???? is array(........) of .....
            - type ???? is array(........) of .....
            - type csr_t is record ..... end record
            - signal csr : csr_t
            - type debug_ctrl_state_t is (........)
            - type debug_ctrl_t is record ..... end record
            - signal debug_ctrl : debug_ctrl_t
            - signal cnt_event : std_ulogic_vector(hpmcnt_event_size_c - 1 downto 0)
            - signal hpmcnt_trigger : std_ulogic_vector(HPM_NUM_CNTS - 1 downto 0)
            - signal illegal_opcode_lsbs : std_ulogic
            - signal illegal_instruction : std_ulogic
            - signal illegal_register : std_ulogic
            - signal illegal_compressed : std_ulogic
            - signal csr_acc_valid : std_ulogic
          Hierarchy:
            - fetch_engine_fsm_sync: process(...)
            - fetch_engine_fsm_comb: process(...)
            - instr_prefetch_buffer: component neorv32_fifo
            - issue_engine_fsm_sync: process(...)
            - issue_engine_fsm_comb: process(...)
            - neorv32_cpu_decompressor_inst_true: if (CPU_EXTENSION_RISCV_C = true) generate
                - neorv32_cpu_decompressor_inst: component neorv32_cpu_decompressor
            - neorv32_cpu_decompressor_inst_false: if (CPU_EXTENSION_RISCV_C = false) generate
            - imm_gen: process(...)
            - branch_check: process(...)
            - execute_engine_fsm_sync: process(...)
            - ctrl_output: process(...)
            - decode_helper: process(...)
            - execute_engine_fsm_comb: process(...)
            - csr_access_check: process(...)
            - illegal_instruction_check: process(...)
            - trap_controller: process(...)
            - trap_priority: process(...)
            - csr_write_data: process(...)
            - csr_write_access: process(...)
            - pmp_output: process(...)
            - pmp_rd_dummy: process(...)
            - csr_counters: process(...)
            - hmp_cnt_lo_inc: for i in 0 to HPM_NUM_CNTS - 1 generate
            - hpm_rd_dummy: process(...)
            - hpmcnt_ctrl: process(...)
            - csr_read_access: process(...)
            - debug_control: process(...)
            - dcsr_readback_false: if (CPU_EXTENSION_RISCV_DEBUG = false) generate
            - dcsr_readback_true: if (CPU_EXTENSION_RISCV_DEBUG = true) generate
          Statements:
            ...
            ...
            ...
            ...
            ...
            ...
            ...
            ...
            ...
            ...
            ...
            ...
            ...
            ...
            ...
            ...
            ...
            ...
            ...
            ...
            ...
            ...
            ...
            ...
            ...
            ...
            ...
            ...
            ...
            ...
            ...
            ...
            ...
            ...
            ...
            ...
            ...
            ...
            ...
            ...
            ...
            ...
            ...
            ...
      Packages:
      PackageBodies:
      Configurations:
      Contexts:

Teardown

XPASS test_AllVHDLSources[/home/runner/work/extended-tests/extended-tests/NEORV32/rtl/core/neorv32_neoled.vhd] 0:00:00.273400

Started 2021-11-23 15:22:19
Ended 2021-11-23 15:22:20
Duration 0:00:00.273400
Markers
xfail
Fixtures file

Setup

Call

Captured stdout call
================================================================================
                         pyGHDL.dom - Test Application                          
================================================================================
Parsing file '/home/runner/work/extended-tests/extended-tests/NEORV32/rtl/core/neorv32_neoled.vhd'
[NOT IMPLEMENTED] Concurrent (conditional) signal assignment (label: 'None') at line 195
[NOT IMPLEMENTED] Concurrent (conditional) signal assignment (label: 'None') at line 246
[NOT IMPLEMENTED] Concurrent (conditional) signal assignment (label: 'None') at line 286
[NOT IMPLEMENTED] Concurrent (conditional) signal assignment (label: 'None') at line 316
[NOT IMPLEMENTED] Concurrent (conditional) signal assignment (label: 'None') at line 426
[NOT IMPLEMENTED] Concurrent (conditional) signal assignment (label: 'None') at line 429
libghdl processing time:  832.904 us
DOM translation time:    14257.971 us

Design:
  Libraries:
    - Name: pretty
      Entities:
        - neorv32_neoled(neorv32_neoled_rtl)
      Packages:
      Configurations:
      Contexts:
  Documents:
    - Path: '/home/runner/work/extended-tests/extended-tests/NEORV32/rtl/core/neorv32_neoled.vhd':
      Entities:
        - Name: neorv32_neoled
          File: neorv32_neoled.vhd
          Position: 56:7
          Generics:
            - FIFO_DEPTH : in natural
          Ports:
            - clk_i : in std_ulogic
            - addr_i : in std_ulogic_vector(31 downto 0)
            - rden_i : in std_ulogic
            - wren_i : in std_ulogic
            - data_i : in std_ulogic_vector(31 downto 0)
            - data_o : out std_ulogic_vector(31 downto 0)
            - ack_o : out std_ulogic
            - clkgen_en_o : out std_ulogic
            - clkgen_i : in std_ulogic_vector(7 downto 0)
            - irq_o : out std_ulogic
            - neoled_o : out std_ulogic
          Declared:
          Statements:
          Architecures:
          - neorv32_neoled_rtl
      Architectures:
        - Name: neorv32_neoled_rtl
          File: neorv32_neoled.vhd
          Position: 79:13
          Entity: neorv32_neoled
          Declared:
            - constant hi_abb_c : natural := index_size_f(io_size_c) - 1
            - constant lo_abb_c : natural := index_size_f(neoled_size_c)
            - signal acc_en : std_ulogic
            - signal addr : std_ulogic_vector(31 downto 0)
            - signal wren : std_ulogic
            - signal rden : std_ulogic
            - constant ctrl_en_c : natural := 0
            - constant ctrl_mode_c : natural := 1
            - constant ctrl_strobe_c : natural := 2
            - constant ctrl_clksel0_c : natural := 3
            - constant ctrl_clksel1_c : natural := 4
            - constant ctrl_clksel2_c : natural := 5
            - constant ctrl_bufs_0_c : natural := 6
            - constant ctrl_bufs_1_c : natural := 7
            - constant ctrl_bufs_2_c : natural := 8
            - constant ctrl_bufs_3_c : natural := 9
            - constant ctrl_t_tot_0_c : natural := 10
            - constant ctrl_t_tot_1_c : natural := 11
            - constant ctrl_t_tot_2_c : natural := 12
            - constant ctrl_t_tot_3_c : natural := 13
            - constant ctrl_t_tot_4_c : natural := 14
            - constant ctrl_t_0h_0_c : natural := 15
            - constant ctrl_t_0h_1_c : natural := 16
            - constant ctrl_t_0h_2_c : natural := 17
            - constant ctrl_t_0h_3_c : natural := 18
            - constant ctrl_t_0h_4_c : natural := 19
            - constant ctrl_t_1h_0_c : natural := 20
            - constant ctrl_t_1h_1_c : natural := 21
            - constant ctrl_t_1h_2_c : natural := 22
            - constant ctrl_t_1h_3_c : natural := 23
            - constant ctrl_t_1h_4_c : natural := 24
            - constant ctrl_irq_conf_c : natural := 27
            - constant ctrl_tx_empty_c : natural := 28
            - constant ctrl_tx_half_c : natural := 29
            - constant ctrl_tx_full_c : natural := 30
            - constant ctrl_tx_busy_c : natural := 31
            - type ctrl_t is record ..... end record
            - signal ctrl : ctrl_t
            - type tx_buffer_t is record ..... end record
            - signal tx_buffer : tx_buffer_t
            - type irq_t is record ..... end record
            - signal irq : irq_t
            - type serial_state_t is (........)
            - type serial_t is record ..... end record
            - signal serial : serial_t
          Hierarchy:
            - rw_access: process(...)
            - irq_select: process(...)
            - irq_generator: process(...)
            - tx_data_fifo: component neorv32_fifo
            - serial_engine: process(...)
          Statements:
            ...
            ...
            ...
            ...
            ...
            ...
            ...
            ...
            ...
            ...
            ...
            ...
            ...
      Packages:
      PackageBodies:
      Configurations:
      Contexts:

Teardown

XPASS test_AllVHDLSources[/home/runner/work/extended-tests/extended-tests/NEORV32/rtl/core/neorv32_busswitch.vhd] 0:00:00.268773

Started 2021-11-23 15:22:19
Ended 2021-11-23 15:22:20
Duration 0:00:00.268773
Markers
xfail
Fixtures file

Setup

Call

Captured stdout call
================================================================================
                         pyGHDL.dom - Test Application                          
================================================================================
Parsing file '/home/runner/work/extended-tests/extended-tests/NEORV32/rtl/core/neorv32_busswitch.vhd'
[NOT IMPLEMENTED] Concurrent (conditional) signal assignment (label: 'None') at line 149
[NOT IMPLEMENTED] Concurrent (conditional) signal assignment (label: 'None') at line 150
[NOT IMPLEMENTED] Concurrent (conditional) signal assignment (label: 'None') at line 153
[NOT IMPLEMENTED] Concurrent (conditional) signal assignment (label: 'None') at line 154
[NOT IMPLEMENTED] Concurrent (conditional) signal assignment (label: 'None') at line 248
[NOT IMPLEMENTED] Concurrent (conditional) signal assignment (label: 'None') at line 249
[NOT IMPLEMENTED] Concurrent (conditional) signal assignment (label: 'None') at line 251
[NOT IMPLEMENTED] Concurrent (conditional) signal assignment (label: 'None') at line 253
[NOT IMPLEMENTED] Concurrent (conditional) signal assignment (label: 'None') at line 254
libghdl processing time:  553.303 us
DOM translation time:    9123.246 us

Design:
  Libraries:
    - Name: pretty
      Entities:
        - neorv32_busswitch(neorv32_busswitch_rtl)
      Packages:
      Configurations:
      Contexts:
  Documents:
    - Path: '/home/runner/work/extended-tests/extended-tests/NEORV32/rtl/core/neorv32_busswitch.vhd':
      Entities:
        - Name: neorv32_busswitch
          File: neorv32_busswitch.vhd
          Position: 45:7
          Generics:
            - PORT_CA_READ_ONLY : in boolean
            - PORT_CB_READ_ONLY : in boolean
          Ports:
            - clk_i : in std_ulogic
            - rstn_i : in std_ulogic
            - ca_bus_addr_i : in std_ulogic_vector(data_width_c - 1 downto 0)
            - ca_bus_rdata_o : out std_ulogic_vector(data_width_c - 1 downto 0)
            - ca_bus_wdata_i : in std_ulogic_vector(data_width_c - 1 downto 0)
            - ca_bus_ben_i : in std_ulogic_vector(3 downto 0)
            - ca_bus_we_i : in std_ulogic
            - ca_bus_re_i : in std_ulogic
            - ca_bus_lock_i : in std_ulogic
            - ca_bus_ack_o : out std_ulogic
            - ca_bus_err_o : out std_ulogic
            - cb_bus_addr_i : in std_ulogic_vector(data_width_c - 1 downto 0)
            - cb_bus_rdata_o : out std_ulogic_vector(data_width_c - 1 downto 0)
            - cb_bus_wdata_i : in std_ulogic_vector(data_width_c - 1 downto 0)
            - cb_bus_ben_i : in std_ulogic_vector(3 downto 0)
            - cb_bus_we_i : in std_ulogic
            - cb_bus_re_i : in std_ulogic
            - cb_bus_lock_i : in std_ulogic
            - cb_bus_ack_o : out std_ulogic
            - cb_bus_err_o : out std_ulogic
            - p_bus_src_o : out std_ulogic
            - p_bus_addr_o : out std_ulogic_vector(data_width_c - 1 downto 0)
            - p_bus_rdata_i : in std_ulogic_vector(data_width_c - 1 downto 0)
            - p_bus_wdata_o : out std_ulogic_vector(data_width_c - 1 downto 0)
            - p_bus_ben_o : out std_ulogic_vector(3 downto 0)
            - p_bus_we_o : out std_ulogic
            - p_bus_re_o : out std_ulogic
            - p_bus_lock_o : out std_ulogic
            - p_bus_ack_i : in std_ulogic
            - p_bus_err_i : in std_ulogic
          Declared:
          Statements:
          Architecures:
          - neorv32_busswitch_rtl
      Architectures:
        - Name: neorv32_busswitch_rtl
          File: neorv32_busswitch.vhd
          Position: 88:13
          Entity: neorv32_busswitch
          Declared:
            - signal ca_rd_req_buf, ca_wr_req_buf : std_ulogic
            - signal cb_rd_req_buf, cb_wr_req_buf : std_ulogic
            - signal ca_req_current, ca_req_buffered : std_ulogic
            - signal cb_req_current, cb_req_buffered : std_ulogic
            - signal ca_bus_ack, cb_bus_ack : std_ulogic
            - signal ca_bus_err, cb_bus_err : std_ulogic
            - signal p_bus_we, p_bus_re : std_ulogic
            - type arbiter_state_t is (........)
            - type arbiter_t is record ..... end record
            - signal arbiter : arbiter_t
          Hierarchy:
            - access_buffer: process(...)
            - arbiter_sync: process(...)
            - arbiter_comb: process(...)
          Statements:
            ...
            ...
            ...
            ...
            ...
            ...
            ...
            ...
            ...
            ...
            ...
            ...
            ...
            ...
            ...
            ...
      Packages:
      PackageBodies:
      Configurations:
      Contexts:

Teardown

XPASS test_AllVHDLSources[/home/runner/work/extended-tests/extended-tests/NEORV32/rtl/core/neorv32_xirq.vhd] 0:00:00.260980

Started 2021-11-23 15:22:20
Ended 2021-11-23 15:22:20
Duration 0:00:00.260980
Markers
xfail
Fixtures file

Setup

Call

Captured stdout call
================================================================================
                         pyGHDL.dom - Test Application                          
================================================================================
Parsing file '/home/runner/work/extended-tests/extended-tests/NEORV32/rtl/core/neorv32_xirq.vhd'
[NOT IMPLEMENTED] Concurrent (conditional) signal assignment (label: 'None') at line 112
libghdl processing time:  440.803 us
DOM translation time:    6347.731 us

Design:
  Libraries:
    - Name: pretty
      Entities:
        - neorv32_xirq(neorv32_xirq_rtl)
      Packages:
      Configurations:
      Contexts:
  Documents:
    - Path: '/home/runner/work/extended-tests/extended-tests/NEORV32/rtl/core/neorv32_xirq.vhd':
      Entities:
        - Name: neorv32_xirq
          File: neorv32_xirq.vhd
          Position: 49:7
          Generics:
            - XIRQ_NUM_CH : in natural
            - XIRQ_TRIGGER_TYPE : in std_ulogic_vector(31 downto 0)
            - XIRQ_TRIGGER_POLARITY : in std_ulogic_vector(31 downto 0)
          Ports:
            - clk_i : in std_ulogic
            - addr_i : in std_ulogic_vector(31 downto 0)
            - rden_i : in std_ulogic
            - wren_i : in std_ulogic
            - data_i : in std_ulogic_vector(31 downto 0)
            - data_o : out std_ulogic_vector(31 downto 0)
            - ack_o : out std_ulogic
            - xirq_i : in std_ulogic_vector(XIRQ_NUM_CH - 1 downto 0)
            - cpu_irq_o : out std_ulogic
          Declared:
          Statements:
          Architecures:
          - neorv32_xirq_rtl
      Architectures:
        - Name: neorv32_xirq_rtl
          File: neorv32_xirq.vhd
          Position: 71:13
          Entity: neorv32_xirq
          Declared:
            - constant hi_abb_c : natural := index_size_f(io_size_c) - 1
            - constant lo_abb_c : natural := index_size_f(xirq_size_c)
            - signal acc_en : std_ulogic
            - signal addr : std_ulogic_vector(31 downto 0)
            - signal wren : std_ulogic
            - signal rden : std_ulogic
            - signal irq_enable : std_ulogic_vector(XIRQ_NUM_CH - 1 downto 0)
            - signal clr_pending : std_ulogic_vector(XIRQ_NUM_CH - 1 downto 0)
            - signal irq_src : std_ulogic_vector(4 downto 0)
            - signal irq_sync : std_ulogic_vector(XIRQ_NUM_CH - 1 downto 0)
            - signal irq_sync2 : std_ulogic_vector(XIRQ_NUM_CH - 1 downto 0)
            - signal irq_trig : std_ulogic_vector(XIRQ_NUM_CH - 1 downto 0)
            - signal irq_buf : std_ulogic_vector(XIRQ_NUM_CH - 1 downto 0)
            - signal irq_fire : std_ulogic
            - signal irq_src_nxt : std_ulogic_vector(4 downto 0)
            - signal irq_run : std_ulogic
          Hierarchy:
            - rw_access: process(...)
            - irq_trigger: process(...)
            - irq_trigger_comb: process(...)
            - irq_buffer: process(...)
            - irq_priority: process(...)
            - irq_arbiter: process(...)
          Statements:
            ...
            ...
            ...
            ...
            ...
            ...
            ...
            ...
            ...
            ...
            ...
            ...
      Packages:
      PackageBodies:
      Configurations:
      Contexts:

Teardown

XPASS test_AllVHDLSources[/home/runner/work/extended-tests/extended-tests/NEORV32/rtl/core/neorv32_dmem.entity.vhd] 0:00:00.254848

Started 2021-11-23 15:22:20
Ended 2021-11-23 15:22:20
Duration 0:00:00.254848
Markers
xfail
Fixtures file

Setup

Call

Captured stdout call
================================================================================
                         pyGHDL.dom - Test Application                          
================================================================================
Parsing file '/home/runner/work/extended-tests/extended-tests/NEORV32/rtl/core/neorv32_dmem.entity.vhd'
libghdl processing time:  103.400 us
DOM translation time:    640.303 us

Design:
  Libraries:
    - Name: pretty
      Entities:
        - neorv32_dmem()
      Packages:
      Configurations:
      Contexts:
  Documents:
    - Path: '/home/runner/work/extended-tests/extended-tests/NEORV32/rtl/core/neorv32_dmem.entity.vhd':
      Entities:
        - Name: neorv32_dmem
          File: neorv32_dmem.entity.vhd
          Position: 39:7
          Generics:
            - DMEM_BASE : in std_ulogic_vector(31 downto 0)
            - DMEM_SIZE : in natural
          Ports:
            - clk_i : in std_ulogic
            - rden_i : in std_ulogic
            - wren_i : in std_ulogic
            - ben_i : in std_ulogic_vector(3 downto 0)
            - addr_i : in std_ulogic_vector(31 downto 0)
            - data_i : in std_ulogic_vector(31 downto 0)
            - data_o : out std_ulogic_vector(31 downto 0)
            - ack_o : out std_ulogic
          Declared:
          Statements:
          Architecures:
      Architectures:
      Packages:
      PackageBodies:
      Configurations:
      Contexts:

Teardown

XPASS test_AllVHDLSources[/home/runner/work/extended-tests/extended-tests/NEORV32/rtl/core/neorv32_application_image.vhd] 0:00:00.291730

Started 2021-11-23 15:22:20
Ended 2021-11-23 15:22:20
Duration 0:00:00.291730
Markers
xfail
Fixtures file

Setup

Call

Captured stdout call
================================================================================
                         pyGHDL.dom - Test Application                          
================================================================================
Parsing file '/home/runner/work/extended-tests/extended-tests/NEORV32/rtl/core/neorv32_application_image.vhd'
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
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libghdl processing time:  4216.924 us
DOM translation time:    29529.670 us

Design:
  Libraries:
    - Name: pretty
      Entities:
      Packages:
        - neorv32_application_image
      Configurations:
      Contexts:
  Documents:
    - Path: '/home/runner/work/extended-tests/extended-tests/NEORV32/rtl/core/neorv32_application_image.vhd':
      Entities:
      Architectures:
      Packages:
        - Name: neorv32_application_image
          File: neorv32_application_image.vhd
          Position: 11:8
          Declared:
          - constant application_init_image : mem32_t := (0 => None, 1 => None, 2 => None, 3 => None, 4 => None, 5 => None, 6 => None, 7 => None, 8 => None, 9 => None, 10 => None, 11 => None, 12 => None, 13 => None, 14 => None, 15 => None, 16 => None, 17 => None, 18 => None, 19 => None, 20 => None, 21 => None, 22 => None, 23 => None, 24 => None, 25 => None, 26 => None, 27 => None, 28 => None, 29 => None, 30 => None, 31 => None, 32 => None, 33 => None, 34 => None, 35 => None, 36 => None, 37 => None, 38 => None, 39 => None, 40 => None, 41 => None, 42 => None, 43 => None, 44 => None, 45 => None, 46 => None, 47 => None, 48 => None, 49 => None, 50 => None, 51 => None, 52 => None, 53 => None, 54 => None, 55 => None, 56 => None, 57 => None, 58 => None, 59 => None, 60 => None, 61 => None, 62 => None, 63 => None, 64 => None, 65 => None, 66 => None, 67 => None, 68 => None, 69 => None, 70 => None, 71 => None, 72 => None, 73 => None, 74 => None, 75 => None, 76 => None, 77 => None, 78 => None, 79 => None, 80 => None, 81 => None, 82 => None, 83 => None, 84 => None, 85 => None, 86 => None, 87 => None, 88 => None, 89 => None, 90 => None, 91 => None, 92 => None, 93 => None, 94 => None, 95 => None, 96 => None, 97 => None, 98 => None, 99 => None, 100 => None, 101 => None, 102 => None, 103 => None, 104 => None, 105 => None, 106 => None, 107 => None, 108 => None, 109 => None, 110 => None, 111 => None, 112 => None, 113 => None, 114 => None, 115 => None, 116 => None, 117 => None, 118 => None, 119 => None, 120 => None, 121 => None, 122 => None, 123 => None, 124 => None, 125 => None, 126 => None, 127 => None, 128 => None, 129 => None, 130 => None, 131 => None, 132 => None, 133 => None, 134 => None, 135 => None, 136 => None, 137 => None, 138 => None, 139 => None, 140 => None, 141 => None, 142 => None, 143 => None, 144 => None, 145 => None, 146 => None, 147 => None, 148 => None, 149 => None, 150 => None, 151 => None, 152 => None, 153 => None, 154 => None, 155 => None, 156 => None, 157 => None, 158 => None, 159 => None, 160 => None, 161 => None, 162 => None, 163 => None, 164 => None, 165 => None, 166 => None, 167 => None, 168 => None, 169 => None, 170 => None, 171 => None, 172 => None, 173 => None, 174 => None, 175 => None, 176 => None, 177 => None, 178 => None, 179 => None, 180 => None, 181 => None, 182 => None, 183 => None, 184 => None, 185 => None, 186 => None, 187 => None, 188 => None, 189 => None, 190 => None, 191 => None, 192 => None, 193 => None, 194 => None, 195 => None, 196 => None, 197 => None, 198 => None, 199 => None, 200 => None, 201 => None, 202 => None, 203 => None, 204 => None, 205 => None, 206 => None, 207 => None, 208 => None, 209 => None, 210 => None, 211 => None, 212 => None, 213 => None, 214 => None, 215 => None, 216 => None, 217 => None, 218 => None, 219 => None, 220 => None, 221 => None, 222 => None, 223 => None, 224 => None, 225 => None, 226 => None, 227 => None, 228 => None, 229 => None, 230 => None, 231 => None, 232 => None, 233 => None, 234 => None, 235 => None, 236 => None, 237 => None, 238 => None, 239 => None, 240 => None, 241 => None, 242 => None, 243 => None, 244 => None, 245 => None, 246 => None, 247 => None, 248 => None, 249 => None, 250 => None, 251 => None, 252 => None, 253 => None, 254 => None, 255 => None, 256 => None, 257 => None, 258 => None, 259 => None, 260 => None, 261 => None, 262 => None, 263 => None, 264 => None, 265 => None, 266 => None, 267 => None, 268 => None, 269 => None, 270 => None, 271 => None, 272 => None, 273 => None, 274 => None, 275 => None, 276 => None, 277 => None, 278 => None, 279 => None, 280 => None, 281 => None, 282 => None, 283 => None, 284 => None, 285 => None, 286 => None, 287 => None, 288 => None, 289 => None, 290 => None, 291 => None, 292 => None, 293 => None, 294 => None, 295 => None, 296 => None, 297 => None, 298 => None, 299 => None, 300 => None, 301 => None, 302 => None, 303 => None, 304 => None, 305 => None, 306 => None, 307 => None, 308 => None, 309 => None, 310 => None, 311 => None, 312 => None, 313 => None, 314 => None, 315 => None, 316 => None, 317 => None, 318 => None, 319 => None, 320 => None, 321 => None, 322 => None, 323 => None, 324 => None, 325 => None, 326 => None, 327 => None, 328 => None, 329 => None, 330 => None, 331 => None, 332 => None, 333 => None, 334 => None, 335 => None, 336 => None, 337 => None, 338 => None, 339 => None, 340 => None, 341 => None, 342 => None, 343 => None, 344 => None, 345 => None, 346 => None, 347 => None, 348 => None, 349 => None, 350 => None, 351 => None, 352 => None, 353 => None, 354 => None, 355 => None, 356 => None, 357 => None, 358 => None, 359 => None, 360 => None, 361 => None, 362 => None, 363 => None, 364 => None, 365 => None, 366 => None, 367 => None, 368 => None, 369 => None, 370 => None, 371 => None, 372 => None, 373 => None, 374 => None, 375 => None, 376 => None, 377 => None, 378 => None, 379 => None, 380 => None, 381 => None, 382 => None, 383 => None, 384 => None, 385 => None, 386 => None, 387 => None, 388 => None, 389 => None, 390 => None, 391 => None, 392 => None, 393 => None, 394 => None, 395 => None, 396 => None, 397 => None, 398 => None, 399 => None, 400 => None, 401 => None, 402 => None, 403 => None, 404 => None, 405 => None, 406 => None, 407 => None, 408 => None, 409 => None, 410 => None, 411 => None, 412 => None, 413 => None, 414 => None, 415 => None, 416 => None, 417 => None, 418 => None, 419 => None, 420 => None, 421 => None, 422 => None, 423 => None, 424 => None, 425 => None, 426 => None, 427 => None, 428 => None, 429 => None, 430 => None, 431 => None, 432 => None, 433 => None, 434 => None, 435 => None, 436 => None, 437 => None, 438 => None, 439 => None, 440 => None, 441 => None, 442 => None, 443 => None, 444 => None, 445 => None, 446 => None, 447 => None, 448 => None, 449 => None, 450 => None, 451 => None, 452 => None, 453 => None, 454 => None, 455 => None, 456 => None, 457 => None, 458 => None, 459 => None, 460 => None, 461 => None, 462 => None, 463 => None, 464 => None, 465 => None, 466 => None, 467 => None, 468 => None, 469 => None, 470 => None, 471 => None, 472 => None, 473 => None, 474 => None, 475 => None, 476 => None, 477 => None, 478 => None, 479 => None, 480 => None, 481 => None, 482 => None, 483 => None, 484 => None, 485 => None, 486 => None, 487 => None, 488 => None, 489 => None, 490 => None, 491 => None, 492 => None, 493 => None, 494 => None, 495 => None, 496 => None, 497 => None, 498 => None, 499 => None, 500 => None, 501 => None, 502 => None, 503 => None, 504 => None, 505 => None, 506 => None, 507 => None, 508 => None, 509 => None, 510 => None, 511 => None, 512 => None, 513 => None, 514 => None, 515 => None, 516 => None, 517 => None, 518 => None, 519 => None, 520 => None, 521 => None, 522 => None, 523 => None, 524 => None, 525 => None, 526 => None, 527 => None, 528 => None, 529 => None, 530 => None, 531 => None, 532 => None, 533 => None, 534 => None, 535 => None, 536 => None, 537 => None, 538 => None, 539 => None, 540 => None, 541 => None, 542 => None, 543 => None, 544 => None, 545 => None, 546 => None, 547 => None, 548 => None, 549 => None, 550 => None, 551 => None, 552 => None, 553 => None, 554 => None, 555 => None, 556 => None, 557 => None, 558 => None, 559 => None, 560 => None, 561 => None, 562 => None, 563 => None, 564 => None, 565 => None, 566 => None, 567 => None, 568 => None, 569 => None, 570 => None, 571 => None, 572 => None, 573 => None, 574 => None, 575 => None, 576 => None, 577 => None, 578 => None, 579 => None, 580 => None, 581 => None, 582 => None, 583 => None, 584 => None, 585 => None, 586 => None, 587 => None, 588 => None, 589 => None, 590 => None, 591 => None, 592 => None, 593 => None, 594 => None, 595 => None, 596 => None, 597 => None, 598 => None, 599 => None, 600 => None, 601 => None, 602 => None, 603 => None, 604 => None, 605 => None, 606 => None, 607 => None, 608 => None, 609 => None, 610 => None, 611 => None, 612 => None, 613 => None, 614 => None, 615 => None, 616 => None, 617 => None, 618 => None, 619 => None, 620 => None, 621 => None, 622 => None, 623 => None, 624 => None, 625 => None, 626 => None, 627 => None, 628 => None, 629 => None, 630 => None, 631 => None, 632 => None, 633 => None, 634 => None, 635 => None, 636 => None, 637 => None, 638 => None, 639 => None, 640 => None, 641 => None, 642 => None, 643 => None, 644 => None, 645 => None, 646 => None, 647 => None, 648 => None, 649 => None, 650 => None, 651 => None, 652 => None, 653 => None, 654 => None, 655 => None, 656 => None, 657 => None, 658 => None, 659 => None, 660 => None, 661 => None, 662 => None, 663 => None, 664 => None, 665 => None, 666 => None, 667 => None, 668 => None, 669 => None, 670 => None, 671 => None, 672 => None, 673 => None, 674 => None, 675 => None, 676 => None, 677 => None, 678 => None, 679 => None, 680 => None, 681 => None, 682 => None, 683 => None, 684 => None, 685 => None, 686 => None, 687 => None, 688 => None, 689 => None, 690 => None, 691 => None, 692 => None, 693 => None, 694 => None, 695 => None, 696 => None, 697 => None, 698 => None, 699 => None, 700 => None, 701 => None, 702 => None, 703 => None, 704 => None, 705 => None, 706 => None, 707 => None, 708 => None, 709 => None, 710 => None, 711 => None, 712 => None, 713 => None, 714 => None, 715 => None, 716 => None, 717 => None, 718 => None, 719 => None, 720 => None, 721 => None, 722 => None, 723 => None, 724 => None, 725 => None, 726 => None, 727 => None, 728 => None, 729 => None, 730 => None, 731 => None, 732 => None, 733 => None, 734 => None, 735 => None, 736 => None, 737 => None, 738 => None, 739 => None, 740 => None, 741 => None, 742 => None, 743 => None, 744 => None, 745 => None, 746 => None, 747 => None, 748 => None, 749 => None, 750 => None, 751 => None, 752 => None, 753 => None, 754 => None, 755 => None, 756 => None, 757 => None, 758 => None, 759 => None, 760 => None, 761 => None, 762 => None, 763 => None, 764 => None, 765 => None, 766 => None, 767 => None, 768 => None, 769 => None, 770 => None, 771 => None, 772 => None, 773 => None, 774 => None, 775 => None, 776 => None, 777 => None, 778 => None, 779 => None, 780 => None, 781 => None, 782 => None, 783 => None, 784 => None, 785 => None, 786 => None, 787 => None, 788 => None, 789 => None, 790 => None, 791 => None, 792 => None, 793 => None, 794 => None, 795 => None, 796 => None, 797 => None, 798 => None, 799 => None, 800 => None, 801 => None, 802 => None, 803 => None, 804 => None, 805 => None, 806 => None, 807 => None, 808 => None, 809 => None, 810 => None, 811 => None, 812 => None, 813 => None, 814 => None, 815 => None, 816 => None, 817 => None, 818 => None, 819 => None, 820 => None, 821 => None, 822 => None, 823 => None, 824 => None, 825 => None, 826 => None, 827 => None, 828 => None, 829 => None, 830 => None, 831 => None, 832 => None, 833 => None, 834 => None, 835 => None, 836 => None, 837 => None, 838 => None, 839 => None, 840 => None, 841 => None, 842 => None, 843 => None, 844 => None, 845 => None, 846 => None, 847 => None, 848 => None, 849 => None, 850 => None, 851 => None, 852 => None, 853 => None, 854 => None, 855 => None, 856 => None, 857 => None, 858 => None, 859 => None, 860 => None, 861 => None, 862 => None, 863 => None, 864 => None, 865 => None, 866 => None)
      PackageBodies:
      Configurations:
      Contexts:

Teardown

XPASS test_AllVHDLSources[/home/runner/work/extended-tests/extended-tests/NEORV32/rtl/core/neorv32_cpu_alu.vhd] 0:00:00.265740

Started 2021-11-23 15:22:20
Ended 2021-11-23 15:22:20
Duration 0:00:00.265740
Markers
xfail
Fixtures file

Setup

Call

Captured stdout call
================================================================================
                         pyGHDL.dom - Test Application                          
================================================================================
Parsing file '/home/runner/work/extended-tests/extended-tests/NEORV32/rtl/core/neorv32_cpu_alu.vhd'
[NOT IMPLEMENTED] Concurrent (conditional) signal assignment (label: 'None') at line 114
[NOT IMPLEMENTED] Concurrent (conditional) signal assignment (label: 'None') at line 115
[NOT IMPLEMENTED] Concurrent (conditional) signal assignment (label: 'None') at line 121
[NOT IMPLEMENTED] Concurrent (conditional) signal assignment (label: 'None') at line 122
[NOT IMPLEMENTED] Variable assignment (label: 'None') at line 135
[NOT IMPLEMENTED] Variable assignment (label: 'None') at line 136
[NOT IMPLEMENTED] Variable assignment (label: 'None') at line 139
[NOT IMPLEMENTED] Variable assignment (label: 'None') at line 140
[NOT IMPLEMENTED] Variable assignment (label: 'None') at line 142
[NOT IMPLEMENTED] Variable assignment (label: 'None') at line 143
[NOT IMPLEMENTED] Concurrent (conditional) signal assignment (label: 'None') at line 219
[NOT IMPLEMENTED] Concurrent (conditional) signal assignment (label: 'None') at line 220
[NOT IMPLEMENTED] Concurrent (conditional) signal assignment (label: 'None') at line 223
[NOT IMPLEMENTED] Concurrent (conditional) signal assignment (label: 'None') at line 224
[NOT IMPLEMENTED] Concurrent (conditional) signal assignment (label: 'None') at line 225
[NOT IMPLEMENTED] Concurrent (conditional) signal assignment (label: 'None') at line 226
libghdl processing time:  939.406 us
DOM translation time:    11428.466 us

Design:
  Libraries:
    - Name: pretty
      Entities:
        - neorv32_cpu_alu(neorv32_cpu_cpu_rtl)
      Packages:
      Configurations:
      Contexts:
  Documents:
    - Path: '/home/runner/work/extended-tests/extended-tests/NEORV32/rtl/core/neorv32_cpu_alu.vhd':
      Entities:
        - Name: neorv32_cpu_alu
          File: neorv32_cpu_alu.vhd
          Position: 44:7
          Generics:
            - CPU_EXTENSION_RISCV_B : in boolean
            - CPU_EXTENSION_RISCV_M : in boolean
            - CPU_EXTENSION_RISCV_Zmmul : in boolean
            - CPU_EXTENSION_RISCV_Zfinx : in boolean
            - FAST_MUL_EN : in boolean
            - FAST_SHIFT_EN : in boolean
          Ports:
            - clk_i : in std_ulogic
            - rstn_i : in std_ulogic
            - ctrl_i : in std_ulogic_vector(ctrl_width_c - 1 downto 0)
            - rs1_i : in std_ulogic_vector(data_width_c - 1 downto 0)
            - rs2_i : in std_ulogic_vector(data_width_c - 1 downto 0)
            - pc_i : in std_ulogic_vector(data_width_c - 1 downto 0)
            - pc2_i : in std_ulogic_vector(data_width_c - 1 downto 0)
            - imm_i : in std_ulogic_vector(data_width_c - 1 downto 0)
            - csr_i : in std_ulogic_vector(data_width_c - 1 downto 0)
            - cmp_o : out std_ulogic_vector(1 downto 0)
            - res_o : out std_ulogic_vector(data_width_c - 1 downto 0)
            - add_o : out std_ulogic_vector(data_width_c - 1 downto 0)
            - fpu_flags_o : out std_ulogic_vector(4 downto 0)
            - idone_o : out std_ulogic
          Declared:
          Statements:
          Architecures:
          - neorv32_cpu_cpu_rtl
      Architectures:
        - Name: neorv32_cpu_cpu_rtl
          File: neorv32_cpu_alu.vhd
          Position: 77:13
          Entity: neorv32_cpu_alu
          Declared:
            - signal cmp_opx : std_ulogic_vector(data_width_c downto 0)
            - signal cmp_opy : std_ulogic_vector(data_width_c downto 0)
            - signal cmp : std_ulogic_vector(1 downto 0)
            - signal opa, opb : std_ulogic_vector(data_width_c - 1 downto 0)
            - signal addsub_res : std_ulogic_vector(data_width_c downto 0)
            - signal alu_res : std_ulogic_vector(data_width_c - 1 downto 0)
            - signal cp_res : std_ulogic_vector(data_width_c - 1 downto 0)
            - type cp_ctrl_t is record ..... end record
            - signal cp_ctrl : cp_ctrl_t
            - signal cp_start : std_ulogic_vector(3 downto 0)
            - signal cp_valid : std_ulogic_vector(3 downto 0)
            - signal cp_result : cp_data_if_t
          Hierarchy:
            - binary_arithmetic_core: process(...)
            - alu_core: process(...)
            - alu_function_mux: process(...)
            - cp_arbiter: process(...)
            - neorv32_cpu_cp_shifter_inst: component neorv32_cpu_cp_shifter
            - neorv32_cpu_cp_muldiv_inst_true: if (CPU_EXTENSION_RISCV_M = true) or (CPU_EXTENSION_RISCV_Zmmul = true) generate
                - neorv32_cpu_cp_muldiv_inst: component neorv32_cpu_cp_muldiv
            - neorv32_cpu_cp_muldiv_inst_false: if (CPU_EXTENSION_RISCV_M = false) and (CPU_EXTENSION_RISCV_Zmmul = false) generate
            - neorv32_cpu_cp_bitmanip_inst_true: if (CPU_EXTENSION_RISCV_B = true) generate
                - neorv32_cpu_cp_bitmanip_inst: component neorv32_cpu_cp_bitmanip
            - neorv32_cpu_cp_bitmanip_inst_false: if (CPU_EXTENSION_RISCV_B = false) generate
            - neorv32_cpu_cp_fpu_inst_true: if (CPU_EXTENSION_RISCV_Zfinx = true) generate
                - neorv32_cpu_cp_fpu_inst: component neorv32_cpu_cp_fpu
            - neorv32_cpu_cp_fpu_inst_false: if (CPU_EXTENSION_RISCV_Zfinx = false) generate
          Statements:
            ...
            ...
            ...
            ...
            ...
            ...
            ...
            ...
            ...
            ...
            ...
            ...
            ...
            ...
            ...
            ...
            ...
      Packages:
      PackageBodies:
      Configurations:
      Contexts:

Teardown

XPASS test_AllVHDLSources[/home/runner/work/extended-tests/extended-tests/NEORV32/rtl/core/neorv32_imem.entity.vhd] 0:00:00.250757

Started 2021-11-23 15:22:20
Ended 2021-11-23 15:22:20
Duration 0:00:00.250757
Markers
xfail
Fixtures file

Setup

Call

Captured stdout call
================================================================================
                         pyGHDL.dom - Test Application                          
================================================================================
Parsing file '/home/runner/work/extended-tests/extended-tests/NEORV32/rtl/core/neorv32_imem.entity.vhd'
libghdl processing time:  137.901 us
DOM translation time:    998.606 us

Design:
  Libraries:
    - Name: pretty
      Entities:
        - neorv32_imem()
      Packages:
      Configurations:
      Contexts:
  Documents:
    - Path: '/home/runner/work/extended-tests/extended-tests/NEORV32/rtl/core/neorv32_imem.entity.vhd':
      Entities:
        - Name: neorv32_imem
          File: neorv32_imem.entity.vhd
          Position: 42:7
          Generics:
            - IMEM_BASE : in std_ulogic_vector(31 downto 0)
            - IMEM_SIZE : in natural
            - IMEM_AS_IROM : in boolean
          Ports:
            - clk_i : in std_ulogic
            - rden_i : in std_ulogic
            - wren_i : in std_ulogic
            - ben_i : in std_ulogic_vector(3 downto 0)
            - addr_i : in std_ulogic_vector(31 downto 0)
            - data_i : in std_ulogic_vector(31 downto 0)
            - data_o : out std_ulogic_vector(31 downto 0)
            - ack_o : out std_ulogic
          Declared:
          Statements:
          Architecures:
      Architectures:
      Packages:
      PackageBodies:
      Configurations:
      Contexts:

Teardown

XPASS test_AllVHDLSources[/home/runner/work/extended-tests/extended-tests/NEORV32/rtl/core/neorv32_fifo.vhd] 0:00:00.249605

Started 2021-11-23 15:22:20
Ended 2021-11-23 15:22:20
Duration 0:00:00.249605
Markers
xfail
Fixtures file

Setup

Call

Captured stdout call
================================================================================
                         pyGHDL.dom - Test Application                          
================================================================================
Parsing file '/home/runner/work/extended-tests/extended-tests/NEORV32/rtl/core/neorv32_fifo.vhd'
[NOT IMPLEMENTED] Array_Subtype_Definition
[NOT IMPLEMENTED] Concurrent (conditional) signal assignment (label: 'None') at line 99
[NOT IMPLEMENTED] Concurrent (conditional) signal assignment (label: 'None') at line 100
[NOT IMPLEMENTED] Concurrent (conditional) signal assignment (label: 'None') at line 127
[NOT IMPLEMENTED] Concurrent (conditional) signal assignment (label: 'None') at line 128
[NOT IMPLEMENTED] Concurrent (conditional) signal assignment (label: 'None') at line 129
[NOT IMPLEMENTED] Concurrent (conditional) signal assignment (label: 'None') at line 133
[NOT IMPLEMENTED] Concurrent (conditional) signal assignment (label: 'None') at line 169
libghdl processing time:  391.502 us
DOM translation time:    6180.536 us

Design:
  Libraries:
    - Name: pretty
      Entities:
        - neorv32_fifo(neorv32_fifo_rtl)
      Packages:
      Configurations:
      Contexts:
  Documents:
    - Path: '/home/runner/work/extended-tests/extended-tests/NEORV32/rtl/core/neorv32_fifo.vhd':
      Entities:
        - Name: neorv32_fifo
          File: neorv32_fifo.vhd
          Position: 42:7
          Generics:
            - FIFO_DEPTH : in natural
            - FIFO_WIDTH : in natural
            - FIFO_RSYNC : in boolean
            - FIFO_SAFE : in boolean
          Ports:
            - clk_i : in std_ulogic
            - rstn_i : in std_ulogic
            - clear_i : in std_ulogic
            - level_o : out std_ulogic_vector(index_size_f(FIFO_DEPTH) downto 0)
            - half_o : out std_ulogic
            - wdata_i : in std_ulogic_vector(FIFO_WIDTH - 1 downto 0)
            - we_i : in std_ulogic
            - free_o : out std_ulogic
            - re_i : in std_ulogic
            - rdata_o : out std_ulogic_vector(FIFO_WIDTH - 1 downto 0)
            - avail_o : out std_ulogic
          Declared:
          Statements:
          Architecures:
          - neorv32_fifo_rtl
      Architectures:
        - Name: neorv32_fifo_rtl
          File: neorv32_fifo.vhd
          Position: 67:13
          Entity: neorv32_fifo
          Declared:
            - type ???? is array(........) of .....
            - type fifo_t is record ..... end record
            - signal fifo : fifo_t
            - signal level_diff : std_ulogic_vector(index_size_f(FIFO_DEPTH) downto 0)
          Hierarchy:
            - fifo_control: process(...)
            - fifo_half_level: if (FIFO_DEPTH > 1) generate
            - fifo_half_level_simple: if (FIFO_DEPTH = 1) generate
            - fifo_memory_write: process(...)
            - fifo_read_async: if (FIFO_RSYNC = false) generate
            - fifo_read_sync: if (FIFO_RSYNC = true) generate
                - fifo_memory_read: process(...)
          Statements:
            ...
            ...
            ...
            ...
            ...
            ...
            ...
            ...
            ...
            ...
            ...
            ...
            ...
            ...
      Packages:
      PackageBodies:
      Configurations:
      Contexts:

Teardown

XPASS test_AllVHDLSources[/home/runner/work/extended-tests/extended-tests/NEORV32/rtl/core/neorv32_cfs.vhd] 0:00:00.254731

Started 2021-11-23 15:22:20
Ended 2021-11-23 15:22:21
Duration 0:00:00.254731
Markers
xfail
Fixtures file

Setup

Call

Captured stdout call
================================================================================
                         pyGHDL.dom - Test Application                          
================================================================================
Parsing file '/home/runner/work/extended-tests/extended-tests/NEORV32/rtl/core/neorv32_cfs.vhd'
[NOT IMPLEMENTED] Array_Subtype_Definition
[NOT IMPLEMENTED] Concurrent (conditional) signal assignment (label: 'None') at line 97
libghdl processing time:  344.502 us
DOM translation time:    4676.327 us

Design:
  Libraries:
    - Name: pretty
      Entities:
        - neorv32_cfs(neorv32_cfs_rtl)
      Packages:
      Configurations:
      Contexts:
  Documents:
    - Path: '/home/runner/work/extended-tests/extended-tests/NEORV32/rtl/core/neorv32_cfs.vhd':
      Entities:
        - Name: neorv32_cfs
          File: neorv32_cfs.vhd
          Position: 46:7
          Generics:
            - CFS_CONFIG : in std_ulogic_vector(31 downto 0)
            - CFS_IN_SIZE : in positive
            - CFS_OUT_SIZE : in positive
          Ports:
            - clk_i : in std_ulogic
            - rstn_i : in std_ulogic
            - addr_i : in std_ulogic_vector(31 downto 0)
            - rden_i : in std_ulogic
            - wren_i : in std_ulogic
            - data_i : in std_ulogic_vector(31 downto 0)
            - data_o : out std_ulogic_vector(31 downto 0)
            - ack_o : out std_ulogic
            - err_o : out std_ulogic
            - clkgen_en_o : out std_ulogic
            - clkgen_i : in std_ulogic_vector(7 downto 0)
            - irq_o : out std_ulogic
            - cfs_in_i : in std_ulogic_vector(CFS_IN_SIZE - 1 downto 0)
            - cfs_out_o : out std_ulogic_vector(CFS_OUT_SIZE - 1 downto 0)
          Declared:
          Statements:
          Architecures:
          - neorv32_cfs_rtl
      Architectures:
        - Name: neorv32_cfs_rtl
          File: neorv32_cfs.vhd
          Position: 74:13
          Entity: neorv32_cfs
          Declared:
            - constant hi_abb_c : natural := index_size_f(io_size_c) - 1
            - constant lo_abb_c : natural := index_size_f(cfs_size_c)
            - signal acc_en : std_ulogic
            - signal addr : std_ulogic_vector(31 downto 0)
            - signal wren : std_ulogic
            - signal rden : std_ulogic
            - type ???? is array(........) of .....
            - signal cfs_reg_wr : cfs_regs_t
            - signal cfs_reg_rd : cfs_regs_t
          Hierarchy:
            - host_access: process(...)
            - cfs_core: process(...)
          Statements:
            ...
            ...
            ...
            ...
            ...
            ...
            ...
            ...
            ...
      Packages:
      PackageBodies:
      Configurations:
      Contexts:

Teardown

XPASS test_AllVHDLSources[/home/runner/work/extended-tests/extended-tests/NEORV32/rtl/core/neorv32_icache.vhd] 0:00:00.261713

Started 2021-11-23 15:22:20
Ended 2021-11-23 15:22:21
Duration 0:00:00.261713
Markers
xfail
Fixtures file

Setup

Call

Captured stdout call
================================================================================
                         pyGHDL.dom - Test Application                          
================================================================================
Parsing file '/home/runner/work/extended-tests/extended-tests/NEORV32/rtl/core/neorv32_icache.vhd'
[NOT IMPLEMENTED] Array_Subtype_Definition
[NOT IMPLEMENTED] Array_Subtype_Definition
[NOT IMPLEMENTED] Array_Subtype_Definition
[NOT IMPLEMENTED] Array_Subtype_Definition
[NOT IMPLEMENTED] Concurrent (conditional) signal assignment (label: 'None') at line 493
[NOT IMPLEMENTED] Concurrent (conditional) signal assignment (label: 'None') at line 578
[NOT IMPLEMENTED] Concurrent (conditional) signal assignment (label: 'None') at line 584
[NOT IMPLEMENTED] Concurrent (conditional) signal assignment (label: 'None') at line 585
[NOT IMPLEMENTED] Concurrent (conditional) signal assignment (label: 'None') at line 586
libghdl processing time:  1184.607 us
DOM translation time:    17718.502 us

Design:
  Libraries:
    - Name: pretty
      Entities:
        - neorv32_icache(neorv32_icache_rtl)
        - neorv32_icache_memory(neorv32_icache_memory_rtl)
      Packages:
      Configurations:
      Contexts:
  Documents:
    - Path: '/home/runner/work/extended-tests/extended-tests/NEORV32/rtl/core/neorv32_icache.vhd':
      Entities:
        - Name: neorv32_icache
          File: neorv32_icache.vhd
          Position: 45:7
          Generics:
            - ICACHE_NUM_BLOCKS : in natural
            - ICACHE_BLOCK_SIZE : in natural
            - ICACHE_NUM_SETS : in natural
          Ports:
            - clk_i : in std_ulogic
            - rstn_i : in std_ulogic
            - clear_i : in std_ulogic
            - host_addr_i : in std_ulogic_vector(data_width_c - 1 downto 0)
            - host_rdata_o : out std_ulogic_vector(data_width_c - 1 downto 0)
            - host_wdata_i : in std_ulogic_vector(data_width_c - 1 downto 0)
            - host_ben_i : in std_ulogic_vector(3 downto 0)
            - host_we_i : in std_ulogic
            - host_re_i : in std_ulogic
            - host_ack_o : out std_ulogic
            - host_err_o : out std_ulogic
            - bus_addr_o : out std_ulogic_vector(data_width_c - 1 downto 0)
            - bus_rdata_i : in std_ulogic_vector(data_width_c - 1 downto 0)
            - bus_wdata_o : out std_ulogic_vector(data_width_c - 1 downto 0)
            - bus_ben_o : out std_ulogic_vector(3 downto 0)
            - bus_we_o : out std_ulogic
            - bus_re_o : out std_ulogic
            - bus_ack_i : in std_ulogic
            - bus_err_i : in std_ulogic
          Declared:
          Statements:
          Architecures:
          - neorv32_icache_rtl
        - Name: neorv32_icache_memory
          File: neorv32_icache.vhd
          Position: 384:7
          Generics:
            - ICACHE_NUM_BLOCKS : in natural := 4
            - ICACHE_BLOCK_SIZE : in natural := 16
            - ICACHE_NUM_SETS : in natural := 1
          Ports:
            - clk_i : in std_ulogic
            - invalidate_i : in std_ulogic
            - host_addr_i : in std_ulogic_vector(31 downto 0)
            - host_re_i : in std_ulogic
            - host_rdata_o : out std_ulogic_vector(31 downto 0)
            - hit_o : out std_ulogic
            - ctrl_en_i : in std_ulogic
            - ctrl_addr_i : in std_ulogic_vector(31 downto 0)
            - ctrl_we_i : in std_ulogic
            - ctrl_wdata_i : in std_ulogic_vector(31 downto 0)
            - ctrl_tag_we_i : in std_ulogic
            - ctrl_valid_i : in std_ulogic
            - ctrl_invalid_i : in std_ulogic
          Declared:
          Statements:
          Architecures:
          - neorv32_icache_memory_rtl
      Architectures:
        - Name: neorv32_icache_rtl
          File: neorv32_icache.vhd
          Position: 77:13
          Entity: neorv32_icache
          Declared:
            - constant cache_offset_size_c : natural := index_size_f(ICACHE_BLOCK_SIZE / 4)
            - constant cache_index_size_c : natural := index_size_f(ICACHE_NUM_BLOCKS)
            - constant cache_tag_size_c : natural := 32 - (cache_offset_size_c + cache_index_size_c + 2)
            - Component: neorv32_icache_memory
              Generics:
                - ICACHE_NUM_BLOCKS : in natural := 4
                - ICACHE_BLOCK_SIZE : in natural := 16
                - ICACHE_NUM_SETS : in natural := 1
              Ports:
                - clk_i : in std_ulogic
                - invalidate_i : in std_ulogic
                - host_addr_i : in std_ulogic_vector(31 downto 0)
                - host_re_i : in std_ulogic
                - host_rdata_o : out std_ulogic_vector(31 downto 0)
                - hit_o : out std_ulogic
                - ctrl_en_i : in std_ulogic
                - ctrl_addr_i : in std_ulogic_vector(31 downto 0)
                - ctrl_we_i : in std_ulogic
                - ctrl_wdata_i : in std_ulogic_vector(31 downto 0)
                - ctrl_tag_we_i : in std_ulogic
                - ctrl_valid_i : in std_ulogic
                - ctrl_invalid_i : in std_ulogic
            - type cache_if_t is record ..... end record
            - signal cache : cache_if_t
            - type ctrl_engine_state_t is (........)
            - type ctrl_t is record ..... end record
            - signal ctrl : ctrl_t
          Hierarchy:
            - ctrl_engine_fsm_sync_rst: process(...)
            - ctrl_engine_fsm_sync: process(...)
            - ctrl_engine_fsm_comb: process(...)
            - neorv32_icache_memory_inst: component neorv32_icache_memory
          Statements:
            ...
            ...
            ...
            ...
            ...
            ...
            ...
            ...
            ...
            ...
        - Name: neorv32_icache_memory_rtl
          File: neorv32_icache.vhd
          Position: 411:13
          Entity: neorv32_icache_memory
          Declared:
            - constant cache_offset_size_c : natural := index_size_f(ICACHE_BLOCK_SIZE / 4)
            - constant cache_index_size_c : natural := index_size_f(ICACHE_NUM_BLOCKS)
            - constant cache_tag_size_c : natural := 32 - (cache_offset_size_c + cache_index_size_c + 2)
            - constant cache_entries_c : natural := ICACHE_NUM_BLOCKS * (ICACHE_BLOCK_SIZE / 4)
            - signal valid_flag_s0 : std_ulogic_vector(ICACHE_NUM_BLOCKS - 1 downto 0)
            - signal valid_flag_s1 : std_ulogic_vector(ICACHE_NUM_BLOCKS - 1 downto 0)
            - signal valid : std_ulogic_vector(1 downto 0)
            - type ???? is array(........) of .....
            - signal tag_mem_s0 : tag_mem_t
            - signal tag_mem_s1 : tag_mem_t
            - type ???? is array(........) of .....
            - signal tag : tag_rd_t
            - signal hit : std_ulogic_vector(1 downto 0)
            - type acc_addr_t is record ..... end record
            - signal host_acc_addr, ctrl_acc_addr : acc_addr_t
            - type ???? is array(........) of .....
            - signal cache_data_memory_s0 : cache_mem_t
            - signal cache_data_memory_s1 : cache_mem_t
            - type ???? is array(........) of .....
            - signal cache_rdata : cache_rdata_t
            - signal cache_index : std_ulogic_vector(cache_index_size_c - 1 downto 0)
            - signal cache_offset : std_ulogic_vector(cache_offset_size_c - 1 downto 0)
            - signal cache_addr : std_ulogic_vector((cache_index_size_c + cache_offset_size_c) - 1 downto 0)
            - signal cache_we : std_ulogic
            - signal set_select : std_ulogic
            - type history_t is record ..... end record
            - signal history : history_t
          Hierarchy:
            - access_history: process(...)
            - status_memory: process(...)
            - tag_memory: process(...)
            - comparator: process(...)
            - cache_mem_access: process(...)
          Statements:
            ...
            ...
            ...
            ...
            ...
            ...
            ...
            ...
            ...
            ...
            ...
            ...
            ...
      Packages:
      PackageBodies:
      Configurations:
      Contexts:

Teardown

XPASS test_AllVHDLSources[/home/runner/work/extended-tests/extended-tests/NEORV32/rtl/core/neorv32_cpu_decompressor.vhd] 0:00:00.270297

Started 2021-11-23 15:22:21
Ended 2021-11-23 15:22:21
Duration 0:00:00.270297
Markers
xfail
Fixtures file

Setup

Call

Captured stdout call
================================================================================
                         pyGHDL.dom - Test Application                          
================================================================================
Parsing file '/home/runner/work/extended-tests/extended-tests/NEORV32/rtl/core/neorv32_cpu_decompressor.vhd'
[NOT IMPLEMENTED] Variable assignment (label: 'None') at line 85
[NOT IMPLEMENTED] Variable assignment (label: 'None') at line 86
[NOT IMPLEMENTED] Variable assignment (label: 'None') at line 87
[NOT IMPLEMENTED] Variable assignment (label: 'None') at line 88
[NOT IMPLEMENTED] Variable assignment (label: 'None') at line 89
[NOT IMPLEMENTED] Variable assignment (label: 'None') at line 90
[NOT IMPLEMENTED] Variable assignment (label: 'None') at line 91
[NOT IMPLEMENTED] Variable assignment (label: 'None') at line 92
[NOT IMPLEMENTED] Variable assignment (label: 'None') at line 93
[NOT IMPLEMENTED] Variable assignment (label: 'None') at line 94
[NOT IMPLEMENTED] Variable assignment (label: 'None') at line 95
[NOT IMPLEMENTED] Variable assignment (label: 'None') at line 96
[NOT IMPLEMENTED] Variable assignment (label: 'None') at line 97
[NOT IMPLEMENTED] Variable assignment (label: 'None') at line 100
[NOT IMPLEMENTED] Variable assignment (label: 'None') at line 101
[NOT IMPLEMENTED] Variable assignment (label: 'None') at line 102
[NOT IMPLEMENTED] Variable assignment (label: 'None') at line 103
[NOT IMPLEMENTED] Variable assignment (label: 'None') at line 104
[NOT IMPLEMENTED] Variable assignment (label: 'None') at line 105
[NOT IMPLEMENTED] Variable assignment (label: 'None') at line 106
[NOT IMPLEMENTED] Variable assignment (label: 'None') at line 107
[NOT IMPLEMENTED] Variable assignment (label: 'None') at line 108
[NOT IMPLEMENTED] Variable assignment (label: 'None') at line 109
libghdl processing time:  1395.108 us
DOM translation time:    17546.501 us

Design:
  Libraries:
    - Name: pretty
      Entities:
        - neorv32_cpu_decompressor(neorv32_cpu_decompressor_rtl)
      Packages:
      Configurations:
      Contexts:
  Documents:
    - Path: '/home/runner/work/extended-tests/extended-tests/NEORV32/rtl/core/neorv32_cpu_decompressor.vhd':
      Entities:
        - Name: neorv32_cpu_decompressor
          File: neorv32_cpu_decompressor.vhd
          Position: 42:7
          Generics:
          Ports:
            - ci_instr16_i : in std_ulogic_vector(15 downto 0)
            - ci_illegal_o : out std_ulogic
            - ci_instr32_o : out std_ulogic_vector(31 downto 0)
          Declared:
          Statements:
          Architecures:
          - neorv32_cpu_decompressor_rtl
      Architectures:
        - Name: neorv32_cpu_decompressor_rtl
          File: neorv32_cpu_decompressor.vhd
          Position: 52:13
          Entity: neorv32_cpu_decompressor
          Declared:
            - constant ci_opcode_lsb_c : natural := 0
            - constant ci_opcode_msb_c : natural := 1
            - constant ci_rd_3_lsb_c : natural := 2
            - constant ci_rd_3_msb_c : natural := 4
            - constant ci_rd_5_lsb_c : natural := 7
            - constant ci_rd_5_msb_c : natural := 11
            - constant ci_rs1_3_lsb_c : natural := 7
            - constant ci_rs1_3_msb_c : natural := 9
            - constant ci_rs1_5_lsb_c : natural := 7
            - constant ci_rs1_5_msb_c : natural := 11
            - constant ci_rs2_3_lsb_c : natural := 2
            - constant ci_rs2_3_msb_c : natural := 4
            - constant ci_rs2_5_lsb_c : natural := 2
            - constant ci_rs2_5_msb_c : natural := 6
            - constant ci_funct3_lsb_c : natural := 13
            - constant ci_funct3_msb_c : natural := 15
          Hierarchy:
            - decompressor: process(...)
          Statements:
            ...
      Packages:
      PackageBodies:
      Configurations:
      Contexts:

Teardown

XPASS test_AllVHDLSources[/home/runner/work/extended-tests/extended-tests/NEORV32/rtl/core/neorv32_cpu_cp_muldiv.vhd] 0:00:00.260343

Started 2021-11-23 15:22:21
Ended 2021-11-23 15:22:21
Duration 0:00:00.260343
Markers
xfail
Fixtures file

Setup

Call

Captured stdout call
================================================================================
                         pyGHDL.dom - Test Application                          
================================================================================
Parsing file '/home/runner/work/extended-tests/extended-tests/NEORV32/rtl/core/neorv32_cpu_cp_muldiv.vhd'
[NOT IMPLEMENTED] Concurrent (conditional) signal assignment (label: 'None') at line 205
[NOT IMPLEMENTED] Concurrent (conditional) signal assignment (label: 'None') at line 208
[NOT IMPLEMENTED] Concurrent (conditional) signal assignment (label: 'None') at line 211
[NOT IMPLEMENTED] Concurrent (conditional) signal assignment (label: 'None') at line 214
[NOT IMPLEMENTED] Concurrent (conditional) signal assignment (label: 'None') at line 270
[NOT IMPLEMENTED] Concurrent (conditional) signal assignment (label: 'None') at line 302
[NOT IMPLEMENTED] Concurrent (conditional) signal assignment (label: 'None') at line 304
libghdl processing time:  741.104 us
DOM translation time:    13917.581 us

Design:
  Libraries:
    - Name: pretty
      Entities:
        - neorv32_cpu_cp_muldiv(neorv32_cpu_cp_muldiv_rtl)
      Packages:
      Configurations:
      Contexts:
  Documents:
    - Path: '/home/runner/work/extended-tests/extended-tests/NEORV32/rtl/core/neorv32_cpu_cp_muldiv.vhd':
      Entities:
        - Name: neorv32_cpu_cp_muldiv
          File: neorv32_cpu_cp_muldiv.vhd
          Position: 49:7
          Generics:
            - FAST_MUL_EN : in boolean
            - DIVISION_EN : in boolean
          Ports:
            - clk_i : in std_ulogic
            - rstn_i : in std_ulogic
            - ctrl_i : in std_ulogic_vector(ctrl_width_c - 1 downto 0)
            - start_i : in std_ulogic
            - rs1_i : in std_ulogic_vector(data_width_c - 1 downto 0)
            - rs2_i : in std_ulogic_vector(data_width_c - 1 downto 0)
            - res_o : out std_ulogic_vector(data_width_c - 1 downto 0)
            - valid_o : out std_ulogic
          Declared:
          Statements:
          Architecures:
          - neorv32_cpu_cp_muldiv_rtl
      Architectures:
        - Name: neorv32_cpu_cp_muldiv_rtl
          File: neorv32_cpu_cp_muldiv.vhd
          Position: 69:13
          Entity: neorv32_cpu_cp_muldiv
          Declared:
            - constant cp_op_mul_c : std_ulogic_vector(2 downto 0) := "000"
            - constant cp_op_mulh_c : std_ulogic_vector(2 downto 0) := "001"
            - constant cp_op_mulhsu_c : std_ulogic_vector(2 downto 0) := "010"
            - constant cp_op_mulhu_c : std_ulogic_vector(2 downto 0) := "011"
            - constant cp_op_div_c : std_ulogic_vector(2 downto 0) := "100"
            - constant cp_op_divu_c : std_ulogic_vector(2 downto 0) := "101"
            - constant cp_op_rem_c : std_ulogic_vector(2 downto 0) := "110"
            - constant cp_op_remu_c : std_ulogic_vector(2 downto 0) := "111"
            - type state_t is (........)
            - signal state : state_t
            - signal cnt : std_ulogic_vector(4 downto 0)
            - signal cp_op : std_ulogic_vector(2 downto 0)
            - signal cp_op_ff : std_ulogic_vector(2 downto 0)
            - signal start_div : std_ulogic
            - signal start_mul : std_ulogic
            - signal operation : std_ulogic
            - signal div_opx : std_ulogic_vector(data_width_c - 1 downto 0)
            - signal div_opy : std_ulogic_vector(data_width_c - 1 downto 0)
            - signal rs1_is_signed : std_ulogic
            - signal rs2_is_signed : std_ulogic
            - signal opy_is_zero : std_ulogic
            - signal div_res_corr : std_ulogic
            - signal valid : std_ulogic
            - signal remainder : std_ulogic_vector(data_width_c - 1 downto 0)
            - signal quotient : std_ulogic_vector(data_width_c - 1 downto 0)
            - signal div_sub : std_ulogic_vector(data_width_c downto 0)
            - signal div_sign_comp_in : std_ulogic_vector(data_width_c - 1 downto 0)
            - signal div_sign_comp : std_ulogic_vector(data_width_c - 1 downto 0)
            - signal div_res : std_ulogic_vector(data_width_c - 1 downto 0)
            - signal mul_product : std_ulogic_vector(63 downto 0)
            - signal mul_do_add : std_ulogic_vector(data_width_c downto 0)
            - signal mul_sign_cycle : std_ulogic
            - signal mul_p_sext : std_ulogic
            - signal mul_op_x : signed(32 downto 0)
            - signal mul_op_y : signed(32 downto 0)
            - signal mul_buf_ff : signed(65 downto 0)
          Hierarchy:
            - coprocessor_ctrl: process(...)
            - multiplier_core_serial: if (FAST_MUL_EN = false) generate
                - multiplier_core: process(...)
            - multiplier_core_dsp: if (FAST_MUL_EN = true) generate
                - multiplier_core: process(...)
            - mul_update: process(...)
            - divider_core_serial: if (DIVISION_EN = true) generate
                - divider_core: process(...)
            - divider_core_serial_none: if (DIVISION_EN = false) generate
            - operation_result: process(...)
          Statements:
            ...
            ...
            ...
            ...
            ...
            ...
            ...
            ...
            ...
            ...
      Packages:
      PackageBodies:
      Configurations:
      Contexts:

Teardown

XPASS test_AllVHDLSources[/home/runner/work/extended-tests/extended-tests/NEORV32/rtl/core/neorv32_wishbone.vhd] 0:00:00.261705

Started 2021-11-23 15:22:21
Ended 2021-11-23 15:22:21
Duration 0:00:00.261705
Markers
xfail
Fixtures file

Setup

Call

Captured stdout call
================================================================================
                         pyGHDL.dom - Test Application                          
================================================================================
Parsing file '/home/runner/work/extended-tests/extended-tests/NEORV32/rtl/core/neorv32_wishbone.vhd'
[NOT IMPLEMENTED] Concurrent (conditional) signal assignment (label: 'None') at line 159
[NOT IMPLEMENTED] Concurrent (conditional) signal assignment (label: 'None') at line 160
[NOT IMPLEMENTED] Concurrent (conditional) signal assignment (label: 'None') at line 162
[NOT IMPLEMENTED] Concurrent (conditional) signal assignment (label: 'None') at line 245
[NOT IMPLEMENTED] Concurrent (conditional) signal assignment (label: 'None') at line 246
[NOT IMPLEMENTED] Concurrent (conditional) signal assignment (label: 'None') at line 247
[NOT IMPLEMENTED] Concurrent (conditional) signal assignment (label: 'None') at line 249
[NOT IMPLEMENTED] Concurrent (conditional) signal assignment (label: 'None') at line 251
[NOT IMPLEMENTED] Concurrent (conditional) signal assignment (label: 'None') at line 252
[NOT IMPLEMENTED] Concurrent (conditional) signal assignment (label: 'None') at line 257
[NOT IMPLEMENTED] Concurrent (conditional) signal assignment (label: 'None') at line 267
[NOT IMPLEMENTED] Concurrent (conditional) signal assignment (label: 'None') at line 270
[NOT IMPLEMENTED] Concurrent (conditional) signal assignment (label: 'None') at line 271
libghdl processing time:  580.504 us
DOM translation time:    7888.945 us

Design:
  Libraries:
    - Name: pretty
      Entities:
        - neorv32_wishbone(neorv32_wishbone_rtl)
      Packages:
      Configurations:
      Contexts:
  Documents:
    - Path: '/home/runner/work/extended-tests/extended-tests/NEORV32/rtl/core/neorv32_wishbone.vhd':
      Entities:
        - Name: neorv32_wishbone
          File: neorv32_wishbone.vhd
          Position: 50:7
          Generics:
            - MEM_INT_IMEM_EN : in boolean
            - MEM_INT_IMEM_SIZE : in natural
            - MEM_INT_DMEM_EN : in boolean
            - MEM_INT_DMEM_SIZE : in natural
            - BUS_TIMEOUT : in natural
            - PIPE_MODE : in boolean
            - BIG_ENDIAN : in boolean
            - ASYNC_RX : in boolean
          Ports:
            - clk_i : in std_ulogic
            - rstn_i : in std_ulogic
            - src_i : in std_ulogic
            - addr_i : in std_ulogic_vector(31 downto 0)
            - rden_i : in std_ulogic
            - wren_i : in std_ulogic
            - ben_i : in std_ulogic_vector(3 downto 0)
            - data_i : in std_ulogic_vector(31 downto 0)
            - data_o : out std_ulogic_vector(31 downto 0)
            - lock_i : in std_ulogic
            - ack_o : out std_ulogic
            - err_o : out std_ulogic
            - tmo_o : out std_ulogic
            - priv_i : in std_ulogic_vector(1 downto 0)
            - ext_o : out std_ulogic
            - wb_tag_o : out std_ulogic_vector(2 downto 0)
            - wb_adr_o : out std_ulogic_vector(31 downto 0)
            - wb_dat_i : in std_ulogic_vector(31 downto 0)
            - wb_dat_o : out std_ulogic_vector(31 downto 0)
            - wb_we_o : out std_ulogic
            - wb_sel_o : out std_ulogic_vector(3 downto 0)
            - wb_stb_o : out std_ulogic
            - wb_cyc_o : out std_ulogic
            - wb_lock_o : out std_ulogic
            - wb_ack_i : in std_ulogic
            - wb_err_i : in std_ulogic
          Declared:
          Statements:
          Architecures:
          - neorv32_wishbone_rtl
      Architectures:
        - Name: neorv32_wishbone_rtl
          File: neorv32_wishbone.vhd
          Position: 97:13
          Entity: neorv32_wishbone
          Declared:
            - constant timeout_en_c : boolean := boolean(BUS_TIMEOUT /= 0)
            - signal int_imem_acc : std_ulogic
            - signal int_dmem_acc : std_ulogic
            - signal int_boot_acc : std_ulogic
            - signal xbus_access : std_ulogic
            - type ctrl_state_t is (........)
            - type ctrl_t is record ..... end record
            - signal ctrl : ctrl_t
            - signal stb_int : std_ulogic
            - signal cyc_int : std_ulogic
            - signal rdata : std_ulogic_vector(31 downto 0)
            - signal ack_gated : std_ulogic
            - signal rdata_gated : std_ulogic_vector(31 downto 0)
          Hierarchy:
            - bus_arbiter: process(...)
          Statements:
            ...
            ...
            ...
            ...
            ...
            ...
            ...
            ...
            ...
            ...
            ...
            ...
            ...
            ...
            ...
            ...
            ...
            ...
            ...
            ...
      Packages:
      PackageBodies:
      Configurations:
      Contexts:

Teardown

XPASS test_AllVHDLSources[/home/runner/work/extended-tests/extended-tests/NEORV32/rtl/core/neorv32_spi.vhd] 0:00:00.255449

Started 2021-11-23 15:22:21
Ended 2021-11-23 15:22:21
Duration 0:00:00.255449
Markers
xfail
Fixtures file

Setup

Call

Captured stdout call
================================================================================
                         pyGHDL.dom - Test Application                          
================================================================================
Parsing file '/home/runner/work/extended-tests/extended-tests/NEORV32/rtl/core/neorv32_spi.vhd'
[NOT IMPLEMENTED] Concurrent (conditional) signal assignment (label: 'None') at line 131
[NOT IMPLEMENTED] Concurrent (conditional) signal assignment (label: 'None') at line 202
[NOT IMPLEMENTED] Concurrent (conditional) signal assignment (label: 'None') at line 292
[NOT IMPLEMENTED] Concurrent (conditional) signal assignment (label: 'None') at line 316
libghdl processing time:  582.104 us
DOM translation time:    11241.365 us

Design:
  Libraries:
    - Name: pretty
      Entities:
        - neorv32_spi(neorv32_spi_rtl)
      Packages:
      Configurations:
      Contexts:
  Documents:
    - Path: '/home/runner/work/extended-tests/extended-tests/NEORV32/rtl/core/neorv32_spi.vhd':
      Entities:
        - Name: neorv32_spi
          File: neorv32_spi.vhd
          Position: 46:7
          Generics:
          Ports:
            - clk_i : in std_ulogic
            - addr_i : in std_ulogic_vector(31 downto 0)
            - rden_i : in std_ulogic
            - wren_i : in std_ulogic
            - data_i : in std_ulogic_vector(31 downto 0)
            - data_o : out std_ulogic_vector(31 downto 0)
            - ack_o : out std_ulogic
            - clkgen_en_o : out std_ulogic
            - clkgen_i : in std_ulogic_vector(7 downto 0)
            - spi_sck_o : out std_ulogic
            - spi_sdo_o : out std_ulogic
            - spi_sdi_i : in std_ulogic
            - spi_csn_o : out std_ulogic_vector(7 downto 0)
            - irq_o : out std_ulogic
          Declared:
          Statements:
          Architecures:
          - neorv32_spi_rtl
      Architectures:
        - Name: neorv32_spi_rtl
          File: neorv32_spi.vhd
          Position: 69:13
          Entity: neorv32_spi
          Declared:
            - constant hi_abb_c : natural := index_size_f(io_size_c) - 1
            - constant lo_abb_c : natural := index_size_f(spi_size_c)
            - constant ctrl_cs0_c : natural := 0
            - constant ctrl_cs1_c : natural := 1
            - constant ctrl_cs2_c : natural := 2
            - constant ctrl_cs3_c : natural := 3
            - constant ctrl_cs4_c : natural := 4
            - constant ctrl_cs5_c : natural := 5
            - constant ctrl_cs6_c : natural := 6
            - constant ctrl_cs7_c : natural := 7
            - constant ctrl_en_c : natural := 8
            - constant ctrl_cpha_c : natural := 9
            - constant ctrl_prsc0_c : natural := 10
            - constant ctrl_prsc1_c : natural := 11
            - constant ctrl_prsc2_c : natural := 12
            - constant ctrl_size0_c : natural := 13
            - constant ctrl_size1_c : natural := 14
            - constant ctrl_cpol_c : natural := 15
            - constant ctrl_busy_c : natural := 31
            - signal ctrl : std_ulogic_vector(15 downto 0)
            - signal acc_en : std_ulogic
            - signal addr : std_ulogic_vector(31 downto 0)
            - signal wren : std_ulogic
            - signal rden : std_ulogic
            - signal spi_clk_en : std_ulogic
            - type rtx_engine_t is record ..... end record
            - signal rtx_engine : rtx_engine_t
            - type irq_t is record ..... end record
            - signal irq : irq_t
          Hierarchy:
            - rw_access: process(...)
            - data_size: process(...)
            - spi_rtx_unit: process(...)
            - irq_generator: process(...)
          Statements:
            ...
            ...
            ...
            ...
            ...
            ...
            ...
            ...
            ...
            ...
            ...
      Packages:
      PackageBodies:
      Configurations:
      Contexts:

Teardown

XPASS test_AllVHDLSources[/home/runner/work/extended-tests/extended-tests/NEORV32/rtl/core/neorv32_pwm.vhd] 0:00:00.262515

Started 2021-11-23 15:22:21
Ended 2021-11-23 15:22:21
Duration 0:00:00.262515
Markers
xfail
Fixtures file

Setup

Call

Captured stdout call
================================================================================
                         pyGHDL.dom - Test Application                          
================================================================================
Parsing file '/home/runner/work/extended-tests/extended-tests/NEORV32/rtl/core/neorv32_pwm.vhd'
[NOT IMPLEMENTED] Array_Subtype_Definition
[NOT IMPLEMENTED] Array_Subtype_Definition
[NOT IMPLEMENTED] Concurrent (conditional) signal assignment (label: 'None') at line 108
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
libghdl processing time:  576.204 us
DOM translation time:    10656.961 us

Design:
  Libraries:
    - Name: pretty
      Entities:
        - neorv32_pwm(neorv32_pwm_rtl)
      Packages:
      Configurations:
      Contexts:
  Documents:
    - Path: '/home/runner/work/extended-tests/extended-tests/NEORV32/rtl/core/neorv32_pwm.vhd':
      Entities:
        - Name: neorv32_pwm
          File: neorv32_pwm.vhd
          Position: 45:7
          Generics:
            - NUM_CHANNELS : in natural
          Ports:
            - clk_i : in std_ulogic
            - addr_i : in std_ulogic_vector(31 downto 0)
            - rden_i : in std_ulogic
            - wren_i : in std_ulogic
            - data_i : in std_ulogic_vector(31 downto 0)
            - data_o : out std_ulogic_vector(31 downto 0)
            - ack_o : out std_ulogic
            - clkgen_en_o : out std_ulogic
            - clkgen_i : in std_ulogic_vector(7 downto 0)
            - pwm_o : out std_ulogic_vector(NUM_CHANNELS - 1 downto 0)
          Declared:
          Statements:
          Architecures:
          - neorv32_pwm_rtl
      Architectures:
        - Name: neorv32_pwm_rtl
          File: neorv32_pwm.vhd
          Position: 66:13
          Entity: neorv32_pwm
          Declared:
            - constant hi_abb_c : natural := index_size_f(io_size_c) - 1
            - constant lo_abb_c : natural := index_size_f(pwm_size_c)
            - constant ctrl_enable_c : natural := 0
            - constant ctrl_prsc0_bit_c : natural := 1
            - constant ctrl_prsc1_bit_c : natural := 2
            - constant ctrl_prsc2_bit_c : natural := 3
            - signal acc_en : std_ulogic
            - signal addr : std_ulogic_vector(31 downto 0)
            - signal wren : std_ulogic
            - signal rden : std_ulogic
            - type ???? is array(........) of .....
            - signal pwm_ch : pwm_ch_t
            - signal enable : std_ulogic
            - signal prsc : std_ulogic_vector(2 downto 0)
            - type ???? is array(........) of .....
            - signal pwm_ch_rd : pwm_ch_rd_t
            - signal prsc_tick : std_ulogic
            - signal pwm_cnt : std_ulogic_vector(7 downto 0)
          Hierarchy:
            - wr_access: process(...)
            - pwm_dc_rd_gen: process(...)
            - pwm_core: process(...)
          Statements:
            ...
            ...
            ...
            ...
            ...
            ...
            ...
            ...
            ...
      Packages:
      PackageBodies:
      Configurations:
      Contexts:

Teardown

XPASS test_AllVHDLSources[/home/runner/work/extended-tests/extended-tests/NEORV32/rtl/core/neorv32_wdt.vhd] 0:00:00.257960

Started 2021-11-23 15:22:21
Ended 2021-11-23 15:22:22
Duration 0:00:00.257960
Markers
xfail
Fixtures file

Setup

Call

Captured stdout call
================================================================================
                         pyGHDL.dom - Test Application                          
================================================================================
Parsing file '/home/runner/work/extended-tests/extended-tests/NEORV32/rtl/core/neorv32_wdt.vhd'
[NOT IMPLEMENTED] Concurrent (conditional) signal assignment (label: 'None') at line 127
libghdl processing time:  641.004 us
DOM translation time:    8763.350 us

Design:
  Libraries:
    - Name: pretty
      Entities:
        - neorv32_wdt(neorv32_wdt_rtl)
      Packages:
      Configurations:
      Contexts:
  Documents:
    - Path: '/home/runner/work/extended-tests/extended-tests/NEORV32/rtl/core/neorv32_wdt.vhd':
      Entities:
        - Name: neorv32_wdt
          File: neorv32_wdt.vhd
          Position: 50:7
          Generics:
          Ports:
            - clk_i : in std_ulogic
            - rstn_i : in std_ulogic
            - addr_i : in std_ulogic_vector(31 downto 0)
            - rden_i : in std_ulogic
            - wren_i : in std_ulogic
            - data_i : in std_ulogic_vector(31 downto 0)
            - data_o : out std_ulogic_vector(31 downto 0)
            - ack_o : out std_ulogic
            - clkgen_en_o : out std_ulogic
            - clkgen_i : in std_ulogic_vector(7 downto 0)
            - irq_o : out std_ulogic
            - rstn_o : out std_ulogic
          Declared:
          Statements:
          Architecures:
          - neorv32_wdt_rtl
      Architectures:
        - Name: neorv32_wdt_rtl
          File: neorv32_wdt.vhd
          Position: 70:13
          Entity: neorv32_wdt
          Declared:
            - constant hi_abb_c : natural := index_size_f(io_size_c) - 1
            - constant lo_abb_c : natural := index_size_f(wdt_size_c)
            - constant ctrl_enable_c : natural := 0
            - constant ctrl_clksel0_c : natural := 1
            - constant ctrl_clksel1_c : natural := 2
            - constant ctrl_clksel2_c : natural := 3
            - constant ctrl_mode_c : natural := 4
            - constant ctrl_rcause_c : natural := 5
            - constant ctrl_reset_c : natural := 6
            - constant ctrl_force_c : natural := 7
            - constant ctrl_lock_c : natural := 8
            - signal acc_en : std_ulogic
            - signal wren : std_ulogic
            - signal rden : std_ulogic
            - type ctrl_reg_t is record ..... end record
            - signal ctrl_reg : ctrl_reg_t
            - signal prsc_tick : std_ulogic
            - signal wdt_cnt : std_ulogic_vector(20 downto 0)
            - signal hw_rst : std_ulogic
            - signal rst_gen : std_ulogic_vector(3 downto 0)
            - signal rstn_sync : std_ulogic
            - type cpu_irq_t is record ..... end record
            - signal cpu_irq : cpu_irq_t
          Hierarchy:
            - write_access: process(...)
            - wdt_counter: process(...)
            - irq_gen: process(...)
            - reset_generator: process(...)
            - read_access: process(...)
          Statements:
            ...
            ...
            ...
            ...
            ...
            ...
            ...
            ...
            ...
            ...
            ...
            ...
            ...
            ...
      Packages:
      PackageBodies:
      Configurations:
      Contexts:

Teardown

XPASS test_AllVHDLSources[/home/runner/work/extended-tests/extended-tests/NEORV32/rtl/core/neorv32_boot_rom.vhd] 0:00:00.269386

Started 2021-11-23 15:22:21
Ended 2021-11-23 15:22:22
Duration 0:00:00.269386
Markers
xfail
Fixtures file

Setup

Call

Captured stdout call
================================================================================
                         pyGHDL.dom - Test Application                          
================================================================================
Parsing file '/home/runner/work/extended-tests/extended-tests/NEORV32/rtl/core/neorv32_boot_rom.vhd'
[NOT IMPLEMENTED] Concurrent (conditional) signal assignment (label: 'None') at line 85
[NOT IMPLEMENTED] Concurrent (conditional) signal assignment (label: 'None') at line 102
libghdl processing time:  245.401 us
DOM translation time:    2473.714 us

Design:
  Libraries:
    - Name: pretty
      Entities:
        - neorv32_boot_rom(neorv32_boot_rom_rtl)
      Packages:
      Configurations:
      Contexts:
  Documents:
    - Path: '/home/runner/work/extended-tests/extended-tests/NEORV32/rtl/core/neorv32_boot_rom.vhd':
      Entities:
        - Name: neorv32_boot_rom
          File: neorv32_boot_rom.vhd
          Position: 43:7
          Generics:
            - BOOTROM_BASE : in std_ulogic_vector(31 downto 0)
          Ports:
            - clk_i : in std_ulogic
            - rden_i : in std_ulogic
            - addr_i : in std_ulogic_vector(31 downto 0)
            - data_o : out std_ulogic_vector(31 downto 0)
            - ack_o : out std_ulogic
          Declared:
          Statements:
          Architecures:
          - neorv32_boot_rom_rtl
      Architectures:
        - Name: neorv32_boot_rom_rtl
          File: neorv32_boot_rom.vhd
          Position: 56:13
          Entity: neorv32_boot_rom
          Declared:
            - constant boot_rom_size_index_c : natural := index_size_f((bootloader_init_image'length))
            - constant boot_rom_size_c : natural := (2**boot_rom_size_index_c) * 4
            - constant hi_abb_c : natural := 31
            - constant lo_abb_c : natural := index_size_f(boot_rom_max_size_c)
            - signal acc_en : std_ulogic
            - signal rden : std_ulogic
            - signal rdata : std_ulogic_vector(31 downto 0)
            - signal addr : std_ulogic_vector(boot_rom_size_index_c - 1 downto 0)
            - constant mem_rom : mem32_t(0 to boot_rom_size_c / 4 - 1) := mem32_init_f(bootloader_init_image, boot_rom_size_c / 4)
          Hierarchy:
            - mem_file_access: process(...)
          Statements:
            ...
            ...
            ...
            ...
            ...
      Packages:
      PackageBodies:
      Configurations:
      Contexts:

Teardown

XPASS test_AllVHDLSources[/home/runner/work/extended-tests/extended-tests/NEORV32/rtl/core/neorv32_debug_dtm.vhd] 0:00:00.270996

Started 2021-11-23 15:22:22
Ended 2021-11-23 15:22:22
Duration 0:00:00.270996
Markers
xfail
Fixtures file

Setup

Call

Captured stdout call
================================================================================
                         pyGHDL.dom - Test Application                          
================================================================================
Parsing file '/home/runner/work/extended-tests/extended-tests/NEORV32/rtl/core/neorv32_debug_dtm.vhd'
[NOT IMPLEMENTED] Concurrent (conditional) signal assignment (label: 'None') at line 148
[NOT IMPLEMENTED] Concurrent (conditional) signal assignment (label: 'None') at line 151
[NOT IMPLEMENTED] Concurrent (conditional) signal assignment (label: 'None') at line 152
[NOT IMPLEMENTED] Concurrent (conditional) signal assignment (label: 'None') at line 342
[NOT IMPLEMENTED] Concurrent (conditional) signal assignment (label: 'None') at line 345
[NOT IMPLEMENTED] Concurrent (conditional) signal assignment (label: 'None') at line 346
[NOT IMPLEMENTED] Concurrent (conditional) signal assignment (label: 'None') at line 347
[NOT IMPLEMENTED] Concurrent (conditional) signal assignment (label: 'None') at line 348
libghdl processing time:  781.004 us
DOM translation time:    16647.496 us

Design:
  Libraries:
    - Name: pretty
      Entities:
        - neorv32_debug_dtm(neorv32_debug_dtm_rtl)
      Packages:
      Configurations:
      Contexts:
  Documents:
    - Path: '/home/runner/work/extended-tests/extended-tests/NEORV32/rtl/core/neorv32_debug_dtm.vhd':
      Entities:
        - Name: neorv32_debug_dtm
          File: neorv32_debug_dtm.vhd
          Position: 41:7
          Generics:
            - IDCODE_VERSION : in std_ulogic_vector(3 downto 0)
            - IDCODE_PARTID : in std_ulogic_vector(15 downto 0)
            - IDCODE_MANID : in std_ulogic_vector(10 downto 0)
          Ports:
            - clk_i : in std_ulogic
            - rstn_i : in std_ulogic
            - jtag_trst_i : in std_ulogic
            - jtag_tck_i : in std_ulogic
            - jtag_tdi_i : in std_ulogic
            - jtag_tdo_o : out std_ulogic
            - jtag_tms_i : in std_ulogic
            - dmi_rstn_o : out std_ulogic
            - dmi_req_valid_o : out std_ulogic
            - dmi_req_ready_i : in std_ulogic
            - dmi_req_addr_o : out std_ulogic_vector(6 downto 0)
            - dmi_req_op_o : out std_ulogic
            - dmi_req_data_o : out std_ulogic_vector(31 downto 0)
            - dmi_resp_valid_i : in std_ulogic
            - dmi_resp_ready_o : out std_ulogic
            - dmi_resp_data_i : in std_ulogic_vector(31 downto 0)
            - dmi_resp_err_i : in std_ulogic
          Declared:
          Statements:
          Architecures:
          - neorv32_debug_dtm_rtl
      Architectures:
        - Name: neorv32_debug_dtm_rtl
          File: neorv32_debug_dtm.vhd
          Position: 71:13
          Entity: neorv32_debug_dtm
          Declared:
            - constant dmi_idle_c : std_ulogic_vector(2 downto 0) := "000"
            - constant dmi_version_c : std_ulogic_vector(3 downto 0) := "0001"
            - constant dmi_abits_c : std_ulogic_vector(5 downto 0) := "000111"
            - type tap_sync_t is record ..... end record
            - signal tap_sync : tap_sync_t
            - type tap_ctrl_state_t is (........)
            - type tap_ctrl_t is record ..... end record
            - signal tap_ctrl : tap_ctrl_t
            - type tap_reg_t is record ..... end record
            - signal tap_reg : tap_reg_t
            - type dmi_ctrl_state_t is (........)
            - type dmi_ctrl_t is record ..... end record
            - signal dmi_ctrl : dmi_ctrl_t
          Hierarchy:
            - tap_synchronizer: process(...)
            - tap_control: process(...)
            - reg_access: process(...)
            - dmi_controller: process(...)
          Statements:
            ...
            ...
            ...
            ...
            ...
            ...
            ...
            ...
            ...
            ...
            ...
            ...
            ...
            ...
            ...
            ...
            ...
            ...
      Packages:
      PackageBodies:
      Configurations:
      Contexts:

Teardown

XPASS test_AllVHDLSources[/home/runner/work/extended-tests/extended-tests/NEORV32/rtl/core/neorv32_uart.vhd] 0:00:00.273646

Started 2021-11-23 15:22:22
Ended 2021-11-23 15:22:22
Duration 0:00:00.273646
Markers
xfail
Fixtures file

Setup

Call

Captured stdout call
================================================================================
                         pyGHDL.dom - Test Application                          
================================================================================
Parsing file '/home/runner/work/extended-tests/extended-tests/NEORV32/rtl/core/neorv32_uart.vhd'
[NOT IMPLEMENTED] Concurrent (conditional) signal assignment (label: 'None') at line 252
[NOT IMPLEMENTED] Concurrent (conditional) signal assignment (label: 'None') at line 317
[NOT IMPLEMENTED] Concurrent (conditional) signal assignment (label: 'None') at line 359
[NOT IMPLEMENTED] Concurrent (conditional) signal assignment (label: 'None') at line 440
[NOT IMPLEMENTED] Concurrent (conditional) signal assignment (label: 'None') at line 502
[NOT IMPLEMENTED] Concurrent (conditional) signal assignment (label: 'None') at line 535
[NOT IMPLEMENTED] Concurrent (conditional) signal assignment (label: 'None') at line 538
[NOT IMPLEMENTED] Concurrent (conditional) signal assignment (label: 'None') at line 539
[NOT IMPLEMENTED] Concurrent (conditional) signal assignment (label: 'None') at line 544
[NOT IMPLEMENTED] Concurrent (conditional) signal assignment (label: 'None') at line 545
[NOT IMPLEMENTED] Concurrent (conditional) signal assignment (label: 'None') at line 613
[NOT IMPLEMENTED] Concurrent (conditional) signal assignment (label: 'None') at line 614
[NOT IMPLEMENTED] Variable assignment (label: 'None') at line 634
[NOT IMPLEMENTED] Variable assignment (label: 'None') at line 636
libghdl processing time:  1413.508 us
DOM translation time:    25239.545 us

Design:
  Libraries:
    - Name: pretty
      Entities:
        - neorv32_uart(neorv32_uart_rtl)
      Packages:
      Configurations:
      Contexts:
  Documents:
    - Path: '/home/runner/work/extended-tests/extended-tests/NEORV32/rtl/core/neorv32_uart.vhd':
      Entities:
        - Name: neorv32_uart
          File: neorv32_uart.vhd
          Position: 68:7
          Generics:
            - UART_PRIMARY : in boolean
            - UART_RX_FIFO : in natural
            - UART_TX_FIFO : in natural
          Ports:
            - clk_i : in std_ulogic
            - addr_i : in std_ulogic_vector(31 downto 0)
            - rden_i : in std_ulogic
            - wren_i : in std_ulogic
            - data_i : in std_ulogic_vector(31 downto 0)
            - data_o : out std_ulogic_vector(31 downto 0)
            - ack_o : out std_ulogic
            - clkgen_en_o : out std_ulogic
            - clkgen_i : in std_ulogic_vector(7 downto 0)
            - uart_txd_o : out std_ulogic
            - uart_rxd_i : in std_ulogic
            - uart_rts_o : out std_ulogic
            - uart_cts_i : in std_ulogic
            - irq_rxd_o : out std_ulogic
            - irq_txd_o : out std_ulogic
          Declared:
          Statements:
          Architecures:
          - neorv32_uart_rtl
      Architectures:
        - Name: neorv32_uart_rtl
          File: neorv32_uart.vhd
          Position: 98:13
          Entity: neorv32_uart
          Declared:
            - constant uart_id_base_c : std_ulogic_vector(data_width_c - 1 downto 0) := cond_sel_stdulogicvector_f(UART_PRIMARY, uart0_base_c, uart1_base_c)
            - constant uart_id_size_c : natural := cond_sel_natural_f(UART_PRIMARY, uart0_size_c, uart1_size_c)
            - constant uart_id_ctrl_addr_c : std_ulogic_vector(data_width_c - 1 downto 0) := cond_sel_stdulogicvector_f(UART_PRIMARY, uart0_ctrl_addr_c, uart1_ctrl_addr_c)
            - constant uart_id_rtx_addr_c : std_ulogic_vector(data_width_c - 1 downto 0) := cond_sel_stdulogicvector_f(UART_PRIMARY, uart0_rtx_addr_c, uart1_rtx_addr_c)
            - constant hi_abb_c : natural := index_size_f(io_size_c) - 1
            - constant lo_abb_c : natural := index_size_f(uart_id_size_c)
            - constant sim_screen_output_en_c : boolean := true
            - constant sim_text_output_en_c : boolean := true
            - constant sim_data_output_en_c : boolean := true
            - constant sim_uart_text_file_c : string := cond_sel_string_f(UART_PRIMARY, "neorv32.uart0.sim_mode.text.out", "neorv32.uart1.sim_mode.text.out")
            - constant sim_uart_data_file_c : string := cond_sel_string_f(UART_PRIMARY, "neorv32.uart0.sim_mode.data.out", "neorv32.uart1.sim_mode.data.out")
            - signal ctrl : std_ulogic_vector(31 downto 0)
            - constant ctrl_baud00_c : natural := 0
            - constant ctrl_baud01_c : natural := 1
            - constant ctrl_baud02_c : natural := 2
            - constant ctrl_baud03_c : natural := 3
            - constant ctrl_baud04_c : natural := 4
            - constant ctrl_baud05_c : natural := 5
            - constant ctrl_baud06_c : natural := 6
            - constant ctrl_baud07_c : natural := 7
            - constant ctrl_baud08_c : natural := 8
            - constant ctrl_baud09_c : natural := 9
            - constant ctrl_baud10_c : natural := 10
            - constant ctrl_baud11_c : natural := 11
            - constant ctrl_sim_en_c : natural := 12
            - constant ctrl_rx_empty_c : natural := 13
            - constant ctrl_rx_half_c : natural := 14
            - constant ctrl_rx_full_c : natural := 15
            - constant ctrl_tx_empty_c : natural := 16
            - constant ctrl_tx_half_c : natural := 17
            - constant ctrl_tx_full_c : natural := 18
            - constant ctrl_rts_en_c : natural := 20
            - constant ctrl_cts_en_c : natural := 21
            - constant ctrl_pmode0_c : natural := 22
            - constant ctrl_pmode1_c : natural := 23
            - constant ctrl_prsc0_c : natural := 24
            - constant ctrl_prsc1_c : natural := 25
            - constant ctrl_prsc2_c : natural := 26
            - constant ctrl_cts_c : natural := 27
            - constant ctrl_en_c : natural := 28
            - constant ctrl_rx_irq_c : natural := 29
            - constant ctrl_tx_irq_c : natural := 30
            - constant ctrl_tx_busy_c : natural := 31
            - constant data_lsb_c : natural := 0
            - constant data_msb_c : natural := 7
            - constant data_rx_perr_c : natural := 28
            - constant data_rx_ferr_c : natural := 29
            - constant data_rx_overr_c : natural := 30
            - constant data_rx_avail_c : natural := 31
            - signal acc_en : std_ulogic
            - signal addr : std_ulogic_vector(31 downto 0)
            - signal wren : std_ulogic
            - signal rden : std_ulogic
            - signal uart_clk : std_ulogic
            - signal num_bits : std_ulogic_vector(3 downto 0)
            - signal uart_cts_ff : std_ulogic_vector(1 downto 0)
            - signal uart_rts : std_ulogic
            - type tx_state_t is (........)
            - type tx_engine_t is record ..... end record
            - signal tx_engine : tx_engine_t
            - type rx_state_t is (........)
            - type rx_engine_t is record ..... end record
            - signal rx_engine : rx_engine_t
            - type tx_buffer_t is record ..... end record
            - signal tx_buffer : tx_buffer_t
            - type rx_buffer_t is record ..... end record
            - signal rx_buffer : rx_buffer_t
            - type irq_t is record ..... end record
            - signal rx_irq, tx_irq : irq_t
          Hierarchy:
            - rw_access: process(...)
            - tx_engine_fifo_inst: component neorv32_fifo
            - uart_tx_engine: process(...)
            - uart_rx_engine: process(...)
            - rx_engine_fifo_inst: component neorv32_fifo
            - flow_control_buffer: process(...)
            - irq_type: process(...)
            - irq_generator: process(...)
            - sim_output: process(...)
          Statements:
            ...
            ...
            ...
            ...
            ...
            ...
            ...
            ...
            ...
            ...
            ...
            ...
            ...
            ...
            ...
            ...
            ...
            ...
            ...
            ...
            ...
            ...
            ...
      Packages:
      PackageBodies:
      Configurations:
      Contexts:

Teardown

XPASS test_AllVHDLSources[/home/runner/work/extended-tests/extended-tests/NEORV32/rtl/core/neorv32_cpu_regfile.vhd] 0:00:00.250384

Started 2021-11-23 15:22:22
Ended 2021-11-23 15:22:22
Duration 0:00:00.250384
Markers
xfail
Fixtures file

Setup

Call

Captured stdout call
================================================================================
                         pyGHDL.dom - Test Application                          
================================================================================
Parsing file '/home/runner/work/extended-tests/extended-tests/NEORV32/rtl/core/neorv32_cpu_regfile.vhd'
[NOT IMPLEMENTED] Array_Subtype_Definition
[NOT IMPLEMENTED] Array_Subtype_Definition
[NOT IMPLEMENTED] Concurrent (conditional) signal assignment (label: 'None') at line 101
[NOT IMPLEMENTED] Concurrent (conditional) signal assignment (label: 'None') at line 127
libghdl processing time:  305.402 us
DOM translation time:    4858.528 us

Design:
  Libraries:
    - Name: pretty
      Entities:
        - neorv32_cpu_regfile(neorv32_cpu_regfile_rtl)
      Packages:
      Configurations:
      Contexts:
  Documents:
    - Path: '/home/runner/work/extended-tests/extended-tests/NEORV32/rtl/core/neorv32_cpu_regfile.vhd':
      Entities:
        - Name: neorv32_cpu_regfile
          File: neorv32_cpu_regfile.vhd
          Position: 52:7
          Generics:
            - CPU_EXTENSION_RISCV_E : in boolean
          Ports:
            - clk_i : in std_ulogic
            - ctrl_i : in std_ulogic_vector(ctrl_width_c - 1 downto 0)
            - mem_i : in std_ulogic_vector(data_width_c - 1 downto 0)
            - alu_i : in std_ulogic_vector(data_width_c - 1 downto 0)
            - rs1_o : out std_ulogic_vector(data_width_c - 1 downto 0)
            - rs2_o : out std_ulogic_vector(data_width_c - 1 downto 0)
          Declared:
          Statements:
          Architecures:
          - neorv32_cpu_regfile_rtl
      Architectures:
        - Name: neorv32_cpu_regfile_rtl
          File: neorv32_cpu_regfile.vhd
          Position: 69:13
          Entity: neorv32_cpu_regfile
          Declared:
            - type ???? is array(........) of .....
            - type ???? is array(........) of .....
            - signal reg_file : reg_file_t
            - signal reg_file_emb : reg_file_emb_t
            - signal rf_wdata : std_ulogic_vector(data_width_c - 1 downto 0)
            - signal rd_is_r0 : std_ulogic
            - signal dst_addr : std_ulogic_vector(4 downto 0)
            - signal opa_addr : std_ulogic_vector(4 downto 0)
            - signal opb_addr : std_ulogic_vector(4 downto 0)
            - signal rs1, rs2 : std_ulogic_vector(data_width_c - 1 downto 0)
          Hierarchy:
            - input_mux: process(...)
            - rf_access: process(...)
          Statements:
            ...
            ...
            ...
            ...
            ...
            ...
      Packages:
      PackageBodies:
      Configurations:
      Contexts:

Teardown

XPASS test_AllVHDLSources[/home/runner/work/extended-tests/extended-tests/NEORV32/rtl/core/neorv32_gpio.vhd] 0:00:00.253544

Started 2021-11-23 15:22:22
Ended 2021-11-23 15:22:22
Duration 0:00:00.253544
Markers
xfail
Fixtures file

Setup

Call

Captured stdout call
================================================================================
                         pyGHDL.dom - Test Application                          
================================================================================
Parsing file '/home/runner/work/extended-tests/extended-tests/NEORV32/rtl/core/neorv32_gpio.vhd'
[NOT IMPLEMENTED] Concurrent (conditional) signal assignment (label: 'None') at line 80
libghdl processing time:  232.902 us
DOM translation time:    3212.318 us

Design:
  Libraries:
    - Name: pretty
      Entities:
        - neorv32_gpio(neorv32_gpio_rtl)
      Packages:
      Configurations:
      Contexts:
  Documents:
    - Path: '/home/runner/work/extended-tests/extended-tests/NEORV32/rtl/core/neorv32_gpio.vhd':
      Entities:
        - Name: neorv32_gpio
          File: neorv32_gpio.vhd
          Position: 44:7
          Generics:
          Ports:
            - clk_i : in std_ulogic
            - addr_i : in std_ulogic_vector(31 downto 0)
            - rden_i : in std_ulogic
            - wren_i : in std_ulogic
            - data_i : in std_ulogic_vector(31 downto 0)
            - data_o : out std_ulogic_vector(31 downto 0)
            - ack_o : out std_ulogic
            - gpio_o : out std_ulogic_vector(63 downto 0)
            - gpio_i : in std_ulogic_vector(63 downto 0)
          Declared:
          Statements:
          Architecures:
          - neorv32_gpio_rtl
      Architectures:
        - Name: neorv32_gpio_rtl
          File: neorv32_gpio.vhd
          Position: 60:13
          Entity: neorv32_gpio
          Declared:
            - constant hi_abb_c : natural := index_size_f(io_size_c) - 1
            - constant lo_abb_c : natural := index_size_f(gpio_size_c)
            - signal acc_en : std_ulogic
            - signal addr : std_ulogic_vector(31 downto 0)
            - signal wren : std_ulogic
            - signal rden : std_ulogic
            - signal din_lo, din_hi : std_ulogic_vector(31 downto 0)
            - signal dout_lo, dout_hi : std_ulogic_vector(31 downto 0)
          Hierarchy:
            - rw_access: process(...)
          Statements:
            ...
            ...
            ...
            ...
            ...
      Packages:
      PackageBodies:
      Configurations:
      Contexts:

Teardown

XPASS test_AllVHDLSources[/home/runner/work/extended-tests/extended-tests/NEORV32/rtl/core/neorv32_bus_keeper.vhd] 0:00:00.253206

Started 2021-11-23 15:22:22
Ended 2021-11-23 15:22:22
Duration 0:00:00.253206
Markers
xfail
Fixtures file

Setup

Call

Captured stdout call
================================================================================
                         pyGHDL.dom - Test Application                          
================================================================================
Parsing file '/home/runner/work/extended-tests/extended-tests/NEORV32/rtl/core/neorv32_bus_keeper.vhd'
[NOT IMPLEMENTED] Concurrent (conditional) signal assignment (label: 'None') at line 105
libghdl processing time:  386.902 us
DOM translation time:    5200.730 us

Design:
  Libraries:
    - Name: pretty
      Entities:
        - neorv32_bus_keeper(neorv32_bus_keeper_rtl)
      Packages:
      Configurations:
      Contexts:
  Documents:
    - Path: '/home/runner/work/extended-tests/extended-tests/NEORV32/rtl/core/neorv32_bus_keeper.vhd':
      Entities:
        - Name: neorv32_bus_keeper
          File: neorv32_bus_keeper.vhd
          Position: 46:7
          Generics:
          Ports:
            - clk_i : in std_ulogic
            - rstn_i : in std_ulogic
            - addr_i : in std_ulogic_vector(31 downto 0)
            - rden_i : in std_ulogic
            - wren_i : in std_ulogic
            - data_o : out std_ulogic_vector(31 downto 0)
            - ack_o : out std_ulogic
            - err_o : out std_ulogic
            - bus_addr_i : in std_ulogic_vector(31 downto 0)
            - bus_rden_i : in std_ulogic
            - bus_wren_i : in std_ulogic
            - bus_ack_i : in std_ulogic
            - bus_err_i : in std_ulogic
            - bus_tmo_i : in std_ulogic
            - bus_ext_i : in std_ulogic
          Declared:
          Statements:
          Architecures:
          - neorv32_bus_keeper_rtl
      Architectures:
        - Name: neorv32_bus_keeper_rtl
          File: neorv32_bus_keeper.vhd
          Position: 68:13
          Entity: neorv32_bus_keeper
          Declared:
            - constant hi_abb_c : natural := index_size_f(io_size_c) - 1
            - constant lo_abb_c : natural := index_size_f(buskeeper_size_c)
            - constant ctrl_err_type_c : natural := 0
            - constant ctrl_err_flag_c : natural := 31
            - signal err_flag : std_ulogic
            - signal err_type : std_ulogic
            - signal acc_en : std_ulogic
            - signal wren : std_ulogic
            - signal rden : std_ulogic
            - type control_t is record ..... end record
            - signal control : control_t
          Hierarchy:
            - rw_access: process(...)
            - keeper_control: process(...)
          Statements:
            ...
            ...
            ...
            ...
            ...
            ...
      Packages:
      PackageBodies:
      Configurations:
      Contexts:

Teardown

XPASS test_AllVHDLSources[/home/runner/work/extended-tests/extended-tests/NEORV32/rtl/core/neorv32_gptmr.vhd] 0:00:00.257256

Started 2021-11-23 15:22:22
Ended 2021-11-23 15:22:23
Duration 0:00:00.257256
Markers
xfail
Fixtures file

Setup

Call

Captured stdout call
================================================================================
                         pyGHDL.dom - Test Application                          
================================================================================
Parsing file '/home/runner/work/extended-tests/extended-tests/NEORV32/rtl/core/neorv32_gptmr.vhd'
[NOT IMPLEMENTED] Concurrent (conditional) signal assignment (label: 'None') at line 111
[NOT IMPLEMENTED] Concurrent (conditional) signal assignment (label: 'None') at line 192
libghdl processing time:  404.302 us
DOM translation time:    7439.943 us

Design:
  Libraries:
    - Name: pretty
      Entities:
        - neorv32_gptmr(neorv32_gptmr_rtl)
      Packages:
      Configurations:
      Contexts:
  Documents:
    - Path: '/home/runner/work/extended-tests/extended-tests/NEORV32/rtl/core/neorv32_gptmr.vhd':
      Entities:
        - Name: neorv32_gptmr
          File: neorv32_gptmr.vhd
          Position: 47:7
          Generics:
          Ports:
            - clk_i : in std_ulogic
            - addr_i : in std_ulogic_vector(31 downto 0)
            - rden_i : in std_ulogic
            - wren_i : in std_ulogic
            - data_i : in std_ulogic_vector(31 downto 0)
            - data_o : out std_ulogic_vector(31 downto 0)
            - ack_o : out std_ulogic
            - clkgen_en_o : out std_ulogic
            - clkgen_i : in std_ulogic_vector(7 downto 0)
            - irq_o : out std_ulogic
          Declared:
          Statements:
          Architecures:
          - neorv32_gptmr_rtl
      Architectures:
        - Name: neorv32_gptmr_rtl
          File: neorv32_gptmr.vhd
          Position: 65:13
          Entity: neorv32_gptmr
          Declared:
            - constant hi_abb_c : natural := index_size_f(io_size_c) - 1
            - constant lo_abb_c : natural := index_size_f(gptmr_size_c)
            - constant ctrl_en_c : natural := 0
            - constant ctrl_prsc0_c : natural := 1
            - constant ctrl_prsc1_c : natural := 2
            - constant ctrl_prsc2_c : natural := 3
            - constant ctrl_mode_c : natural := 4
            - constant ctrl_alarm_c : natural := 5
            - signal ctrl : std_ulogic_vector(4 downto 0)
            - signal acc_en : std_ulogic
            - signal addr : std_ulogic_vector(31 downto 0)
            - signal wren : std_ulogic
            - signal rden : std_ulogic
            - signal gptmr_clk_en : std_ulogic
            - type timer_t is record ..... end record
            - signal timer : timer_t
            - type irq_t is record ..... end record
            - signal irq : irq_t
          Hierarchy:
            - rw_access: process(...)
            - timer_core: process(...)
            - irq_generator: process(...)
          Statements:
            ...
            ...
            ...
            ...
            ...
            ...
            ...
            ...
            ...
      Packages:
      PackageBodies:
      Configurations:
      Contexts:

Teardown

XPASS test_AllVHDLSources[/home/runner/work/extended-tests/extended-tests/NEORV32/rtl/core/neorv32_cpu_bus.vhd] 0:00:00.274319

Started 2021-11-23 15:22:22
Ended 2021-11-23 15:22:23
Duration 0:00:00.274319
Markers
xfail
Fixtures file

Setup

Call

Captured stdout call
================================================================================
                         pyGHDL.dom - Test Application                          
================================================================================
Parsing file '/home/runner/work/extended-tests/extended-tests/NEORV32/rtl/core/neorv32_cpu_bus.vhd'
[NOT IMPLEMENTED] Array_Subtype_Definition
[NOT IMPLEMENTED] Variable assignment (label: 'None') at line 282
[NOT IMPLEMENTED] Variable assignment (label: 'None') at line 282
[NOT IMPLEMENTED] Variable assignment (label: 'None') at line 283
[NOT IMPLEMENTED] Variable assignment (label: 'None') at line 283
[NOT IMPLEMENTED] Variable assignment (label: 'None') at line 285
[NOT IMPLEMENTED] Variable assignment (label: 'None') at line 285
[NOT IMPLEMENTED] Concurrent (conditional) signal assignment (label: 'None') at line 301
[NOT IMPLEMENTED] Concurrent (conditional) signal assignment (label: 'None') at line 347
[NOT IMPLEMENTED] Concurrent (conditional) signal assignment (label: 'None') at line 348
[NOT IMPLEMENTED] Concurrent (conditional) signal assignment (label: 'None') at line 435
[NOT IMPLEMENTED] Concurrent (conditional) signal assignment (label: 'None') at line 440
[NOT IMPLEMENTED] Concurrent (conditional) signal assignment (label: 'None') at line 479
[NOT IMPLEMENTED] Concurrent (conditional) signal assignment (label: 'None') at line 480
[NOT IMPLEMENTED] Concurrent (conditional) signal assignment (label: 'None') at line 504
[NOT IMPLEMENTED] Concurrent (conditional) signal assignment (label: 'None') at line 505
[NOT IMPLEMENTED] Concurrent (conditional) signal assignment (label: 'None') at line 506
libghdl processing time:  1068.706 us
DOM translation time:    17770.803 us

Design:
  Libraries:
    - Name: pretty
      Entities:
        - neorv32_cpu_bus(neorv32_cpu_bus_rtl)
      Packages:
      Configurations:
      Contexts:
  Documents:
    - Path: '/home/runner/work/extended-tests/extended-tests/NEORV32/rtl/core/neorv32_cpu_bus.vhd':
      Entities:
        - Name: neorv32_cpu_bus
          File: neorv32_cpu_bus.vhd
          Position: 44:7
          Generics:
            - CPU_EXTENSION_RISCV_A : in boolean
            - CPU_EXTENSION_RISCV_C : in boolean
            - PMP_NUM_REGIONS : in natural
            - PMP_MIN_GRANULARITY : in natural
          Ports:
            - clk_i : in std_ulogic
            - rstn_i : in std_ulogic := 0
            - ctrl_i : in std_ulogic_vector(ctrl_width_c - 1 downto 0)
            - fetch_pc_i : in std_ulogic_vector(data_width_c - 1 downto 0)
            - instr_o : out std_ulogic_vector(data_width_c - 1 downto 0)
            - i_wait_o : out std_ulogic
            - ma_instr_o : out std_ulogic
            - be_instr_o : out std_ulogic
            - addr_i : in std_ulogic_vector(data_width_c - 1 downto 0)
            - wdata_i : in std_ulogic_vector(data_width_c - 1 downto 0)
            - rdata_o : out std_ulogic_vector(data_width_c - 1 downto 0)
            - mar_o : out std_ulogic_vector(data_width_c - 1 downto 0)
            - d_wait_o : out std_ulogic
            - excl_state_o : out std_ulogic
            - ma_load_o : out std_ulogic
            - ma_store_o : out std_ulogic
            - be_load_o : out std_ulogic
            - be_store_o : out std_ulogic
            - pmp_addr_i : in pmp_addr_if_t
            - pmp_ctrl_i : in pmp_ctrl_if_t
            - i_bus_addr_o : out std_ulogic_vector(data_width_c - 1 downto 0)
            - i_bus_rdata_i : in std_ulogic_vector(data_width_c - 1 downto 0)
            - i_bus_wdata_o : out std_ulogic_vector(data_width_c - 1 downto 0)
            - i_bus_ben_o : out std_ulogic_vector(3 downto 0)
            - i_bus_we_o : out std_ulogic
            - i_bus_re_o : out std_ulogic
            - i_bus_lock_o : out std_ulogic
            - i_bus_ack_i : in std_ulogic
            - i_bus_err_i : in std_ulogic
            - i_bus_fence_o : out std_ulogic
            - d_bus_addr_o : out std_ulogic_vector(data_width_c - 1 downto 0)
            - d_bus_rdata_i : in std_ulogic_vector(data_width_c - 1 downto 0)
            - d_bus_wdata_o : out std_ulogic_vector(data_width_c - 1 downto 0)
            - d_bus_ben_o : out std_ulogic_vector(3 downto 0)
            - d_bus_we_o : out std_ulogic
            - d_bus_re_o : out std_ulogic
            - d_bus_lock_o : out std_ulogic
            - d_bus_ack_i : in std_ulogic
            - d_bus_err_i : in std_ulogic
            - d_bus_fence_o : out std_ulogic
          Declared:
          Statements:
          Architecures:
          - neorv32_cpu_bus_rtl
      Architectures:
        - Name: neorv32_cpu_bus_rtl
          File: neorv32_cpu_bus.vhd
          Position: 104:13
          Entity: neorv32_cpu_bus
          Declared:
            - constant pmp_off_mode_c : std_ulogic_vector(1 downto 0) := "00"
            - constant pmp_napot_mode_c : std_ulogic_vector(1 downto 0) := "11"
            - constant pmp_g_c : natural := index_size_f(PMP_MIN_GRANULARITY)
            - constant pmp_cfg_r_c : natural := 0
            - constant pmp_cfg_w_c : natural := 1
            - constant pmp_cfg_x_c : natural := 2
            - constant pmp_cfg_al_c : natural := 3
            - constant pmp_cfg_ah_c : natural := 4
            - constant pmp_cfg_l_c : natural := 7
            - signal mar, mdo, mdi : std_ulogic_vector(data_width_c - 1 downto 0)
            - signal d_bus_wdata : std_ulogic_vector(data_width_c - 1 downto 0)
            - signal d_bus_rdata : std_ulogic_vector(data_width_c - 1 downto 0)
            - signal rdata_align : std_ulogic_vector(data_width_c - 1 downto 0)
            - signal d_bus_ben : std_ulogic_vector(3 downto 0)
            - signal d_misaligned, i_misaligned : std_ulogic
            - type bus_arbiter_t is record ..... end record
            - signal i_arbiter, d_arbiter : bus_arbiter_t
            - signal exclusive_lock : std_ulogic
            - signal exclusive_lock_status : std_ulogic_vector(data_width_c - 1 downto 0)
            - type ???? is array(........) of .....
            - type pmp_t is record ..... end record
            - signal pmp : pmp_t
            - signal d_bus_we, d_bus_we_buf : std_ulogic
            - signal d_bus_re, d_bus_re_buf : std_ulogic
            - signal i_bus_re, i_bus_re_buf : std_ulogic
            - signal if_pmp_fault : std_ulogic
            - signal ld_pmp_fault : std_ulogic
            - signal st_pmp_fault : std_ulogic
          Hierarchy:
            - mem_adr_reg: process(...)
            - misaligned_d_check: process(...)
            - mem_do_reg: process(...)
            - byte_enable: process(...)
            - mem_di_reg: process(...)
            - read_align: process(...)
            - data_access_arbiter: process(...)
            - pmp_dbus_buffer: process(...)
            - exclusive_access_controller: process(...)
            - ifetch_arbiter: process(...)
            - pmp_ibus_buffer: process(...)
            - pmp_masks: process(...)
            - pmp_address_check: for r in 0 to PMP_NUM_REGIONS - 1 generate
            - pmp_check_permission: process(...)
          Statements:
            ...
            ...
            ...
            ...
            ...
            ...
            ...
            ...
            ...
            ...
            ...
            ...
            ...
            ...
            ...
            ...
            ...
            ...
            ...
            ...
            ...
            ...
            ...
            ...
            ...
            ...
            ...
            ...
            ...
            ...
            ...
            ...
            ...
            ...
            ...
            ...
            ...
            ...
            ...
            ...
            ...
            ...
            ...
            ...
      Packages:
      PackageBodies:
      Configurations:
      Contexts:

Teardown

XPASS test_AllVHDLSources[/home/runner/work/extended-tests/extended-tests/NEORV32/rtl/core/neorv32_cpu_cp_bitmanip.vhd] 0:00:00.315819

Started 2021-11-23 15:22:23
Ended 2021-11-23 15:22:23
Duration 0:00:00.315819
Markers
xfail
Fixtures file

Setup

Call

Captured stdout call
================================================================================
                         pyGHDL.dom - Test Application                          
================================================================================
Parsing file '/home/runner/work/extended-tests/extended-tests/NEORV32/rtl/core/neorv32_cpu_cp_bitmanip.vhd'
[NOT IMPLEMENTED] Array_Subtype_Definition
[NOT IMPLEMENTED] Array_Subtype_Definition
[NOT IMPLEMENTED] Concurrent (conditional) signal assignment (label: 'None') at line 161
[NOT IMPLEMENTED] Concurrent (conditional) signal assignment (label: 'None') at line 162
[NOT IMPLEMENTED] Concurrent (conditional) signal assignment (label: 'None') at line 163
[NOT IMPLEMENTED] Concurrent (conditional) signal assignment (label: 'None') at line 165
[NOT IMPLEMENTED] Concurrent (conditional) signal assignment (label: 'None') at line 166
[NOT IMPLEMENTED] Concurrent (conditional) signal assignment (label: 'None') at line 167
[NOT IMPLEMENTED] Concurrent (conditional) signal assignment (label: 'None') at line 169
[NOT IMPLEMENTED] Concurrent (conditional) signal assignment (label: 'None') at line 171
[NOT IMPLEMENTED] Concurrent (conditional) signal assignment (label: 'None') at line 172
[NOT IMPLEMENTED] Concurrent (conditional) signal assignment (label: 'None') at line 173
[NOT IMPLEMENTED] Concurrent (conditional) signal assignment (label: 'None') at line 174
[NOT IMPLEMENTED] Concurrent (conditional) signal assignment (label: 'None') at line 175
[NOT IMPLEMENTED] Concurrent (conditional) signal assignment (label: 'None') at line 176
[NOT IMPLEMENTED] Concurrent (conditional) signal assignment (label: 'None') at line 177
[NOT IMPLEMENTED] Concurrent (conditional) signal assignment (label: 'None') at line 178
[NOT IMPLEMENTED] Concurrent (conditional) signal assignment (label: 'None') at line 181
[NOT IMPLEMENTED] Concurrent (conditional) signal assignment (label: 'None') at line 182
[NOT IMPLEMENTED] Concurrent (conditional) signal assignment (label: 'None') at line 183
[NOT IMPLEMENTED] Variable assignment (label: 'None') at line 278
[NOT IMPLEMENTED] Variable assignment (label: 'None') at line 366
[NOT IMPLEMENTED] Variable assignment (label: 'None') at line 367
[NOT IMPLEMENTED] Variable assignment (label: 'None') at line 369
[NOT IMPLEMENTED] Concurrent (conditional) signal assignment (label: 'None') at line 392
[NOT IMPLEMENTED] Concurrent (conditional) signal assignment (label: 'None') at line 424
[NOT IMPLEMENTED] Concurrent (conditional) signal assignment (label: 'None') at line 425
[NOT IMPLEMENTED] Concurrent (conditional) signal assignment (label: 'None') at line 426
[NOT IMPLEMENTED] Concurrent (conditional) signal assignment (label: 'None') at line 427
[NOT IMPLEMENTED] Concurrent (conditional) signal assignment (label: 'None') at line 429
[NOT IMPLEMENTED] Concurrent (conditional) signal assignment (label: 'None') at line 430
[NOT IMPLEMENTED] Concurrent (conditional) signal assignment (label: 'None') at line 432
[NOT IMPLEMENTED] Concurrent (conditional) signal assignment (label: 'None') at line 433
[NOT IMPLEMENTED] Concurrent (conditional) signal assignment (label: 'None') at line 434
[NOT IMPLEMENTED] Concurrent (conditional) signal assignment (label: 'None') at line 435
[NOT IMPLEMENTED] Concurrent (conditional) signal assignment (label: 'None') at line 436
[NOT IMPLEMENTED] Concurrent (conditional) signal assignment (label: 'None') at line 437
[NOT IMPLEMENTED] Concurrent (conditional) signal assignment (label: 'None') at line 438
[NOT IMPLEMENTED] Concurrent (conditional) signal assignment (label: 'None') at line 440
libghdl processing time:  1322.608 us
DOM translation time:    36429.110 us

Design:
  Libraries:
    - Name: pretty
      Entities:
        - neorv32_cpu_cp_bitmanip(neorv32_cpu_cp_bitmanip_rtl)
      Packages:
      Configurations:
      Contexts:
  Documents:
    - Path: '/home/runner/work/extended-tests/extended-tests/NEORV32/rtl/core/neorv32_cpu_cp_bitmanip.vhd':
      Entities:
        - Name: neorv32_cpu_cp_bitmanip
          File: neorv32_cpu_cp_bitmanip.vhd
          Position: 51:7
          Generics:
            - FAST_SHIFT_EN : in boolean
          Ports:
            - clk_i : in std_ulogic
            - rstn_i : in std_ulogic
            - ctrl_i : in std_ulogic_vector(ctrl_width_c - 1 downto 0)
            - start_i : in std_ulogic
            - cmp_i : in std_ulogic_vector(1 downto 0)
            - rs1_i : in std_ulogic_vector(data_width_c - 1 downto 0)
            - rs2_i : in std_ulogic_vector(data_width_c - 1 downto 0)
            - shamt_i : in std_ulogic_vector(index_size_f(data_width_c) - 1 downto 0)
            - res_o : out std_ulogic_vector(data_width_c - 1 downto 0)
            - valid_o : out std_ulogic
          Declared:
          Statements:
          Architecures:
          - neorv32_cpu_cp_bitmanip_rtl
      Architectures:
        - Name: neorv32_cpu_cp_bitmanip_rtl
          File: neorv32_cpu_cp_bitmanip.vhd
          Position: 72:13
          Entity: neorv32_cpu_cp_bitmanip
          Declared:
            - constant zbb_en_c : boolean := true
            - constant zba_en_c : boolean := true
            - constant op_andn_c : natural := 0
            - constant op_orn_c : natural := 1
            - constant op_xnor_c : natural := 2
            - constant op_clz_c : natural := 3
            - constant op_ctz_c : natural := 4
            - constant op_cpop_c : natural := 5
            - constant op_max_c : natural := 6
            - constant op_min_c : natural := 7
            - constant op_sextb_c : natural := 8
            - constant op_sexth_c : natural := 9
            - constant op_zexth_c : natural := 10
            - constant op_rol_c : natural := 11
            - constant op_ror_c : natural := 12
            - constant op_orcb_c : natural := 13
            - constant op_rev8_c : natural := 14
            - constant op_sh1add_c : natural := 15
            - constant op_sh2add_c : natural := 16
            - constant op_sh3add_c : natural := 17
            - constant op_width_c : natural := 18
            - type ctrl_state_t is (........)
            - signal ctrl_state : ctrl_state_t
            - signal cmd, cmd_buf : std_ulogic_vector(op_width_c - 1 downto 0)
            - signal valid : std_ulogic
            - signal rs1_reg : std_ulogic_vector(data_width_c - 1 downto 0)
            - signal rs2_reg : std_ulogic_vector(data_width_c - 1 downto 0)
            - signal sha_reg : std_ulogic_vector(index_size_f(data_width_c) - 1 downto 0)
            - signal less_ff : std_ulogic
            - type shifter_t is record ..... end record
            - signal shifter : shifter_t
            - type ???? is array(........) of .....
            - signal bs_level : bs_level_t
            - type ???? is array(........) of .....
            - signal res_int, res_out : res_t
            - signal adder_core : std_ulogic_vector(data_width_c - 1 downto 0)
          Hierarchy:
            - coprocessor_ctrl: process(...)
            - serial_shifter: if (FAST_SHIFT_EN = false) generate
                - shifter_unit: process(...)
            - serial_shifter_ctrl: if (FAST_SHIFT_EN = false) generate
                - shifter_unit_ctrl: process(...)
            - barrel_shifter_async_sync: if (FAST_SHIFT_EN = true) generate
                - shifter_unit_fast: process(...)
            - barrel_shifter_async: if (FAST_SHIFT_EN = true) generate
                - shifter_unit_async: process(...)
            - shift_adder: process(...)
            - or_combine_gen: for i in 0 to (data_width_c / 8) - 1 generate
            - output_gate: process(...)
          Statements:
            ...
            ...
            ...
            ...
            ...
            ...
            ...
            ...
            ...
            ...
            ...
            ...
            ...
            ...
            ...
            ...
            ...
            ...
            ...
            ...
            ...
            ...
            ...
            ...
            ...
            ...
            ...
            ...
            ...
            ...
            ...
            ...
            ...
            ...
            ...
      Packages:
      PackageBodies:
      Configurations:
      Contexts:

Teardown

XPASS test_AllVHDLSources[/home/runner/work/extended-tests/extended-tests/NEORV32/rtl/core/neorv32_mtime.vhd] 0:00:00.309053

Started 2021-11-23 15:22:23
Ended 2021-11-23 15:22:23
Duration 0:00:00.309053
Markers
xfail
Fixtures file

Setup

Call

Captured stdout call
================================================================================
                         pyGHDL.dom - Test Application                          
================================================================================
Parsing file '/home/runner/work/extended-tests/extended-tests/NEORV32/rtl/core/neorv32_mtime.vhd'
[NOT IMPLEMENTED] Concurrent (conditional) signal assignment (label: 'None') at line 96
[NOT IMPLEMENTED] Concurrent (conditional) signal assignment (label: 'None') at line 176
[NOT IMPLEMENTED] Concurrent (conditional) signal assignment (label: 'None') at line 177
[NOT IMPLEMENTED] Concurrent (conditional) signal assignment (label: 'None') at line 178
libghdl processing time:  578.503 us
DOM translation time:    7010.840 us

Design:
  Libraries:
    - Name: pretty
      Entities:
        - neorv32_mtime(neorv32_mtime_rtl)
      Packages:
      Configurations:
      Contexts:
  Documents:
    - Path: '/home/runner/work/extended-tests/extended-tests/NEORV32/rtl/core/neorv32_mtime.vhd':
      Entities:
        - Name: neorv32_mtime
          File: neorv32_mtime.vhd
          Position: 45:7
          Generics:
          Ports:
            - clk_i : in std_ulogic
            - addr_i : in std_ulogic_vector(31 downto 0)
            - rden_i : in std_ulogic
            - wren_i : in std_ulogic
            - data_i : in std_ulogic_vector(31 downto 0)
            - data_o : out std_ulogic_vector(31 downto 0)
            - ack_o : out std_ulogic
            - time_o : out std_ulogic_vector(63 downto 0)
            - irq_o : out std_ulogic
          Declared:
          Statements:
          Architecures:
          - neorv32_mtime_rtl
      Architectures:
        - Name: neorv32_mtime_rtl
          File: neorv32_mtime.vhd
          Position: 62:13
          Entity: neorv32_mtime
          Declared:
            - constant hi_abb_c : natural := index_size_f(io_size_c) - 1
            - constant lo_abb_c : natural := index_size_f(mtime_size_c)
            - signal acc_en : std_ulogic
            - signal addr : std_ulogic_vector(31 downto 0)
            - signal wren : std_ulogic
            - signal rden : std_ulogic
            - signal mtime_lo_we : std_ulogic
            - signal mtime_hi_we : std_ulogic
            - signal mtimecmp_lo : std_ulogic_vector(31 downto 0)
            - signal mtimecmp_hi : std_ulogic_vector(31 downto 0)
            - signal mtime_lo : std_ulogic_vector(31 downto 0)
            - signal mtime_lo_nxt : std_ulogic_vector(32 downto 0)
            - signal mtime_lo_ovfl : std_ulogic_vector(0 downto 0)
            - signal mtime_hi : std_ulogic_vector(31 downto 0)
            - signal cmp_lo_ge : std_ulogic
            - signal cmp_lo_ge_ff : std_ulogic
            - signal cmp_hi_eq : std_ulogic
            - signal cmp_hi_gt : std_ulogic
          Hierarchy:
            - wr_access: process(...)
            - rd_access: process(...)
            - cmp_sync: process(...)
          Statements:
            ...
            ...
            ...
            ...
            ...
            ...
            ...
            ...
      Packages:
      PackageBodies:
      Configurations:
      Contexts:

Teardown

XPASS test_AllVHDLSources[/home/runner/work/extended-tests/extended-tests/NEORV32/rtl/core/neorv32_sysinfo.vhd] 0:00:00.348201

Started 2021-11-23 15:22:23
Ended 2021-11-23 15:22:23
Duration 0:00:00.348201
Markers
xfail
Fixtures file

Setup

Call

Captured stdout call
================================================================================
                         pyGHDL.dom - Test Application                          
================================================================================
Parsing file '/home/runner/work/extended-tests/extended-tests/NEORV32/rtl/core/neorv32_sysinfo.vhd'
[NOT IMPLEMENTED] Array_Subtype_Definition
[NOT IMPLEMENTED] Concurrent (conditional) signal assignment (label: 'None') at line 126
[NOT IMPLEMENTED] Concurrent (conditional) signal assignment (label: 'None') at line 189
[NOT IMPLEMENTED] Concurrent (conditional) signal assignment (label: 'None') at line 190
[NOT IMPLEMENTED] Concurrent (conditional) signal assignment (label: 'None') at line 191
[NOT IMPLEMENTED] Concurrent (conditional) signal assignment (label: 'None') at line 192
[NOT IMPLEMENTED] Concurrent (conditional) signal assignment (label: 'None') at line 206
[NOT IMPLEMENTED] Concurrent (conditional) signal assignment (label: 'None') at line 209
libghdl processing time:  652.704 us
DOM translation time:    9580.555 us

Design:
  Libraries:
    - Name: pretty
      Entities:
        - neorv32_sysinfo(neorv32_sysinfo_rtl)
      Packages:
      Configurations:
      Contexts:
  Documents:
    - Path: '/home/runner/work/extended-tests/extended-tests/NEORV32/rtl/core/neorv32_sysinfo.vhd':
      Entities:
        - Name: neorv32_sysinfo
          File: neorv32_sysinfo.vhd
          Position: 45:7
          Generics:
            - CLOCK_FREQUENCY : in natural
            - INT_BOOTLOADER_EN : in boolean
            - CPU_EXTENSION_RISCV_Zfinx : in boolean
            - CPU_EXTENSION_RISCV_Zicsr : in boolean
            - CPU_EXTENSION_RISCV_Zicntr : in boolean
            - CPU_EXTENSION_RISCV_Zihpm : in boolean
            - CPU_EXTENSION_RISCV_Zifencei : in boolean
            - CPU_EXTENSION_RISCV_Zmmul : in boolean
            - CPU_EXTENSION_RISCV_DEBUG : in boolean
            - FAST_MUL_EN : in boolean
            - FAST_SHIFT_EN : in boolean
            - CPU_CNT_WIDTH : in natural
            - PMP_NUM_REGIONS : in natural
            - MEM_INT_IMEM_EN : in boolean
            - MEM_INT_IMEM_SIZE : in natural
            - MEM_INT_DMEM_EN : in boolean
            - MEM_INT_DMEM_SIZE : in natural
            - ICACHE_EN : in boolean
            - ICACHE_NUM_BLOCKS : in natural
            - ICACHE_BLOCK_SIZE : in natural
            - ICACHE_ASSOCIATIVITY : in natural
            - MEM_EXT_EN : in boolean
            - MEM_EXT_BIG_ENDIAN : in boolean
            - ON_CHIP_DEBUGGER_EN : in boolean
            - IO_GPIO_EN : in boolean
            - IO_MTIME_EN : in boolean
            - IO_UART0_EN : in boolean
            - IO_UART1_EN : in boolean
            - IO_SPI_EN : in boolean
            - IO_TWI_EN : in boolean
            - IO_PWM_NUM_CH : in natural
            - IO_WDT_EN : in boolean
            - IO_TRNG_EN : in boolean
            - IO_CFS_EN : in boolean
            - IO_SLINK_EN : in boolean
            - IO_NEOLED_EN : in boolean
            - IO_XIRQ_NUM_CH : in natural
            - IO_GPTMR_EN : in boolean
          Ports:
            - clk_i : in std_ulogic
            - addr_i : in std_ulogic_vector(31 downto 0)
            - rden_i : in std_ulogic
            - data_o : out std_ulogic_vector(31 downto 0)
            - ack_o : out std_ulogic
          Declared:
          Statements:
          Architecures:
          - neorv32_sysinfo_rtl
      Architectures:
        - Name: neorv32_sysinfo_rtl
          File: neorv32_sysinfo.vhd
          Position: 106:13
          Entity: neorv32_sysinfo
          Declared:
            - constant hi_abb_c : natural := index_size_f(io_size_c) - 1
            - constant lo_abb_c : natural := index_size_f(sysinfo_size_c)
            - signal acc_en : std_ulogic
            - signal addr : std_ulogic_vector(31 downto 0)
            - signal rden : std_ulogic
            - signal info_addr : std_ulogic_vector(2 downto 0)
            - type ???? is array(........) of .....
            - signal sysinfo_mem : info_mem_t
          Hierarchy:
            - read_access: process(...)
          Statements:
            ...
            ...
            ...
            ...
            ...
            ...
            ...
            ...
            ...
            ...
            ...
            ...
            ...
            ...
            ...
            ...
            ...
            ...
            ...
            ...
            ...
            ...
            ...
            ...
            ...
            ...
            ...
            ...
            ...
            ...
            ...
            ...
            ...
            ...
            ...
            ...
            ...
            ...
            ...
            ...
            ...
            ...
            ...
            ...
            ...
            ...
            ...
            ...
      Packages:
      PackageBodies:
      Configurations:
      Contexts:

Teardown

XPASS test_AllVHDLSources[/home/runner/work/extended-tests/extended-tests/NEORV32/rtl/core/neorv32_trng.vhd] 0:00:00.335657

Started 2021-11-23 15:22:23
Ended 2021-11-23 15:22:23
Duration 0:00:00.335657
Markers
xfail
Fixtures file

Setup

Call

Captured stdout call
================================================================================
                         pyGHDL.dom - Test Application                          
================================================================================
Parsing file '/home/runner/work/extended-tests/extended-tests/NEORV32/rtl/core/neorv32_trng.vhd'
[NOT IMPLEMENTED] Concurrent (conditional) signal assignment (label: 'None') at line 111
[NOT IMPLEMENTED] Variable assignment (label: 'None') at line 338
[NOT IMPLEMENTED] Variable assignment (label: 'None') at line 361
[NOT IMPLEMENTED] Concurrent (conditional) signal assignment (label: 'None') at line 399
[NOT IMPLEMENTED] Concurrent (conditional) signal assignment (label: 'None') at line 524
libghdl processing time:  837.505 us
DOM translation time:    12164.470 us

Design:
  Libraries:
    - Name: pretty
      Entities:
        - neorv32_trng(neorv32_trng_rtl)
        - neoTRNG(neoTRNG_rtl)
        - neoTRNG_cell(neoTRNG_cell_rtl)
      Packages:
      Configurations:
      Contexts:
  Documents:
    - Path: '/home/runner/work/extended-tests/extended-tests/NEORV32/rtl/core/neorv32_trng.vhd':
      Entities:
        - Name: neorv32_trng
          File: neorv32_trng.vhd
          Position: 45:7
          Generics:
          Ports:
            - clk_i : in std_ulogic
            - addr_i : in std_ulogic_vector(31 downto 0)
            - rden_i : in std_ulogic
            - wren_i : in std_ulogic
            - data_i : in std_ulogic_vector(31 downto 0)
            - data_o : out std_ulogic_vector(31 downto 0)
            - ack_o : out std_ulogic
          Declared:
          Statements:
          Architecures:
          - neorv32_trng_rtl
        - Name: neoTRNG
          File: neorv32_trng.vhd
          Position: 234:7
          Generics:
            - NUM_CELLS : in natural
            - NUM_INV_START : in natural
            - NUM_INV_INC : in natural
            - NUM_INV_DELAY : in natural
          Ports:
            - clk_i : in std_ulogic
            - enable_i : in std_ulogic
            - data_o : out std_ulogic_vector(7 downto 0)
            - valid_o : out std_ulogic
          Declared:
          Statements:
          Architecures:
          - neoTRNG_rtl
        - Name: neoTRNG_cell
          File: neorv32_trng.vhd
          Position: 459:7
          Generics:
            - NUM_INV_S : in natural
            - NUM_INV_L : in natural
          Ports:
            - clk_i : in std_ulogic
            - select_i : in std_ulogic
            - enable_i : in std_ulogic
            - enable_o : out std_ulogic
            - data_o : out std_ulogic
          Declared:
          Statements:
          Architecures:
          - neoTRNG_cell_rtl
      Architectures:
        - Name: neorv32_trng_rtl
          File: neorv32_trng.vhd
          Position: 58:13
          Entity: neorv32_trng
          Declared:
            - constant num_cells_c : natural := 3
            - constant num_inv_start_c : natural := 3
            - constant num_inv_inc_c : natural := 2
            - constant num_inv_delay_c : natural := 2
            - constant ctrl_data_lsb_c : natural := 0
            - constant ctrl_data_msb_c : natural := 7
            - constant ctrl_en_c : natural := 30
            - constant ctrl_valid_c : natural := 31
            - constant hi_abb_c : natural := index_size_f(io_size_c) - 1
            - constant lo_abb_c : natural := index_size_f(trng_size_c)
            - signal acc_en : std_ulogic
            - signal wren : std_ulogic
            - signal rden : std_ulogic
            - Component: neoTRNG
              Generics:
                - NUM_CELLS : in natural
                - NUM_INV_START : in natural
                - NUM_INV_INC : in natural
                - NUM_INV_DELAY : in natural
              Ports:
                - clk_i : in std_ulogic
                - enable_i : in std_ulogic
                - data_o : out std_ulogic_vector(7 downto 0)
                - valid_o : out std_ulogic
            - signal trng_data : std_ulogic_vector(7 downto 0)
            - signal trng_valid : std_ulogic
            - signal enable : std_ulogic
            - signal valid : std_ulogic
            - signal rnd_reg : std_ulogic_vector(7 downto 0)
          Hierarchy:
            - rw_access: process(...)
            - neotrng_inst: component neoTRNG
          Statements:
            ...
            ...
            ...
            ...
        - Name: neoTRNG_rtl
          File: neorv32_trng.vhd
          Position: 249:13
          Entity: neoTRNG
          Declared:
            - Component: neoTRNG_cell
              Generics:
                - NUM_INV_S : in natural
                - NUM_INV_L : in natural
              Ports:
                - clk_i : in std_ulogic
                - select_i : in std_ulogic
                - enable_i : in std_ulogic
                - enable_o : out std_ulogic
                - data_o : out std_ulogic
            - type cell_array_t is record ..... end record
            - signal cell_array : cell_array_t
            - signal rnd_bit : std_ulogic
            - type debiasing_t is record ..... end record
            - signal deb : debiasing_t
            - type ctrl_t is record ..... end record
            - signal ctrl : ctrl_t
          Hierarchy:
            - neotrng_cell_inst: for i in 0 to NUM_CELLS - 1 generate
                - neotrng_cell_inst_i: component neoTRNG_cell
            - cell_xor: process(...)
            - debiasing_sync: process(...)
            - debiasing_comb: process(...)
            - control_unit: process(...)
          Statements:
            ...
            ...
            ...
            ...
            ...
            ...
            ...
            ...
            ...
            ...
            ...
            ...
            ...
            ...
        - Name: neoTRNG_cell_rtl
          File: neorv32_trng.vhd
          Position: 473:13
          Entity: neoTRNG_cell
          Declared:
            - signal inv_chain_s : std_ulogic_vector(NUM_INV_S - 1 downto 0)
            - signal inv_chain_l : std_ulogic_vector(NUM_INV_L - 1 downto 0)
            - signal feedback : std_ulogic
            - signal enable_sreg_s : std_ulogic_vector(NUM_INV_S - 1 downto 0)
            - signal enable_sreg_l : std_ulogic_vector(NUM_INV_L - 1 downto 0)
            - signal sync_ff : std_ulogic_vector(1 downto 0)
          Hierarchy:
            - ring_osc_short: process(...)
            - ring_osc_long: process(...)
            - ctrl_unit: process(...)
          Statements:
            ...
            ...
            ...
            ...
            ...
      Packages:
      PackageBodies:
      Configurations:
      Contexts:

Teardown

XPASS test_AllVHDLSources[/home/runner/work/extended-tests/extended-tests/NEORV32/rtl/core/neorv32_debug_dm.vhd] 0:00:00.280896

Started 2021-11-23 15:22:23
Ended 2021-11-23 15:22:23
Duration 0:00:00.280896
Markers
xfail
Fixtures file

Setup

Call

Captured stdout call
================================================================================
                         pyGHDL.dom - Test Application                          
================================================================================
Parsing file '/home/runner/work/extended-tests/extended-tests/NEORV32/rtl/core/neorv32_debug_dm.vhd'
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Array_Subtype_Definition
[NOT IMPLEMENTED] Array_Subtype_Definition
[NOT IMPLEMENTED] Array_Subtype_Definition
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Array_Subtype_Definition
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Concurrent (conditional) signal assignment (label: 'None') at line 404
[NOT IMPLEMENTED] Concurrent (conditional) signal assignment (label: 'None') at line 509
[NOT IMPLEMENTED] Concurrent (conditional) signal assignment (label: 'None') at line 521
[NOT IMPLEMENTED] Concurrent (conditional) signal assignment (label: 'None') at line 522
[NOT IMPLEMENTED] Concurrent (conditional) signal assignment (label: 'None') at line 669
libghdl processing time:  1623.109 us
DOM translation time:    28924.867 us

Design:
  Libraries:
    - Name: pretty
      Entities:
        - neorv32_debug_dm(neorv32_debug_dm_rtl)
      Packages:
      Configurations:
      Contexts:
  Documents:
    - Path: '/home/runner/work/extended-tests/extended-tests/NEORV32/rtl/core/neorv32_debug_dm.vhd':
      Entities:
        - Name: neorv32_debug_dm
          File: neorv32_debug_dm.vhd
          Position: 58:7
          Generics:
          Ports:
            - clk_i : in std_ulogic
            - rstn_i : in std_ulogic
            - dmi_rstn_i : in std_ulogic
            - dmi_req_valid_i : in std_ulogic
            - dmi_req_ready_o : out std_ulogic
            - dmi_req_addr_i : in std_ulogic_vector(6 downto 0)
            - dmi_req_op_i : in std_ulogic
            - dmi_req_data_i : in std_ulogic_vector(31 downto 0)
            - dmi_resp_valid_o : out std_ulogic
            - dmi_resp_ready_i : in std_ulogic
            - dmi_resp_data_o : out std_ulogic_vector(31 downto 0)
            - dmi_resp_err_o : out std_ulogic
            - cpu_addr_i : in std_ulogic_vector(31 downto 0)
            - cpu_rden_i : in std_ulogic
            - cpu_wren_i : in std_ulogic
            - cpu_data_i : in std_ulogic_vector(31 downto 0)
            - cpu_data_o : out std_ulogic_vector(31 downto 0)
            - cpu_ack_o : out std_ulogic
            - cpu_ndmrstn_o : out std_ulogic
            - cpu_halt_req_o : out std_ulogic
          Declared:
          Statements:
          Architecures:
          - neorv32_debug_dm_rtl
      Architectures:
        - Name: neorv32_debug_dm_rtl
          File: neorv32_debug_dm.vhd
          Position: 87:13
          Entity: neorv32_debug_dm
          Declared:
            - constant nscratch_c : std_ulogic_vector(3 downto 0) := "0001"
            - constant dataaccess_c : std_ulogic := 1
            - constant datasize_c : std_ulogic_vector(3 downto 0) := "0001"
            - constant dataaddr_c : std_ulogic_vector(11 downto 0) := dm_data_base_c(11 downto 0)
            - constant addr_data0_c : std_ulogic_vector(6 downto 0) := "000" & None
            - constant addr_dmcontrol_c : std_ulogic_vector(6 downto 0) := "001" & None
            - constant addr_dmstatus_c : std_ulogic_vector(6 downto 0) := "001" & None
            - constant addr_hartinfo_c : std_ulogic_vector(6 downto 0) := "001" & None
            - constant addr_abstractcs_c : std_ulogic_vector(6 downto 0) := "001" & None
            - constant addr_command_c : std_ulogic_vector(6 downto 0) := "001" & None
            - constant addr_abstractauto_c : std_ulogic_vector(6 downto 0) := "001" & None
            - constant addr_nextdm_c : std_ulogic_vector(6 downto 0) := "001" & None
            - constant addr_progbuf0_c : std_ulogic_vector(6 downto 0) := "010" & None
            - constant addr_progbuf1_c : std_ulogic_vector(6 downto 0) := "010" & None
            - constant addr_sbcs_c : std_ulogic_vector(6 downto 0) := "011" & None
            - constant addr_haltsum0_c : std_ulogic_vector(6 downto 0) := "100" & None
            - constant instr_nop_c : std_ulogic_vector(31 downto 0) := None
            - constant instr_lw_c : std_ulogic_vector(31 downto 0) := None
            - constant instr_sw_c : std_ulogic_vector(31 downto 0) := None
            - constant instr_ebreak_c : std_ulogic_vector(31 downto 0) := None
            - type dm_ctrl_state_t is (........)
            - type dm_ctrl_t is record ..... end record
            - signal dm_ctrl : dm_ctrl_t
            - type ???? is array(........) of .....
            - type dm_reg_t is record ..... end record
            - signal dm_reg : dm_reg_t
            - type ???? is array(........) of .....
            - signal cpu_progbuf : cpu_progbuf_t
            - type dci_t is record ..... end record
            - signal dci : dci_t
            - constant hi_abb_c : natural := 31
            - constant lo_abb_c : natural := index_size_f(dm_size_c)
            - constant sreg_halt_ack_c : natural := 0
            - constant sreg_resume_req_c : natural := 1
            - constant sreg_resume_ack_c : natural := 2
            - constant sreg_execute_req_c : natural := 3
            - constant sreg_execute_ack_c : natural := 4
            - constant sreg_exception_ack_c : natural := 5
            - type ???? is array(........) of .....
            - constant code_rom_file : code_rom_file_t := (0 => None, 1 => None, 2 => None, 3 => None, 4 => None, 5 => None, 6 => None, 7 => None, 8 => None, 9 => None, 10 => None, 11 => None, 12 => None, 13 => None, 14 => None, 15 => None, 16 => None, 17 => None, 18 => None, 19 => None, 20 => None, 21 => None, 22 => None, 23 => None, 24 => None, others => None)
            - signal acc_en : std_ulogic
            - signal rden : std_ulogic
            - signal wren : std_ulogic
            - signal maddr : std_ulogic_vector(1 downto 0)
            - signal data_buf : std_ulogic_vector(31 downto 0)
            - type ???? is array(........) of .....
            - signal prog_buf : prog_buf_t
          Hierarchy:
            - dm_controller: process(...)
            - dmi_write_access: process(...)
            - dmi_read_access: process(...)
            - write_access: process(...)
            - read_access: process(...)
          Statements:
            ...
            ...
            ...
            ...
            ...
            ...
            ...
            ...
            ...
            ...
            ...
            ...
            ...
            ...
            ...
            ...
            ...
      Packages:
      PackageBodies:
      Configurations:
      Contexts:

Teardown

XPASS test_AllVHDLSources[/home/runner/work/extended-tests/extended-tests/NEORV32/rtl/core/neorv32_package.vhd] 0:00:00.354567

Started 2021-11-23 15:22:23
Ended 2021-11-23 15:22:24
Duration 0:00:00.354567
Markers
xfail
Fixtures file

Setup

Call

Captured stdout call
================================================================================
                         pyGHDL.dom - Test Application                          
================================================================================
Parsing file '/home/runner/work/extended-tests/extended-tests/NEORV32/rtl/core/neorv32_package.vhd'
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libghdl processing time:  5110.330 us
DOM translation time:    80041.661 us

Design:
  Libraries:
    - Name: pretty
      Entities:
      Packages:
        - neorv32_package
      Configurations:
      Contexts:
  Documents:
    - Path: '/home/runner/work/extended-tests/extended-tests/NEORV32/rtl/core/neorv32_package.vhd':
      Entities:
      Architectures:
      Packages:
        - Name: neorv32_package
          File: neorv32_package.vhd
          Position: 39:8
          Declared:
          - constant ispace_base_c : std_ulogic_vector(31 downto 0) := None
          - constant dspace_base_c : std_ulogic_vector(31 downto 0) := None
          - constant dedicated_reset_c : boolean := false
          - constant cp_timeout_en_c : boolean := false
          - constant pmp_num_regions_critical_c : natural := 8
          - constant max_proc_int_response_time_c : natural := 15
          - constant jtag_tap_idcode_version_c : std_ulogic_vector(3 downto 0) := None
          - constant jtag_tap_idcode_partid_c : std_ulogic_vector(15 downto 0) := None
          - constant jtag_tap_idcode_manid_c : std_ulogic_vector(10 downto 0) := "00000000000"
          - constant data_width_c : natural := 32
          - constant hw_version_c : std_ulogic_vector(31 downto 0) := None
          - constant archid_c : natural := 19
          - type ???? is array(........) of .....
          - type ???? is array(........) of .....
          - type ???? is array(........) of .....
          - type ???? is array(........) of .....
          - type ???? is array(........) of .....
          - type mem32_t is array(........) of .....
          - type mem8_t is array(........) of .....
          - constant def_rst_val_c : std_ulogic := cond_sel_stdulogic_f(dedicated_reset_c, 0, -)
          - constant imem_base_c : std_ulogic_vector(data_width_c - 1 downto 0) := ispace_base_c
          - constant dmem_base_c : std_ulogic_vector(data_width_c - 1 downto 0) := dspace_base_c
          - constant boot_rom_base_c : std_ulogic_vector(data_width_c - 1 downto 0) := None
          - constant boot_rom_max_size_c : natural := 32 * 1024
          - constant dm_base_c : std_ulogic_vector(data_width_c - 1 downto 0) := None
          - constant dm_size_c : natural := 4 * 32 * 4
          - constant dm_code_base_c : std_ulogic_vector(data_width_c - 1 downto 0) := None
          - constant dm_pbuf_base_c : std_ulogic_vector(data_width_c - 1 downto 0) := None
          - constant dm_data_base_c : std_ulogic_vector(data_width_c - 1 downto 0) := None
          - constant dm_sreg_base_c : std_ulogic_vector(data_width_c - 1 downto 0) := None
          - constant io_base_c : std_ulogic_vector(data_width_c - 1 downto 0) := None
          - constant io_size_c : natural := 512
          - constant cfs_base_c : std_ulogic_vector(data_width_c - 1 downto 0) := None
          - constant cfs_size_c : natural := 32 * 4
          - constant cfs_reg0_addr_c : std_ulogic_vector(data_width_c - 1 downto 0) := None
          - constant cfs_reg1_addr_c : std_ulogic_vector(data_width_c - 1 downto 0) := None
          - constant cfs_reg2_addr_c : std_ulogic_vector(data_width_c - 1 downto 0) := None
          - constant cfs_reg3_addr_c : std_ulogic_vector(data_width_c - 1 downto 0) := None
          - constant cfs_reg4_addr_c : std_ulogic_vector(data_width_c - 1 downto 0) := None
          - constant cfs_reg5_addr_c : std_ulogic_vector(data_width_c - 1 downto 0) := None
          - constant cfs_reg6_addr_c : std_ulogic_vector(data_width_c - 1 downto 0) := None
          - constant cfs_reg7_addr_c : std_ulogic_vector(data_width_c - 1 downto 0) := None
          - constant cfs_reg8_addr_c : std_ulogic_vector(data_width_c - 1 downto 0) := None
          - constant cfs_reg9_addr_c : std_ulogic_vector(data_width_c - 1 downto 0) := None
          - constant cfs_reg10_addr_c : std_ulogic_vector(data_width_c - 1 downto 0) := None
          - constant cfs_reg11_addr_c : std_ulogic_vector(data_width_c - 1 downto 0) := None
          - constant cfs_reg12_addr_c : std_ulogic_vector(data_width_c - 1 downto 0) := None
          - constant cfs_reg13_addr_c : std_ulogic_vector(data_width_c - 1 downto 0) := None
          - constant cfs_reg14_addr_c : std_ulogic_vector(data_width_c - 1 downto 0) := None
          - constant cfs_reg15_addr_c : std_ulogic_vector(data_width_c - 1 downto 0) := None
          - constant cfs_reg16_addr_c : std_ulogic_vector(data_width_c - 1 downto 0) := None
          - constant cfs_reg17_addr_c : std_ulogic_vector(data_width_c - 1 downto 0) := None
          - constant cfs_reg18_addr_c : std_ulogic_vector(data_width_c - 1 downto 0) := None
          - constant cfs_reg19_addr_c : std_ulogic_vector(data_width_c - 1 downto 0) := None
          - constant cfs_reg20_addr_c : std_ulogic_vector(data_width_c - 1 downto 0) := None
          - constant cfs_reg21_addr_c : std_ulogic_vector(data_width_c - 1 downto 0) := None
          - constant cfs_reg22_addr_c : std_ulogic_vector(data_width_c - 1 downto 0) := None
          - constant cfs_reg23_addr_c : std_ulogic_vector(data_width_c - 1 downto 0) := None
          - constant cfs_reg24_addr_c : std_ulogic_vector(data_width_c - 1 downto 0) := None
          - constant cfs_reg25_addr_c : std_ulogic_vector(data_width_c - 1 downto 0) := None
          - constant cfs_reg26_addr_c : std_ulogic_vector(data_width_c - 1 downto 0) := None
          - constant cfs_reg27_addr_c : std_ulogic_vector(data_width_c - 1 downto 0) := None
          - constant cfs_reg28_addr_c : std_ulogic_vector(data_width_c - 1 downto 0) := None
          - constant cfs_reg29_addr_c : std_ulogic_vector(data_width_c - 1 downto 0) := None
          - constant cfs_reg30_addr_c : std_ulogic_vector(data_width_c - 1 downto 0) := None
          - constant cfs_reg31_addr_c : std_ulogic_vector(data_width_c - 1 downto 0) := None
          - constant pwm_base_c : std_ulogic_vector(data_width_c - 1 downto 0) := None
          - constant pwm_size_c : natural := 16 * 4
          - constant pwm_ctrl_addr_c : std_ulogic_vector(data_width_c - 1 downto 0) := None
          - constant pwm_duty0_addr_c : std_ulogic_vector(data_width_c - 1 downto 0) := None
          - constant pwm_duty1_addr_c : std_ulogic_vector(data_width_c - 1 downto 0) := None
          - constant pwm_duty2_addr_c : std_ulogic_vector(data_width_c - 1 downto 0) := None
          - constant pwm_duty3_addr_c : std_ulogic_vector(data_width_c - 1 downto 0) := None
          - constant pwm_duty4_addr_c : std_ulogic_vector(data_width_c - 1 downto 0) := None
          - constant pwm_duty5_addr_c : std_ulogic_vector(data_width_c - 1 downto 0) := None
          - constant pwm_duty6_addr_c : std_ulogic_vector(data_width_c - 1 downto 0) := None
          - constant pwm_duty7_addr_c : std_ulogic_vector(data_width_c - 1 downto 0) := None
          - constant pwm_duty8_addr_c : std_ulogic_vector(data_width_c - 1 downto 0) := None
          - constant pwm_duty9_addr_c : std_ulogic_vector(data_width_c - 1 downto 0) := None
          - constant pwm_duty10_addr_c : std_ulogic_vector(data_width_c - 1 downto 0) := None
          - constant pwm_duty11_addr_c : std_ulogic_vector(data_width_c - 1 downto 0) := None
          - constant pwm_duty12_addr_c : std_ulogic_vector(data_width_c - 1 downto 0) := None
          - constant pwm_duty13_addr_c : std_ulogic_vector(data_width_c - 1 downto 0) := None
          - constant pwm_duty14_addr_c : std_ulogic_vector(data_width_c - 1 downto 0) := None
          - constant slink_base_c : std_ulogic_vector(data_width_c - 1 downto 0) := None
          - constant slink_size_c : natural := 16 * 4
          - constant gptmr_base_c : std_ulogic_vector(data_width_c - 1 downto 0) := None
          - constant gptmr_size_c : natural := 4 * 4
          - constant gptmr_ctrl_addr_c : std_ulogic_vector(data_width_c - 1 downto 0) := None
          - constant gptmr_thres_addr_c : std_ulogic_vector(data_width_c - 1 downto 0) := None
          - constant gptmr_count_addr_c : std_ulogic_vector(data_width_c - 1 downto 0) := None
          - constant buskeeper_base_c : std_ulogic_vector(data_width_c - 1 downto 0) := None
          - constant buskeeper_size_c : natural := 1 * 4
          - constant xirq_base_c : std_ulogic_vector(data_width_c - 1 downto 0) := None
          - constant xirq_size_c : natural := 4 * 4
          - constant xirq_enable_addr_c : std_ulogic_vector(data_width_c - 1 downto 0) := None
          - constant xirq_pending_addr_c : std_ulogic_vector(data_width_c - 1 downto 0) := None
          - constant xirq_source_addr_c : std_ulogic_vector(data_width_c - 1 downto 0) := None
          - constant mtime_base_c : std_ulogic_vector(data_width_c - 1 downto 0) := None
          - constant mtime_size_c : natural := 4 * 4
          - constant mtime_time_lo_addr_c : std_ulogic_vector(data_width_c - 1 downto 0) := None
          - constant mtime_time_hi_addr_c : std_ulogic_vector(data_width_c - 1 downto 0) := None
          - constant mtime_cmp_lo_addr_c : std_ulogic_vector(data_width_c - 1 downto 0) := None
          - constant mtime_cmp_hi_addr_c : std_ulogic_vector(data_width_c - 1 downto 0) := None
          - constant uart0_base_c : std_ulogic_vector(data_width_c - 1 downto 0) := None
          - constant uart0_size_c : natural := 2 * 4
          - constant uart0_ctrl_addr_c : std_ulogic_vector(data_width_c - 1 downto 0) := None
          - constant uart0_rtx_addr_c : std_ulogic_vector(data_width_c - 1 downto 0) := None
          - constant spi_base_c : std_ulogic_vector(data_width_c - 1 downto 0) := None
          - constant spi_size_c : natural := 2 * 4
          - constant spi_ctrl_addr_c : std_ulogic_vector(data_width_c - 1 downto 0) := None
          - constant spi_rtx_addr_c : std_ulogic_vector(data_width_c - 1 downto 0) := None
          - constant twi_base_c : std_ulogic_vector(data_width_c - 1 downto 0) := None
          - constant twi_size_c : natural := 2 * 4
          - constant twi_ctrl_addr_c : std_ulogic_vector(data_width_c - 1 downto 0) := None
          - constant twi_rtx_addr_c : std_ulogic_vector(data_width_c - 1 downto 0) := None
          - constant trng_base_c : std_ulogic_vector(data_width_c - 1 downto 0) := None
          - constant trng_size_c : natural := 1 * 4
          - constant trng_ctrl_addr_c : std_ulogic_vector(data_width_c - 1 downto 0) := None
          - constant wdt_base_c : std_ulogic_vector(data_width_c - 1 downto 0) := None
          - constant wdt_size_c : natural := 1 * 4
          - constant wdt_ctrl_addr_c : std_ulogic_vector(data_width_c - 1 downto 0) := None
          - constant gpio_base_c : std_ulogic_vector(data_width_c - 1 downto 0) := None
          - constant gpio_size_c : natural := 4 * 4
          - constant gpio_in_lo_addr_c : std_ulogic_vector(data_width_c - 1 downto 0) := None
          - constant gpio_in_hi_addr_c : std_ulogic_vector(data_width_c - 1 downto 0) := None
          - constant gpio_out_lo_addr_c : std_ulogic_vector(data_width_c - 1 downto 0) := None
          - constant gpio_out_hi_addr_c : std_ulogic_vector(data_width_c - 1 downto 0) := None
          - constant uart1_base_c : std_ulogic_vector(data_width_c - 1 downto 0) := None
          - constant uart1_size_c : natural := 2 * 4
          - constant uart1_ctrl_addr_c : std_ulogic_vector(data_width_c - 1 downto 0) := None
          - constant uart1_rtx_addr_c : std_ulogic_vector(data_width_c - 1 downto 0) := None
          - constant neoled_base_c : std_ulogic_vector(data_width_c - 1 downto 0) := None
          - constant neoled_size_c : natural := 2 * 4
          - constant neoled_ctrl_addr_c : std_ulogic_vector(data_width_c - 1 downto 0) := None
          - constant neoled_data_addr_c : std_ulogic_vector(data_width_c - 1 downto 0) := None
          - constant sysinfo_base_c : std_ulogic_vector(data_width_c - 1 downto 0) := None
          - constant sysinfo_size_c : natural := 8 * 4
          - constant ctrl_rf_in_mux_c : natural := 0
          - constant ctrl_rf_rs1_adr0_c : natural := 1
          - constant ctrl_rf_rs1_adr1_c : natural := 2
          - constant ctrl_rf_rs1_adr2_c : natural := 3
          - constant ctrl_rf_rs1_adr3_c : natural := 4
          - constant ctrl_rf_rs1_adr4_c : natural := 5
          - constant ctrl_rf_rs2_adr0_c : natural := 6
          - constant ctrl_rf_rs2_adr1_c : natural := 7
          - constant ctrl_rf_rs2_adr2_c : natural := 8
          - constant ctrl_rf_rs2_adr3_c : natural := 9
          - constant ctrl_rf_rs2_adr4_c : natural := 10
          - constant ctrl_rf_rd_adr0_c : natural := 11
          - constant ctrl_rf_rd_adr1_c : natural := 12
          - constant ctrl_rf_rd_adr2_c : natural := 13
          - constant ctrl_rf_rd_adr3_c : natural := 14
          - constant ctrl_rf_rd_adr4_c : natural := 15
          - constant ctrl_rf_wb_en_c : natural := 16
          - constant ctrl_alu_op0_c : natural := 17
          - constant ctrl_alu_op1_c : natural := 18
          - constant ctrl_alu_op2_c : natural := 19
          - constant ctrl_alu_func0_c : natural := 20
          - constant ctrl_alu_func1_c : natural := 21
          - constant ctrl_alu_opa_mux_c : natural := 22
          - constant ctrl_alu_opb_mux_c : natural := 23
          - constant ctrl_alu_unsigned_c : natural := 24
          - constant ctrl_alu_shift_dir_c : natural := 25
          - constant ctrl_alu_shift_ar_c : natural := 26
          - constant ctrl_alu_frm0_c : natural := 27
          - constant ctrl_alu_frm1_c : natural := 28
          - constant ctrl_alu_frm2_c : natural := 29
          - constant ctrl_bus_size_lsb_c : natural := 30
          - constant ctrl_bus_size_msb_c : natural := 31
          - constant ctrl_bus_rd_c : natural := 32
          - constant ctrl_bus_wr_c : natural := 33
          - constant ctrl_bus_if_c : natural := 34
          - constant ctrl_bus_mo_we_c : natural := 35
          - constant ctrl_bus_mi_we_c : natural := 36
          - constant ctrl_bus_unsigned_c : natural := 37
          - constant ctrl_bus_ierr_ack_c : natural := 38
          - constant ctrl_bus_derr_ack_c : natural := 39
          - constant ctrl_bus_fence_c : natural := 40
          - constant ctrl_bus_fencei_c : natural := 41
          - constant ctrl_bus_lock_c : natural := 42
          - constant ctrl_bus_de_lock_c : natural := 43
          - constant ctrl_bus_ch_lock_c : natural := 44
          - constant ctrl_cp_id_lsb_c : natural := 45
          - constant ctrl_cp_id_msb_c : natural := 46
          - constant ctrl_ir_funct3_0_c : natural := 47
          - constant ctrl_ir_funct3_1_c : natural := 48
          - constant ctrl_ir_funct3_2_c : natural := 49
          - constant ctrl_ir_funct12_0_c : natural := 50
          - constant ctrl_ir_funct12_1_c : natural := 51
          - constant ctrl_ir_funct12_2_c : natural := 52
          - constant ctrl_ir_funct12_3_c : natural := 53
          - constant ctrl_ir_funct12_4_c : natural := 54
          - constant ctrl_ir_funct12_5_c : natural := 55
          - constant ctrl_ir_funct12_6_c : natural := 56
          - constant ctrl_ir_funct12_7_c : natural := 57
          - constant ctrl_ir_funct12_8_c : natural := 58
          - constant ctrl_ir_funct12_9_c : natural := 59
          - constant ctrl_ir_funct12_10_c : natural := 60
          - constant ctrl_ir_funct12_11_c : natural := 61
          - constant ctrl_ir_opcode7_0_c : natural := 62
          - constant ctrl_ir_opcode7_1_c : natural := 63
          - constant ctrl_ir_opcode7_2_c : natural := 64
          - constant ctrl_ir_opcode7_3_c : natural := 65
          - constant ctrl_ir_opcode7_4_c : natural := 66
          - constant ctrl_ir_opcode7_5_c : natural := 67
          - constant ctrl_ir_opcode7_6_c : natural := 68
          - constant ctrl_priv_lvl_lsb_c : natural := 69
          - constant ctrl_priv_lvl_msb_c : natural := 70
          - constant ctrl_sleep_c : natural := 71
          - constant ctrl_trap_c : natural := 72
          - constant ctrl_debug_running_c : natural := 73
          - constant ctrl_width_c : natural := 74
          - constant cmp_equal_c : natural := 0
          - constant cmp_less_c : natural := 1
          - constant instr_opcode_lsb_c : natural := 0
          - constant instr_opcode_msb_c : natural := 6
          - constant instr_rd_lsb_c : natural := 7
          - constant instr_rd_msb_c : natural := 11
          - constant instr_funct3_lsb_c : natural := 12
          - constant instr_funct3_msb_c : natural := 14
          - constant instr_rs1_lsb_c : natural := 15
          - constant instr_rs1_msb_c : natural := 19
          - constant instr_rs2_lsb_c : natural := 20
          - constant instr_rs2_msb_c : natural := 24
          - constant instr_funct7_lsb_c : natural := 25
          - constant instr_funct7_msb_c : natural := 31
          - constant instr_funct12_lsb_c : natural := 20
          - constant instr_funct12_msb_c : natural := 31
          - constant instr_imm12_lsb_c : natural := 20
          - constant instr_imm12_msb_c : natural := 31
          - constant instr_imm20_lsb_c : natural := 12
          - constant instr_imm20_msb_c : natural := 31
          - constant instr_csr_id_lsb_c : natural := 20
          - constant instr_csr_id_msb_c : natural := 31
          - constant instr_funct5_lsb_c : natural := 27
          - constant instr_funct5_msb_c : natural := 31
          - constant opcode_lui_c : std_ulogic_vector(6 downto 0) := "0110111"
          - constant opcode_auipc_c : std_ulogic_vector(6 downto 0) := "0010111"
          - constant opcode_alui_c : std_ulogic_vector(6 downto 0) := "0010011"
          - constant opcode_alu_c : std_ulogic_vector(6 downto 0) := "0110011"
          - constant opcode_jal_c : std_ulogic_vector(6 downto 0) := "1101111"
          - constant opcode_jalr_c : std_ulogic_vector(6 downto 0) := "1100111"
          - constant opcode_branch_c : std_ulogic_vector(6 downto 0) := "1100011"
          - constant opcode_load_c : std_ulogic_vector(6 downto 0) := "0000011"
          - constant opcode_store_c : std_ulogic_vector(6 downto 0) := "0100011"
          - constant opcode_fence_c : std_ulogic_vector(6 downto 0) := "0001111"
          - constant opcode_syscsr_c : std_ulogic_vector(6 downto 0) := "1110011"
          - constant opcode_atomic_c : std_ulogic_vector(6 downto 0) := "0101111"
          - constant opcode_fop_c : std_ulogic_vector(6 downto 0) := "1010011"
          - constant funct3_beq_c : std_ulogic_vector(2 downto 0) := "000"
          - constant funct3_bne_c : std_ulogic_vector(2 downto 0) := "001"
          - constant funct3_blt_c : std_ulogic_vector(2 downto 0) := "100"
          - constant funct3_bge_c : std_ulogic_vector(2 downto 0) := "101"
          - constant funct3_bltu_c : std_ulogic_vector(2 downto 0) := "110"
          - constant funct3_bgeu_c : std_ulogic_vector(2 downto 0) := "111"
          - constant funct3_lb_c : std_ulogic_vector(2 downto 0) := "000"
          - constant funct3_lh_c : std_ulogic_vector(2 downto 0) := "001"
          - constant funct3_lw_c : std_ulogic_vector(2 downto 0) := "010"
          - constant funct3_lbu_c : std_ulogic_vector(2 downto 0) := "100"
          - constant funct3_lhu_c : std_ulogic_vector(2 downto 0) := "101"
          - constant funct3_sb_c : std_ulogic_vector(2 downto 0) := "000"
          - constant funct3_sh_c : std_ulogic_vector(2 downto 0) := "001"
          - constant funct3_sw_c : std_ulogic_vector(2 downto 0) := "010"
          - constant funct3_subadd_c : std_ulogic_vector(2 downto 0) := "000"
          - constant funct3_sll_c : std_ulogic_vector(2 downto 0) := "001"
          - constant funct3_slt_c : std_ulogic_vector(2 downto 0) := "010"
          - constant funct3_sltu_c : std_ulogic_vector(2 downto 0) := "011"
          - constant funct3_xor_c : std_ulogic_vector(2 downto 0) := "100"
          - constant funct3_sr_c : std_ulogic_vector(2 downto 0) := "101"
          - constant funct3_or_c : std_ulogic_vector(2 downto 0) := "110"
          - constant funct3_and_c : std_ulogic_vector(2 downto 0) := "111"
          - constant funct3_env_c : std_ulogic_vector(2 downto 0) := "000"
          - constant funct3_csrrw_c : std_ulogic_vector(2 downto 0) := "001"
          - constant funct3_csrrs_c : std_ulogic_vector(2 downto 0) := "010"
          - constant funct3_csrrc_c : std_ulogic_vector(2 downto 0) := "011"
          - constant funct3_csrrwi_c : std_ulogic_vector(2 downto 0) := "101"
          - constant funct3_csrrsi_c : std_ulogic_vector(2 downto 0) := "110"
          - constant funct3_csrrci_c : std_ulogic_vector(2 downto 0) := "111"
          - constant funct3_fence_c : std_ulogic_vector(2 downto 0) := "000"
          - constant funct3_fencei_c : std_ulogic_vector(2 downto 0) := "001"
          - constant funct12_ecall_c : std_ulogic_vector(11 downto 0) := None
          - constant funct12_ebreak_c : std_ulogic_vector(11 downto 0) := None
          - constant funct12_mret_c : std_ulogic_vector(11 downto 0) := None
          - constant funct12_wfi_c : std_ulogic_vector(11 downto 0) := None
          - constant funct12_dret_c : std_ulogic_vector(11 downto 0) := None
          - constant funct5_a_lr_c : std_ulogic_vector(4 downto 0) := "00010"
          - constant funct5_a_sc_c : std_ulogic_vector(4 downto 0) := "00011"
          - constant float_single_c : std_ulogic_vector(1 downto 0) := "00"
          - constant float_double_c : std_ulogic_vector(1 downto 0) := "01"
          - constant float_half_c : std_ulogic_vector(1 downto 0) := "10"
          - constant float_quad_c : std_ulogic_vector(1 downto 0) := "11"
          - constant fp_class_neg_inf_c : natural := 0
          - constant fp_class_neg_norm_c : natural := 1
          - constant fp_class_neg_denorm_c : natural := 2
          - constant fp_class_neg_zero_c : natural := 3
          - constant fp_class_pos_zero_c : natural := 4
          - constant fp_class_pos_denorm_c : natural := 5
          - constant fp_class_pos_norm_c : natural := 6
          - constant fp_class_pos_inf_c : natural := 7
          - constant fp_class_snan_c : natural := 8
          - constant fp_class_qnan_c : natural := 9
          - constant fp_exc_nv_c : natural := 0
          - constant fp_exc_dz_c : natural := 1
          - constant fp_exc_of_c : natural := 2
          - constant fp_exc_uf_c : natural := 3
          - constant fp_exc_nx_c : natural := 4
          - constant fp_single_qnan_c : std_ulogic_vector(31 downto 0) := None
          - constant fp_single_snan_c : std_ulogic_vector(31 downto 0) := None
          - constant fp_single_pos_inf_c : std_ulogic_vector(31 downto 0) := None
          - constant fp_single_neg_inf_c : std_ulogic_vector(31 downto 0) := None
          - constant fp_single_pos_zero_c : std_ulogic_vector(31 downto 0) := None
          - constant fp_single_neg_zero_c : std_ulogic_vector(31 downto 0) := None
          - constant csr_class_float_c : std_ulogic_vector(9 downto 0) := None & "00"
          - constant csr_fflags_c : std_ulogic_vector(11 downto 0) := None
          - constant csr_frm_c : std_ulogic_vector(11 downto 0) := None
          - constant csr_fcsr_c : std_ulogic_vector(11 downto 0) := None
          - constant csr_class_setup_c : std_ulogic_vector(8 downto 0) := None & 0
          - constant csr_mstatus_c : std_ulogic_vector(11 downto 0) := None
          - constant csr_misa_c : std_ulogic_vector(11 downto 0) := None
          - constant csr_mie_c : std_ulogic_vector(11 downto 0) := None
          - constant csr_mtvec_c : std_ulogic_vector(11 downto 0) := None
          - constant csr_mcounteren_c : std_ulogic_vector(11 downto 0) := None
          - constant csr_mstatush_c : std_ulogic_vector(11 downto 0) := None
          - constant csr_class_envcfg_c : std_ulogic_vector(6 downto 0) := None & "000"
          - constant csr_menvcfg_c : std_ulogic_vector(11 downto 0) := None
          - constant csr_menvcfgh_c : std_ulogic_vector(11 downto 0) := None
          - constant csr_cnt_setup_c : std_ulogic_vector(6 downto 0) := None & "001"
          - constant csr_mcountinhibit_c : std_ulogic_vector(11 downto 0) := None
          - constant csr_mhpmevent3_c : std_ulogic_vector(11 downto 0) := None
          - constant csr_mhpmevent4_c : std_ulogic_vector(11 downto 0) := None
          - constant csr_mhpmevent5_c : std_ulogic_vector(11 downto 0) := None
          - constant csr_mhpmevent6_c : std_ulogic_vector(11 downto 0) := None
          - constant csr_mhpmevent7_c : std_ulogic_vector(11 downto 0) := None
          - constant csr_mhpmevent8_c : std_ulogic_vector(11 downto 0) := None
          - constant csr_mhpmevent9_c : std_ulogic_vector(11 downto 0) := None
          - constant csr_mhpmevent10_c : std_ulogic_vector(11 downto 0) := None
          - constant csr_mhpmevent11_c : std_ulogic_vector(11 downto 0) := None
          - constant csr_mhpmevent12_c : std_ulogic_vector(11 downto 0) := None
          - constant csr_mhpmevent13_c : std_ulogic_vector(11 downto 0) := None
          - constant csr_mhpmevent14_c : std_ulogic_vector(11 downto 0) := None
          - constant csr_mhpmevent15_c : std_ulogic_vector(11 downto 0) := None
          - constant csr_mhpmevent16_c : std_ulogic_vector(11 downto 0) := None
          - constant csr_mhpmevent17_c : std_ulogic_vector(11 downto 0) := None
          - constant csr_mhpmevent18_c : std_ulogic_vector(11 downto 0) := None
          - constant csr_mhpmevent19_c : std_ulogic_vector(11 downto 0) := None
          - constant csr_mhpmevent20_c : std_ulogic_vector(11 downto 0) := None
          - constant csr_mhpmevent21_c : std_ulogic_vector(11 downto 0) := None
          - constant csr_mhpmevent22_c : std_ulogic_vector(11 downto 0) := None
          - constant csr_mhpmevent23_c : std_ulogic_vector(11 downto 0) := None
          - constant csr_mhpmevent24_c : std_ulogic_vector(11 downto 0) := None
          - constant csr_mhpmevent25_c : std_ulogic_vector(11 downto 0) := None
          - constant csr_mhpmevent26_c : std_ulogic_vector(11 downto 0) := None
          - constant csr_mhpmevent27_c : std_ulogic_vector(11 downto 0) := None
          - constant csr_mhpmevent28_c : std_ulogic_vector(11 downto 0) := None
          - constant csr_mhpmevent29_c : std_ulogic_vector(11 downto 0) := None
          - constant csr_mhpmevent30_c : std_ulogic_vector(11 downto 0) := None
          - constant csr_mhpmevent31_c : std_ulogic_vector(11 downto 0) := None
          - constant csr_class_trap_c : std_ulogic_vector(8 downto 0) := None & 0
          - constant csr_mscratch_c : std_ulogic_vector(11 downto 0) := None
          - constant csr_mepc_c : std_ulogic_vector(11 downto 0) := None
          - constant csr_mcause_c : std_ulogic_vector(11 downto 0) := None
          - constant csr_mtval_c : std_ulogic_vector(11 downto 0) := None
          - constant csr_mip_c : std_ulogic_vector(11 downto 0) := None
          - constant csr_class_pmpcfg_c : std_ulogic_vector(7 downto 0) := None
          - constant csr_pmpcfg0_c : std_ulogic_vector(11 downto 0) := None
          - constant csr_pmpcfg1_c : std_ulogic_vector(11 downto 0) := None
          - constant csr_pmpcfg2_c : std_ulogic_vector(11 downto 0) := None
          - constant csr_pmpcfg3_c : std_ulogic_vector(11 downto 0) := None
          - constant csr_pmpcfg4_c : std_ulogic_vector(11 downto 0) := None
          - constant csr_pmpcfg5_c : std_ulogic_vector(11 downto 0) := None
          - constant csr_pmpcfg6_c : std_ulogic_vector(11 downto 0) := None
          - constant csr_pmpcfg7_c : std_ulogic_vector(11 downto 0) := None
          - constant csr_pmpcfg8_c : std_ulogic_vector(11 downto 0) := None
          - constant csr_pmpcfg9_c : std_ulogic_vector(11 downto 0) := None
          - constant csr_pmpcfg10_c : std_ulogic_vector(11 downto 0) := None
          - constant csr_pmpcfg11_c : std_ulogic_vector(11 downto 0) := None
          - constant csr_pmpcfg12_c : std_ulogic_vector(11 downto 0) := None
          - constant csr_pmpcfg13_c : std_ulogic_vector(11 downto 0) := None
          - constant csr_pmpcfg14_c : std_ulogic_vector(11 downto 0) := None
          - constant csr_pmpcfg15_c : std_ulogic_vector(11 downto 0) := None
          - constant csr_pmpaddr0_c : std_ulogic_vector(11 downto 0) := None
          - constant csr_pmpaddr1_c : std_ulogic_vector(11 downto 0) := None
          - constant csr_pmpaddr2_c : std_ulogic_vector(11 downto 0) := None
          - constant csr_pmpaddr3_c : std_ulogic_vector(11 downto 0) := None
          - constant csr_pmpaddr4_c : std_ulogic_vector(11 downto 0) := None
          - constant csr_pmpaddr5_c : std_ulogic_vector(11 downto 0) := None
          - constant csr_pmpaddr6_c : std_ulogic_vector(11 downto 0) := None
          - constant csr_pmpaddr7_c : std_ulogic_vector(11 downto 0) := None
          - constant csr_pmpaddr8_c : std_ulogic_vector(11 downto 0) := None
          - constant csr_pmpaddr9_c : std_ulogic_vector(11 downto 0) := None
          - constant csr_pmpaddr10_c : std_ulogic_vector(11 downto 0) := None
          - constant csr_pmpaddr11_c : std_ulogic_vector(11 downto 0) := None
          - constant csr_pmpaddr12_c : std_ulogic_vector(11 downto 0) := None
          - constant csr_pmpaddr13_c : std_ulogic_vector(11 downto 0) := None
          - constant csr_pmpaddr14_c : std_ulogic_vector(11 downto 0) := None
          - constant csr_pmpaddr15_c : std_ulogic_vector(11 downto 0) := None
          - constant csr_pmpaddr16_c : std_ulogic_vector(11 downto 0) := None
          - constant csr_pmpaddr17_c : std_ulogic_vector(11 downto 0) := None
          - constant csr_pmpaddr18_c : std_ulogic_vector(11 downto 0) := None
          - constant csr_pmpaddr19_c : std_ulogic_vector(11 downto 0) := None
          - constant csr_pmpaddr20_c : std_ulogic_vector(11 downto 0) := None
          - constant csr_pmpaddr21_c : std_ulogic_vector(11 downto 0) := None
          - constant csr_pmpaddr22_c : std_ulogic_vector(11 downto 0) := None
          - constant csr_pmpaddr23_c : std_ulogic_vector(11 downto 0) := None
          - constant csr_pmpaddr24_c : std_ulogic_vector(11 downto 0) := None
          - constant csr_pmpaddr25_c : std_ulogic_vector(11 downto 0) := None
          - constant csr_pmpaddr26_c : std_ulogic_vector(11 downto 0) := None
          - constant csr_pmpaddr27_c : std_ulogic_vector(11 downto 0) := None
          - constant csr_pmpaddr28_c : std_ulogic_vector(11 downto 0) := None
          - constant csr_pmpaddr29_c : std_ulogic_vector(11 downto 0) := None
          - constant csr_pmpaddr30_c : std_ulogic_vector(11 downto 0) := None
          - constant csr_pmpaddr31_c : std_ulogic_vector(11 downto 0) := None
          - constant csr_pmpaddr32_c : std_ulogic_vector(11 downto 0) := None
          - constant csr_pmpaddr33_c : std_ulogic_vector(11 downto 0) := None
          - constant csr_pmpaddr34_c : std_ulogic_vector(11 downto 0) := None
          - constant csr_pmpaddr35_c : std_ulogic_vector(11 downto 0) := None
          - constant csr_pmpaddr36_c : std_ulogic_vector(11 downto 0) := None
          - constant csr_pmpaddr37_c : std_ulogic_vector(11 downto 0) := None
          - constant csr_pmpaddr38_c : std_ulogic_vector(11 downto 0) := None
          - constant csr_pmpaddr39_c : std_ulogic_vector(11 downto 0) := None
          - constant csr_pmpaddr40_c : std_ulogic_vector(11 downto 0) := None
          - constant csr_pmpaddr41_c : std_ulogic_vector(11 downto 0) := None
          - constant csr_pmpaddr42_c : std_ulogic_vector(11 downto 0) := None
          - constant csr_pmpaddr43_c : std_ulogic_vector(11 downto 0) := None
          - constant csr_pmpaddr44_c : std_ulogic_vector(11 downto 0) := None
          - constant csr_pmpaddr45_c : std_ulogic_vector(11 downto 0) := None
          - constant csr_pmpaddr46_c : std_ulogic_vector(11 downto 0) := None
          - constant csr_pmpaddr47_c : std_ulogic_vector(11 downto 0) := None
          - constant csr_pmpaddr48_c : std_ulogic_vector(11 downto 0) := None
          - constant csr_pmpaddr49_c : std_ulogic_vector(11 downto 0) := None
          - constant csr_pmpaddr50_c : std_ulogic_vector(11 downto 0) := None
          - constant csr_pmpaddr51_c : std_ulogic_vector(11 downto 0) := None
          - constant csr_pmpaddr52_c : std_ulogic_vector(11 downto 0) := None
          - constant csr_pmpaddr53_c : std_ulogic_vector(11 downto 0) := None
          - constant csr_pmpaddr54_c : std_ulogic_vector(11 downto 0) := None
          - constant csr_pmpaddr55_c : std_ulogic_vector(11 downto 0) := None
          - constant csr_pmpaddr56_c : std_ulogic_vector(11 downto 0) := None
          - constant csr_pmpaddr57_c : std_ulogic_vector(11 downto 0) := None
          - constant csr_pmpaddr58_c : std_ulogic_vector(11 downto 0) := None
          - constant csr_pmpaddr59_c : std_ulogic_vector(11 downto 0) := None
          - constant csr_pmpaddr60_c : std_ulogic_vector(11 downto 0) := None
          - constant csr_pmpaddr61_c : std_ulogic_vector(11 downto 0) := None
          - constant csr_pmpaddr62_c : std_ulogic_vector(11 downto 0) := None
          - constant csr_pmpaddr63_c : std_ulogic_vector(11 downto 0) := None
          - constant csr_class_debug_c : std_ulogic_vector(9 downto 0) := None & "00"
          - constant csr_dcsr_c : std_ulogic_vector(11 downto 0) := None
          - constant csr_dpc_c : std_ulogic_vector(11 downto 0) := None
          - constant csr_dscratch0_c : std_ulogic_vector(11 downto 0) := None
          - constant csr_mcycle_c : std_ulogic_vector(11 downto 0) := None
          - constant csr_minstret_c : std_ulogic_vector(11 downto 0) := None
          - constant csr_mhpmcounter3_c : std_ulogic_vector(11 downto 0) := None
          - constant csr_mhpmcounter4_c : std_ulogic_vector(11 downto 0) := None
          - constant csr_mhpmcounter5_c : std_ulogic_vector(11 downto 0) := None
          - constant csr_mhpmcounter6_c : std_ulogic_vector(11 downto 0) := None
          - constant csr_mhpmcounter7_c : std_ulogic_vector(11 downto 0) := None
          - constant csr_mhpmcounter8_c : std_ulogic_vector(11 downto 0) := None
          - constant csr_mhpmcounter9_c : std_ulogic_vector(11 downto 0) := None
          - constant csr_mhpmcounter10_c : std_ulogic_vector(11 downto 0) := None
          - constant csr_mhpmcounter11_c : std_ulogic_vector(11 downto 0) := None
          - constant csr_mhpmcounter12_c : std_ulogic_vector(11 downto 0) := None
          - constant csr_mhpmcounter13_c : std_ulogic_vector(11 downto 0) := None
          - constant csr_mhpmcounter14_c : std_ulogic_vector(11 downto 0) := None
          - constant csr_mhpmcounter15_c : std_ulogic_vector(11 downto 0) := None
          - constant csr_mhpmcounter16_c : std_ulogic_vector(11 downto 0) := None
          - constant csr_mhpmcounter17_c : std_ulogic_vector(11 downto 0) := None
          - constant csr_mhpmcounter18_c : std_ulogic_vector(11 downto 0) := None
          - constant csr_mhpmcounter19_c : std_ulogic_vector(11 downto 0) := None
          - constant csr_mhpmcounter20_c : std_ulogic_vector(11 downto 0) := None
          - constant csr_mhpmcounter21_c : std_ulogic_vector(11 downto 0) := None
          - constant csr_mhpmcounter22_c : std_ulogic_vector(11 downto 0) := None
          - constant csr_mhpmcounter23_c : std_ulogic_vector(11 downto 0) := None
          - constant csr_mhpmcounter24_c : std_ulogic_vector(11 downto 0) := None
          - constant csr_mhpmcounter25_c : std_ulogic_vector(11 downto 0) := None
          - constant csr_mhpmcounter26_c : std_ulogic_vector(11 downto 0) := None
          - constant csr_mhpmcounter27_c : std_ulogic_vector(11 downto 0) := None
          - constant csr_mhpmcounter28_c : std_ulogic_vector(11 downto 0) := None
          - constant csr_mhpmcounter29_c : std_ulogic_vector(11 downto 0) := None
          - constant csr_mhpmcounter30_c : std_ulogic_vector(11 downto 0) := None
          - constant csr_mhpmcounter31_c : std_ulogic_vector(11 downto 0) := None
          - constant csr_mcycleh_c : std_ulogic_vector(11 downto 0) := None
          - constant csr_minstreth_c : std_ulogic_vector(11 downto 0) := None
          - constant csr_mhpmcounter3h_c : std_ulogic_vector(11 downto 0) := None
          - constant csr_mhpmcounter4h_c : std_ulogic_vector(11 downto 0) := None
          - constant csr_mhpmcounter5h_c : std_ulogic_vector(11 downto 0) := None
          - constant csr_mhpmcounter6h_c : std_ulogic_vector(11 downto 0) := None
          - constant csr_mhpmcounter7h_c : std_ulogic_vector(11 downto 0) := None
          - constant csr_mhpmcounter8h_c : std_ulogic_vector(11 downto 0) := None
          - constant csr_mhpmcounter9h_c : std_ulogic_vector(11 downto 0) := None
          - constant csr_mhpmcounter10h_c : std_ulogic_vector(11 downto 0) := None
          - constant csr_mhpmcounter11h_c : std_ulogic_vector(11 downto 0) := None
          - constant csr_mhpmcounter12h_c : std_ulogic_vector(11 downto 0) := None
          - constant csr_mhpmcounter13h_c : std_ulogic_vector(11 downto 0) := None
          - constant csr_mhpmcounter14h_c : std_ulogic_vector(11 downto 0) := None
          - constant csr_mhpmcounter15h_c : std_ulogic_vector(11 downto 0) := None
          - constant csr_mhpmcounter16h_c : std_ulogic_vector(11 downto 0) := None
          - constant csr_mhpmcounter17h_c : std_ulogic_vector(11 downto 0) := None
          - constant csr_mhpmcounter18h_c : std_ulogic_vector(11 downto 0) := None
          - constant csr_mhpmcounter19h_c : std_ulogic_vector(11 downto 0) := None
          - constant csr_mhpmcounter20h_c : std_ulogic_vector(11 downto 0) := None
          - constant csr_mhpmcounter21h_c : std_ulogic_vector(11 downto 0) := None
          - constant csr_mhpmcounter22h_c : std_ulogic_vector(11 downto 0) := None
          - constant csr_mhpmcounter23h_c : std_ulogic_vector(11 downto 0) := None
          - constant csr_mhpmcounter24h_c : std_ulogic_vector(11 downto 0) := None
          - constant csr_mhpmcounter25h_c : std_ulogic_vector(11 downto 0) := None
          - constant csr_mhpmcounter26h_c : std_ulogic_vector(11 downto 0) := None
          - constant csr_mhpmcounter27h_c : std_ulogic_vector(11 downto 0) := None
          - constant csr_mhpmcounter28h_c : std_ulogic_vector(11 downto 0) := None
          - constant csr_mhpmcounter29h_c : std_ulogic_vector(11 downto 0) := None
          - constant csr_mhpmcounter30h_c : std_ulogic_vector(11 downto 0) := None
          - constant csr_mhpmcounter31h_c : std_ulogic_vector(11 downto 0) := None
          - constant csr_cycle_c : std_ulogic_vector(11 downto 0) := None
          - constant csr_time_c : std_ulogic_vector(11 downto 0) := None
          - constant csr_instret_c : std_ulogic_vector(11 downto 0) := None
          - constant csr_cycleh_c : std_ulogic_vector(11 downto 0) := None
          - constant csr_timeh_c : std_ulogic_vector(11 downto 0) := None
          - constant csr_instreth_c : std_ulogic_vector(11 downto 0) := None
          - constant csr_mvendorid_c : std_ulogic_vector(11 downto 0) := None
          - constant csr_marchid_c : std_ulogic_vector(11 downto 0) := None
          - constant csr_mimpid_c : std_ulogic_vector(11 downto 0) := None
          - constant csr_mhartid_c : std_ulogic_vector(11 downto 0) := None
          - constant csr_mconfigptr_c : std_ulogic_vector(11 downto 0) := None
          - constant cp_sel_shifter_c : std_ulogic_vector(1 downto 0) := "00"
          - constant cp_sel_muldiv_c : std_ulogic_vector(1 downto 0) := "01"
          - constant cp_sel_bitmanip_c : std_ulogic_vector(1 downto 0) := "10"
          - constant cp_sel_fpu_c : std_ulogic_vector(1 downto 0) := "11"
          - constant alu_op_add_c : std_ulogic_vector(2 downto 0) := "000"
          - constant alu_op_sub_c : std_ulogic_vector(2 downto 0) := "001"
          - constant alu_op_slt_c : std_ulogic_vector(2 downto 0) := "011"
          - constant alu_op_movb_c : std_ulogic_vector(2 downto 0) := "100"
          - constant alu_op_xor_c : std_ulogic_vector(2 downto 0) := "101"
          - constant alu_op_or_c : std_ulogic_vector(2 downto 0) := "110"
          - constant alu_op_and_c : std_ulogic_vector(2 downto 0) := "111"
          - constant alu_func_core_c : std_ulogic_vector(1 downto 0) := "00"
          - constant alu_func_nxpc_c : std_ulogic_vector(1 downto 0) := "01"
          - constant alu_func_csrr_c : std_ulogic_vector(1 downto 0) := "10"
          - constant alu_func_copro_c : std_ulogic_vector(1 downto 0) := "11"
          - constant trap_ima_c : std_ulogic_vector(6 downto 0) := "0" & "0" & "00000"
          - constant trap_iba_c : std_ulogic_vector(6 downto 0) := "0" & "0" & "00001"
          - constant trap_iil_c : std_ulogic_vector(6 downto 0) := "0" & "0" & "00010"
          - constant trap_brk_c : std_ulogic_vector(6 downto 0) := "0" & "0" & "00011"
          - constant trap_lma_c : std_ulogic_vector(6 downto 0) := "0" & "0" & "00100"
          - constant trap_lbe_c : std_ulogic_vector(6 downto 0) := "0" & "0" & "00101"
          - constant trap_sma_c : std_ulogic_vector(6 downto 0) := "0" & "0" & "00110"
          - constant trap_sbe_c : std_ulogic_vector(6 downto 0) := "0" & "0" & "00111"
          - constant trap_uenv_c : std_ulogic_vector(6 downto 0) := "0" & "0" & "01000"
          - constant trap_menv_c : std_ulogic_vector(6 downto 0) := "0" & "0" & "01011"
          - constant trap_msi_c : std_ulogic_vector(6 downto 0) := "1" & "0" & "00011"
          - constant trap_mti_c : std_ulogic_vector(6 downto 0) := "1" & "0" & "00111"
          - constant trap_mei_c : std_ulogic_vector(6 downto 0) := "1" & "0" & "01011"
          - constant trap_firq0_c : std_ulogic_vector(6 downto 0) := "1" & "0" & "10000"
          - constant trap_firq1_c : std_ulogic_vector(6 downto 0) := "1" & "0" & "10001"
          - constant trap_firq2_c : std_ulogic_vector(6 downto 0) := "1" & "0" & "10010"
          - constant trap_firq3_c : std_ulogic_vector(6 downto 0) := "1" & "0" & "10011"
          - constant trap_firq4_c : std_ulogic_vector(6 downto 0) := "1" & "0" & "10100"
          - constant trap_firq5_c : std_ulogic_vector(6 downto 0) := "1" & "0" & "10101"
          - constant trap_firq6_c : std_ulogic_vector(6 downto 0) := "1" & "0" & "10110"
          - constant trap_firq7_c : std_ulogic_vector(6 downto 0) := "1" & "0" & "10111"
          - constant trap_firq8_c : std_ulogic_vector(6 downto 0) := "1" & "0" & "11000"
          - constant trap_firq9_c : std_ulogic_vector(6 downto 0) := "1" & "0" & "11001"
          - constant trap_firq10_c : std_ulogic_vector(6 downto 0) := "1" & "0" & "11010"
          - constant trap_firq11_c : std_ulogic_vector(6 downto 0) := "1" & "0" & "11011"
          - constant trap_firq12_c : std_ulogic_vector(6 downto 0) := "1" & "0" & "11100"
          - constant trap_firq13_c : std_ulogic_vector(6 downto 0) := "1" & "0" & "11101"
          - constant trap_firq14_c : std_ulogic_vector(6 downto 0) := "1" & "0" & "11110"
          - constant trap_firq15_c : std_ulogic_vector(6 downto 0) := "1" & "0" & "11111"
          - constant trap_db_break_c : std_ulogic_vector(6 downto 0) := "0" & "1" & "00010"
          - constant trap_db_halt_c : std_ulogic_vector(6 downto 0) := "1" & "1" & "00011"
          - constant trap_db_step_c : std_ulogic_vector(6 downto 0) := "1" & "1" & "00100"
          - constant exception_iaccess_c : natural := 0
          - constant exception_iillegal_c : natural := 1
          - constant exception_ialign_c : natural := 2
          - constant exception_m_envcall_c : natural := 3
          - constant exception_u_envcall_c : natural := 4
          - constant exception_break_c : natural := 5
          - constant exception_salign_c : natural := 6
          - constant exception_lalign_c : natural := 7
          - constant exception_saccess_c : natural := 8
          - constant exception_laccess_c : natural := 9
          - constant exception_db_break_c : natural := 10
          - constant exception_width_c : natural := 11
          - constant interrupt_msw_irq_c : natural := 0
          - constant interrupt_mtime_irq_c : natural := 1
          - constant interrupt_mext_irq_c : natural := 2
          - constant interrupt_firq_0_c : natural := 3
          - constant interrupt_firq_1_c : natural := 4
          - constant interrupt_firq_2_c : natural := 5
          - constant interrupt_firq_3_c : natural := 6
          - constant interrupt_firq_4_c : natural := 7
          - constant interrupt_firq_5_c : natural := 8
          - constant interrupt_firq_6_c : natural := 9
          - constant interrupt_firq_7_c : natural := 10
          - constant interrupt_firq_8_c : natural := 11
          - constant interrupt_firq_9_c : natural := 12
          - constant interrupt_firq_10_c : natural := 13
          - constant interrupt_firq_11_c : natural := 14
          - constant interrupt_firq_12_c : natural := 15
          - constant interrupt_firq_13_c : natural := 16
          - constant interrupt_firq_14_c : natural := 17
          - constant interrupt_firq_15_c : natural := 18
          - constant interrupt_db_halt_c : natural := 19
          - constant interrupt_db_step_c : natural := 20
          - constant interrupt_width_c : natural := 21
          - constant priv_mode_m_c : std_ulogic_vector(1 downto 0) := "11"
          - constant priv_mode_u_c : std_ulogic_vector(1 downto 0) := "00"
          - constant hpmcnt_event_cy_c : natural := 0
          - constant hpmcnt_event_never_c : natural := 1
          - constant hpmcnt_event_ir_c : natural := 2
          - constant hpmcnt_event_cir_c : natural := 3
          - constant hpmcnt_event_wait_if_c : natural := 4
          - constant hpmcnt_event_wait_ii_c : natural := 5
          - constant hpmcnt_event_wait_mc_c : natural := 6
          - constant hpmcnt_event_load_c : natural := 7
          - constant hpmcnt_event_store_c : natural := 8
          - constant hpmcnt_event_wait_ls_c : natural := 9
          - constant hpmcnt_event_jump_c : natural := 10
          - constant hpmcnt_event_branch_c : natural := 11
          - constant hpmcnt_event_tbranch_c : natural := 12
          - constant hpmcnt_event_trap_c : natural := 13
          - constant hpmcnt_event_illegal_c : natural := 14
          - constant hpmcnt_event_size_c : natural := 15
          - constant clk_div2_c : natural := 0
          - constant clk_div4_c : natural := 1
          - constant clk_div8_c : natural := 2
          - constant clk_div64_c : natural := 3
          - constant clk_div128_c : natural := 4
          - constant clk_div1024_c : natural := 5
          - constant clk_div2048_c : natural := 6
          - constant clk_div4096_c : natural := 7
          - Component: neorv32_top
            Generics:
              - CLOCK_FREQUENCY : in natural
              - HW_THREAD_ID : in natural := 0
              - INT_BOOTLOADER_EN : in boolean := false
              - ON_CHIP_DEBUGGER_EN : in boolean := false
              - CPU_EXTENSION_RISCV_A : in boolean := false
              - CPU_EXTENSION_RISCV_B : in boolean := false
              - CPU_EXTENSION_RISCV_C : in boolean := false
              - CPU_EXTENSION_RISCV_E : in boolean := false
              - CPU_EXTENSION_RISCV_M : in boolean := false
              - CPU_EXTENSION_RISCV_U : in boolean := false
              - CPU_EXTENSION_RISCV_Zfinx : in boolean := false
              - CPU_EXTENSION_RISCV_Zicsr : in boolean := true
              - CPU_EXTENSION_RISCV_Zicntr : in boolean := true
              - CPU_EXTENSION_RISCV_Zihpm : in boolean := false
              - CPU_EXTENSION_RISCV_Zifencei : in boolean := false
              - CPU_EXTENSION_RISCV_Zmmul : in boolean := false
              - FAST_MUL_EN : in boolean := false
              - FAST_SHIFT_EN : in boolean := false
              - CPU_CNT_WIDTH : in natural := 64
              - CPU_IPB_ENTRIES : in natural := 2
              - PMP_NUM_REGIONS : in natural := 0
              - PMP_MIN_GRANULARITY : in natural := 64 * 1024
              - HPM_NUM_CNTS : in natural := 0
              - HPM_CNT_WIDTH : in natural := 40
              - MEM_INT_IMEM_EN : in boolean := false
              - MEM_INT_IMEM_SIZE : in natural := 16 * 1024
              - MEM_INT_DMEM_EN : in boolean := false
              - MEM_INT_DMEM_SIZE : in natural := 8 * 1024
              - ICACHE_EN : in boolean := false
              - ICACHE_NUM_BLOCKS : in natural := 4
              - ICACHE_BLOCK_SIZE : in natural := 64
              - ICACHE_ASSOCIATIVITY : in natural := 1
              - MEM_EXT_EN : in boolean := false
              - MEM_EXT_TIMEOUT : in natural := 255
              - MEM_EXT_PIPE_MODE : in boolean := false
              - MEM_EXT_BIG_ENDIAN : in boolean := false
              - MEM_EXT_ASYNC_RX : in boolean := false
              - SLINK_NUM_TX : in natural := 0
              - SLINK_NUM_RX : in natural := 0
              - SLINK_TX_FIFO : in natural := 1
              - SLINK_RX_FIFO : in natural := 1
              - XIRQ_NUM_CH : in natural := 0
              - XIRQ_TRIGGER_TYPE : in std_ulogic_vector(31 downto 0)
              - XIRQ_TRIGGER_POLARITY : in std_ulogic_vector(31 downto 0)
              - IO_GPIO_EN : in boolean := false
              - IO_MTIME_EN : in boolean := false
              - IO_UART0_EN : in boolean := false
              - IO_UART0_RX_FIFO : in natural := 1
              - IO_UART0_TX_FIFO : in natural := 1
              - IO_UART1_EN : in boolean := false
              - IO_UART1_RX_FIFO : in natural := 1
              - IO_UART1_TX_FIFO : in natural := 1
              - IO_SPI_EN : in boolean := false
              - IO_TWI_EN : in boolean := false
              - IO_PWM_NUM_CH : in natural := 0
              - IO_WDT_EN : in boolean := false
              - IO_TRNG_EN : in boolean := false
              - IO_CFS_EN : in boolean := false
              - IO_CFS_CONFIG : in std_ulogic_vector(31 downto 0)
              - IO_CFS_IN_SIZE : in positive := 32
              - IO_CFS_OUT_SIZE : in positive := 32
              - IO_NEOLED_EN : in boolean := false
              - IO_NEOLED_TX_FIFO : in natural := 1
              - IO_GPTMR_EN : in boolean := false
            Ports:
              - clk_i : in std_ulogic
              - rstn_i : in std_ulogic
              - jtag_trst_i : in std_ulogic := U
              - jtag_tck_i : in std_ulogic := U
              - jtag_tdi_i : in std_ulogic := U
              - jtag_tdo_o : out std_ulogic
              - jtag_tms_i : in std_ulogic := U
              - wb_tag_o : out std_ulogic_vector(2 downto 0)
              - wb_adr_o : out std_ulogic_vector(31 downto 0)
              - wb_dat_i : in std_ulogic_vector(31 downto 0) := (others => U)
              - wb_dat_o : out std_ulogic_vector(31 downto 0)
              - wb_we_o : out std_ulogic
              - wb_sel_o : out std_ulogic_vector(3 downto 0)
              - wb_stb_o : out std_ulogic
              - wb_cyc_o : out std_ulogic
              - wb_lock_o : out std_ulogic
              - wb_ack_i : in std_ulogic := L
              - wb_err_i : in std_ulogic := L
              - fence_o : out std_ulogic
              - fencei_o : out std_ulogic
              - slink_tx_dat_o : out sdata_8x32_t
              - slink_tx_val_o : out std_ulogic_vector(7 downto 0)
              - slink_tx_rdy_i : in std_ulogic_vector(7 downto 0) := (others => L)
              - slink_rx_dat_i : in sdata_8x32_t := (others => (others => U))
              - slink_rx_val_i : in std_ulogic_vector(7 downto 0) := (others => L)
              - slink_rx_rdy_o : out std_ulogic_vector(7 downto 0)
              - gpio_o : out std_ulogic_vector(63 downto 0)
              - gpio_i : in std_ulogic_vector(63 downto 0) := (others => U)
              - uart0_txd_o : out std_ulogic
              - uart0_rxd_i : in std_ulogic := U
              - uart0_rts_o : out std_ulogic
              - uart0_cts_i : in std_ulogic := L
              - uart1_txd_o : out std_ulogic
              - uart1_rxd_i : in std_ulogic := U
              - uart1_rts_o : out std_ulogic
              - uart1_cts_i : in std_ulogic := L
              - spi_sck_o : out std_ulogic
              - spi_sdo_o : out std_ulogic
              - spi_sdi_i : in std_ulogic := U
              - spi_csn_o : out std_ulogic_vector(7 downto 0)
              - twi_sda_io : inout std_logic := U
              - twi_scl_io : inout std_logic := U
              - pwm_o : out std_ulogic_vector(IO_PWM_NUM_CH - 1 downto 0)
              - cfs_in_i : in std_ulogic_vector(IO_CFS_IN_SIZE - 1 downto 0) := (others => U)
              - cfs_out_o : out std_ulogic_vector(IO_CFS_OUT_SIZE - 1 downto 0)
              - neoled_o : out std_ulogic
              - mtime_i : in std_ulogic_vector(63 downto 0) := (others => U)
              - mtime_o : out std_ulogic_vector(63 downto 0)
              - xirq_i : in std_ulogic_vector(XIRQ_NUM_CH - 1 downto 0) := (others => L)
              - mtime_irq_i : in std_ulogic := L
              - msw_irq_i : in std_ulogic := L
              - mext_irq_i : in std_ulogic := L
          - Component: neorv32_cpu
            Generics:
              - HW_THREAD_ID : in natural
              - CPU_BOOT_ADDR : in std_ulogic_vector(31 downto 0)
              - CPU_DEBUG_ADDR : in std_ulogic_vector(31 downto 0)
              - CPU_EXTENSION_RISCV_A : in boolean
              - CPU_EXTENSION_RISCV_B : in boolean
              - CPU_EXTENSION_RISCV_C : in boolean
              - CPU_EXTENSION_RISCV_E : in boolean
              - CPU_EXTENSION_RISCV_M : in boolean
              - CPU_EXTENSION_RISCV_U : in boolean
              - CPU_EXTENSION_RISCV_Zfinx : in boolean
              - CPU_EXTENSION_RISCV_Zicsr : in boolean
              - CPU_EXTENSION_RISCV_Zicntr : in boolean
              - CPU_EXTENSION_RISCV_Zihpm : in boolean
              - CPU_EXTENSION_RISCV_Zifencei : in boolean
              - CPU_EXTENSION_RISCV_Zmmul : in boolean
              - CPU_EXTENSION_RISCV_DEBUG : in boolean
              - FAST_MUL_EN : in boolean
              - FAST_SHIFT_EN : in boolean
              - CPU_CNT_WIDTH : in natural
              - CPU_IPB_ENTRIES : in natural
              - PMP_NUM_REGIONS : in natural
              - PMP_MIN_GRANULARITY : in natural
              - HPM_NUM_CNTS : in natural
              - HPM_CNT_WIDTH : in natural
            Ports:
              - clk_i : in std_ulogic
              - rstn_i : in std_ulogic
              - sleep_o : out std_ulogic
              - i_bus_addr_o : out std_ulogic_vector(data_width_c - 1 downto 0)
              - i_bus_rdata_i : in std_ulogic_vector(data_width_c - 1 downto 0)
              - i_bus_wdata_o : out std_ulogic_vector(data_width_c - 1 downto 0)
              - i_bus_ben_o : out std_ulogic_vector(3 downto 0)
              - i_bus_we_o : out std_ulogic
              - i_bus_re_o : out std_ulogic
              - i_bus_lock_o : out std_ulogic
              - i_bus_ack_i : in std_ulogic
              - i_bus_err_i : in std_ulogic
              - i_bus_fence_o : out std_ulogic
              - i_bus_priv_o : out std_ulogic_vector(1 downto 0)
              - d_bus_addr_o : out std_ulogic_vector(data_width_c - 1 downto 0)
              - d_bus_rdata_i : in std_ulogic_vector(data_width_c - 1 downto 0)
              - d_bus_wdata_o : out std_ulogic_vector(data_width_c - 1 downto 0)
              - d_bus_ben_o : out std_ulogic_vector(3 downto 0)
              - d_bus_we_o : out std_ulogic
              - d_bus_re_o : out std_ulogic
              - d_bus_lock_o : out std_ulogic
              - d_bus_ack_i : in std_ulogic
              - d_bus_err_i : in std_ulogic
              - d_bus_fence_o : out std_ulogic
              - d_bus_priv_o : out std_ulogic_vector(1 downto 0)
              - time_i : in std_ulogic_vector(63 downto 0)
              - msw_irq_i : in std_ulogic
              - mext_irq_i : in std_ulogic
              - mtime_irq_i : in std_ulogic
              - firq_i : in std_ulogic_vector(15 downto 0)
              - db_halt_req_i : in std_ulogic
          - Component: neorv32_cpu_control
            Generics:
              - HW_THREAD_ID : in natural
              - CPU_BOOT_ADDR : in std_ulogic_vector(31 downto 0)
              - CPU_DEBUG_ADDR : in std_ulogic_vector(31 downto 0)
              - CPU_EXTENSION_RISCV_A : in boolean
              - CPU_EXTENSION_RISCV_B : in boolean
              - CPU_EXTENSION_RISCV_C : in boolean
              - CPU_EXTENSION_RISCV_E : in boolean
              - CPU_EXTENSION_RISCV_M : in boolean
              - CPU_EXTENSION_RISCV_U : in boolean
              - CPU_EXTENSION_RISCV_Zfinx : in boolean
              - CPU_EXTENSION_RISCV_Zicsr : in boolean
              - CPU_EXTENSION_RISCV_Zicntr : in boolean
              - CPU_EXTENSION_RISCV_Zihpm : in boolean
              - CPU_EXTENSION_RISCV_Zifencei : in boolean
              - CPU_EXTENSION_RISCV_Zmmul : in boolean
              - CPU_EXTENSION_RISCV_DEBUG : in boolean
              - CPU_CNT_WIDTH : in natural
              - CPU_IPB_ENTRIES : in natural
              - PMP_NUM_REGIONS : in natural
              - PMP_MIN_GRANULARITY : in natural
              - HPM_NUM_CNTS : in natural
              - HPM_CNT_WIDTH : in natural
            Ports:
              - clk_i : in std_ulogic
              - rstn_i : in std_ulogic
              - ctrl_o : out std_ulogic_vector(ctrl_width_c - 1 downto 0)
              - alu_idone_i : in std_ulogic
              - bus_i_wait_i : in std_ulogic
              - bus_d_wait_i : in std_ulogic
              - excl_state_i : in std_ulogic
              - instr_i : in std_ulogic_vector(data_width_c - 1 downto 0)
              - cmp_i : in std_ulogic_vector(1 downto 0)
              - alu_add_i : in std_ulogic_vector(data_width_c - 1 downto 0)
              - rs1_i : in std_ulogic_vector(data_width_c - 1 downto 0)
              - imm_o : out std_ulogic_vector(data_width_c - 1 downto 0)
              - fetch_pc_o : out std_ulogic_vector(data_width_c - 1 downto 0)
              - curr_pc_o : out std_ulogic_vector(data_width_c - 1 downto 0)
              - next_pc_o : out std_ulogic_vector(data_width_c - 1 downto 0)
              - csr_rdata_o : out std_ulogic_vector(data_width_c - 1 downto 0)
              - fpu_flags_i : in std_ulogic_vector(4 downto 0)
              - db_halt_req_i : in std_ulogic
              - msw_irq_i : in std_ulogic
              - mext_irq_i : in std_ulogic
              - mtime_irq_i : in std_ulogic
              - firq_i : in std_ulogic_vector(15 downto 0)
              - time_i : in std_ulogic_vector(63 downto 0)
              - pmp_addr_o : out pmp_addr_if_t
              - pmp_ctrl_o : out pmp_ctrl_if_t
              - mar_i : in std_ulogic_vector(data_width_c - 1 downto 0)
              - ma_instr_i : in std_ulogic
              - ma_load_i : in std_ulogic
              - ma_store_i : in std_ulogic
              - be_instr_i : in std_ulogic
              - be_load_i : in std_ulogic
              - be_store_i : in std_ulogic
          - Component: neorv32_cpu_regfile
            Generics:
              - CPU_EXTENSION_RISCV_E : in boolean
            Ports:
              - clk_i : in std_ulogic
              - ctrl_i : in std_ulogic_vector(ctrl_width_c - 1 downto 0)
              - mem_i : in std_ulogic_vector(data_width_c - 1 downto 0)
              - alu_i : in std_ulogic_vector(data_width_c - 1 downto 0)
              - rs1_o : out std_ulogic_vector(data_width_c - 1 downto 0)
              - rs2_o : out std_ulogic_vector(data_width_c - 1 downto 0)
          - Component: neorv32_cpu_alu
            Generics:
              - CPU_EXTENSION_RISCV_B : in boolean
              - CPU_EXTENSION_RISCV_M : in boolean
              - CPU_EXTENSION_RISCV_Zmmul : in boolean
              - CPU_EXTENSION_RISCV_Zfinx : in boolean
              - FAST_MUL_EN : in boolean
              - FAST_SHIFT_EN : in boolean
            Ports:
              - clk_i : in std_ulogic
              - rstn_i : in std_ulogic
              - ctrl_i : in std_ulogic_vector(ctrl_width_c - 1 downto 0)
              - rs1_i : in std_ulogic_vector(data_width_c - 1 downto 0)
              - rs2_i : in std_ulogic_vector(data_width_c - 1 downto 0)
              - pc_i : in std_ulogic_vector(data_width_c - 1 downto 0)
              - pc2_i : in std_ulogic_vector(data_width_c - 1 downto 0)
              - imm_i : in std_ulogic_vector(data_width_c - 1 downto 0)
              - csr_i : in std_ulogic_vector(data_width_c - 1 downto 0)
              - cmp_o : out std_ulogic_vector(1 downto 0)
              - res_o : out std_ulogic_vector(data_width_c - 1 downto 0)
              - add_o : out std_ulogic_vector(data_width_c - 1 downto 0)
              - fpu_flags_o : out std_ulogic_vector(4 downto 0)
              - idone_o : out std_ulogic
          - Component: neorv32_cpu_cp_shifter
            Generics:
              - FAST_SHIFT_EN : in boolean
            Ports:
              - clk_i : in std_ulogic
              - rstn_i : in std_ulogic
              - ctrl_i : in std_ulogic_vector(ctrl_width_c - 1 downto 0)
              - start_i : in std_ulogic
              - rs1_i : in std_ulogic_vector(data_width_c - 1 downto 0)
              - shamt_i : in std_ulogic_vector(index_size_f(data_width_c) - 1 downto 0)
              - res_o : out std_ulogic_vector(data_width_c - 1 downto 0)
              - valid_o : out std_ulogic
          - Component: neorv32_cpu_cp_muldiv
            Generics:
              - FAST_MUL_EN : in boolean
              - DIVISION_EN : in boolean
            Ports:
              - clk_i : in std_ulogic
              - rstn_i : in std_ulogic
              - ctrl_i : in std_ulogic_vector(ctrl_width_c - 1 downto 0)
              - start_i : in std_ulogic
              - rs1_i : in std_ulogic_vector(data_width_c - 1 downto 0)
              - rs2_i : in std_ulogic_vector(data_width_c - 1 downto 0)
              - res_o : out std_ulogic_vector(data_width_c - 1 downto 0)
              - valid_o : out std_ulogic
          - Component: neorv32_cpu_cp_bitmanip
            Generics:
              - FAST_SHIFT_EN : in boolean
            Ports:
              - clk_i : in std_ulogic
              - rstn_i : in std_ulogic
              - ctrl_i : in std_ulogic_vector(ctrl_width_c - 1 downto 0)
              - start_i : in std_ulogic
              - cmp_i : in std_ulogic_vector(1 downto 0)
              - rs1_i : in std_ulogic_vector(data_width_c - 1 downto 0)
              - rs2_i : in std_ulogic_vector(data_width_c - 1 downto 0)
              - shamt_i : in std_ulogic_vector(index_size_f(data_width_c) - 1 downto 0)
              - res_o : out std_ulogic_vector(data_width_c - 1 downto 0)
              - valid_o : out std_ulogic
          - Component: neorv32_cpu_cp_fpu
            Generics:
            Ports:
              - clk_i : in std_ulogic
              - rstn_i : in std_ulogic
              - ctrl_i : in std_ulogic_vector(ctrl_width_c - 1 downto 0)
              - start_i : in std_ulogic
              - cmp_i : in std_ulogic_vector(1 downto 0)
              - rs1_i : in std_ulogic_vector(data_width_c - 1 downto 0)
              - rs2_i : in std_ulogic_vector(data_width_c - 1 downto 0)
              - res_o : out std_ulogic_vector(data_width_c - 1 downto 0)
              - fflags_o : out std_ulogic_vector(4 downto 0)
              - valid_o : out std_ulogic
          - Component: neorv32_cpu_bus
            Generics:
              - CPU_EXTENSION_RISCV_A : in boolean
              - CPU_EXTENSION_RISCV_C : in boolean
              - PMP_NUM_REGIONS : in natural
              - PMP_MIN_GRANULARITY : in natural
            Ports:
              - clk_i : in std_ulogic
              - rstn_i : in std_ulogic := 0
              - ctrl_i : in std_ulogic_vector(ctrl_width_c - 1 downto 0)
              - fetch_pc_i : in std_ulogic_vector(data_width_c - 1 downto 0)
              - instr_o : out std_ulogic_vector(data_width_c - 1 downto 0)
              - i_wait_o : out std_ulogic
              - ma_instr_o : out std_ulogic
              - be_instr_o : out std_ulogic
              - addr_i : in std_ulogic_vector(data_width_c - 1 downto 0)
              - wdata_i : in std_ulogic_vector(data_width_c - 1 downto 0)
              - rdata_o : out std_ulogic_vector(data_width_c - 1 downto 0)
              - mar_o : out std_ulogic_vector(data_width_c - 1 downto 0)
              - d_wait_o : out std_ulogic
              - excl_state_o : out std_ulogic
              - ma_load_o : out std_ulogic
              - ma_store_o : out std_ulogic
              - be_load_o : out std_ulogic
              - be_store_o : out std_ulogic
              - pmp_addr_i : in pmp_addr_if_t
              - pmp_ctrl_i : in pmp_ctrl_if_t
              - i_bus_addr_o : out std_ulogic_vector(data_width_c - 1 downto 0)
              - i_bus_rdata_i : in std_ulogic_vector(data_width_c - 1 downto 0)
              - i_bus_wdata_o : out std_ulogic_vector(data_width_c - 1 downto 0)
              - i_bus_ben_o : out std_ulogic_vector(3 downto 0)
              - i_bus_we_o : out std_ulogic
              - i_bus_re_o : out std_ulogic
              - i_bus_lock_o : out std_ulogic
              - i_bus_ack_i : in std_ulogic
              - i_bus_err_i : in std_ulogic
              - i_bus_fence_o : out std_ulogic
              - d_bus_addr_o : out std_ulogic_vector(data_width_c - 1 downto 0)
              - d_bus_rdata_i : in std_ulogic_vector(data_width_c - 1 downto 0)
              - d_bus_wdata_o : out std_ulogic_vector(data_width_c - 1 downto 0)
              - d_bus_ben_o : out std_ulogic_vector(3 downto 0)
              - d_bus_we_o : out std_ulogic
              - d_bus_re_o : out std_ulogic
              - d_bus_lock_o : out std_ulogic
              - d_bus_ack_i : in std_ulogic
              - d_bus_err_i : in std_ulogic
              - d_bus_fence_o : out std_ulogic
          - Component: neorv32_bus_keeper
            Generics:
            Ports:
              - clk_i : in std_ulogic
              - rstn_i : in std_ulogic
              - addr_i : in std_ulogic_vector(31 downto 0)
              - rden_i : in std_ulogic
              - wren_i : in std_ulogic
              - data_o : out std_ulogic_vector(31 downto 0)
              - ack_o : out std_ulogic
              - err_o : out std_ulogic
              - bus_addr_i : in std_ulogic_vector(31 downto 0)
              - bus_rden_i : in std_ulogic
              - bus_wren_i : in std_ulogic
              - bus_ack_i : in std_ulogic
              - bus_err_i : in std_ulogic
              - bus_tmo_i : in std_ulogic
              - bus_ext_i : in std_ulogic
          - Component: neorv32_icache
            Generics:
              - ICACHE_NUM_BLOCKS : in natural
              - ICACHE_BLOCK_SIZE : in natural
              - ICACHE_NUM_SETS : in natural
            Ports:
              - clk_i : in std_ulogic
              - rstn_i : in std_ulogic
              - clear_i : in std_ulogic
              - host_addr_i : in std_ulogic_vector(data_width_c - 1 downto 0)
              - host_rdata_o : out std_ulogic_vector(data_width_c - 1 downto 0)
              - host_wdata_i : in std_ulogic_vector(data_width_c - 1 downto 0)
              - host_ben_i : in std_ulogic_vector(3 downto 0)
              - host_we_i : in std_ulogic
              - host_re_i : in std_ulogic
              - host_ack_o : out std_ulogic
              - host_err_o : out std_ulogic
              - bus_addr_o : out std_ulogic_vector(data_width_c - 1 downto 0)
              - bus_rdata_i : in std_ulogic_vector(data_width_c - 1 downto 0)
              - bus_wdata_o : out std_ulogic_vector(data_width_c - 1 downto 0)
              - bus_ben_o : out std_ulogic_vector(3 downto 0)
              - bus_we_o : out std_ulogic
              - bus_re_o : out std_ulogic
              - bus_ack_i : in std_ulogic
              - bus_err_i : in std_ulogic
          - Component: neorv32_busswitch
            Generics:
              - PORT_CA_READ_ONLY : in boolean
              - PORT_CB_READ_ONLY : in boolean
            Ports:
              - clk_i : in std_ulogic
              - rstn_i : in std_ulogic
              - ca_bus_addr_i : in std_ulogic_vector(data_width_c - 1 downto 0)
              - ca_bus_rdata_o : out std_ulogic_vector(data_width_c - 1 downto 0)
              - ca_bus_wdata_i : in std_ulogic_vector(data_width_c - 1 downto 0)
              - ca_bus_ben_i : in std_ulogic_vector(3 downto 0)
              - ca_bus_we_i : in std_ulogic
              - ca_bus_re_i : in std_ulogic
              - ca_bus_lock_i : in std_ulogic
              - ca_bus_ack_o : out std_ulogic
              - ca_bus_err_o : out std_ulogic
              - cb_bus_addr_i : in std_ulogic_vector(data_width_c - 1 downto 0)
              - cb_bus_rdata_o : out std_ulogic_vector(data_width_c - 1 downto 0)
              - cb_bus_wdata_i : in std_ulogic_vector(data_width_c - 1 downto 0)
              - cb_bus_ben_i : in std_ulogic_vector(3 downto 0)
              - cb_bus_we_i : in std_ulogic
              - cb_bus_re_i : in std_ulogic
              - cb_bus_lock_i : in std_ulogic
              - cb_bus_ack_o : out std_ulogic
              - cb_bus_err_o : out std_ulogic
              - p_bus_src_o : out std_ulogic
              - p_bus_addr_o : out std_ulogic_vector(data_width_c - 1 downto 0)
              - p_bus_rdata_i : in std_ulogic_vector(data_width_c - 1 downto 0)
              - p_bus_wdata_o : out std_ulogic_vector(data_width_c - 1 downto 0)
              - p_bus_ben_o : out std_ulogic_vector(3 downto 0)
              - p_bus_we_o : out std_ulogic
              - p_bus_re_o : out std_ulogic
              - p_bus_lock_o : out std_ulogic
              - p_bus_ack_i : in std_ulogic
              - p_bus_err_i : in std_ulogic
          - Component: neorv32_cpu_decompressor
            Generics:
            Ports:
              - ci_instr16_i : in std_ulogic_vector(15 downto 0)
              - ci_illegal_o : out std_ulogic
              - ci_instr32_o : out std_ulogic_vector(31 downto 0)
          - Component: neorv32_imem
            Generics:
              - IMEM_BASE : in std_ulogic_vector(31 downto 0)
              - IMEM_SIZE : in natural
              - IMEM_AS_IROM : in boolean
            Ports:
              - clk_i : in std_ulogic
              - rden_i : in std_ulogic
              - wren_i : in std_ulogic
              - ben_i : in std_ulogic_vector(3 downto 0)
              - addr_i : in std_ulogic_vector(31 downto 0)
              - data_i : in std_ulogic_vector(31 downto 0)
              - data_o : out std_ulogic_vector(31 downto 0)
              - ack_o : out std_ulogic
          - Component: neorv32_dmem
            Generics:
              - DMEM_BASE : in std_ulogic_vector(31 downto 0)
              - DMEM_SIZE : in natural
            Ports:
              - clk_i : in std_ulogic
              - rden_i : in std_ulogic
              - wren_i : in std_ulogic
              - ben_i : in std_ulogic_vector(3 downto 0)
              - addr_i : in std_ulogic_vector(31 downto 0)
              - data_i : in std_ulogic_vector(31 downto 0)
              - data_o : out std_ulogic_vector(31 downto 0)
              - ack_o : out std_ulogic
          - Component: neorv32_boot_rom
            Generics:
              - BOOTROM_BASE : in std_ulogic_vector(31 downto 0)
            Ports:
              - clk_i : in std_ulogic
              - rden_i : in std_ulogic
              - addr_i : in std_ulogic_vector(31 downto 0)
              - data_o : out std_ulogic_vector(31 downto 0)
              - ack_o : out std_ulogic
          - Component: neorv32_mtime
            Generics:
            Ports:
              - clk_i : in std_ulogic
              - addr_i : in std_ulogic_vector(31 downto 0)
              - rden_i : in std_ulogic
              - wren_i : in std_ulogic
              - data_i : in std_ulogic_vector(31 downto 0)
              - data_o : out std_ulogic_vector(31 downto 0)
              - ack_o : out std_ulogic
              - time_o : out std_ulogic_vector(63 downto 0)
              - irq_o : out std_ulogic
          - Component: neorv32_gpio
            Generics:
            Ports:
              - clk_i : in std_ulogic
              - addr_i : in std_ulogic_vector(31 downto 0)
              - rden_i : in std_ulogic
              - wren_i : in std_ulogic
              - data_i : in std_ulogic_vector(31 downto 0)
              - data_o : out std_ulogic_vector(31 downto 0)
              - ack_o : out std_ulogic
              - gpio_o : out std_ulogic_vector(63 downto 0)
              - gpio_i : in std_ulogic_vector(63 downto 0)
          - Component: neorv32_wdt
            Generics:
            Ports:
              - clk_i : in std_ulogic
              - rstn_i : in std_ulogic
              - rden_i : in std_ulogic
              - wren_i : in std_ulogic
              - addr_i : in std_ulogic_vector(31 downto 0)
              - data_i : in std_ulogic_vector(31 downto 0)
              - data_o : out std_ulogic_vector(31 downto 0)
              - ack_o : out std_ulogic
              - clkgen_en_o : out std_ulogic
              - clkgen_i : in std_ulogic_vector(7 downto 0)
              - irq_o : out std_ulogic
              - rstn_o : out std_ulogic
          - Component: neorv32_uart
            Generics:
              - UART_PRIMARY : in boolean
              - UART_RX_FIFO : in natural
              - UART_TX_FIFO : in natural
            Ports:
              - clk_i : in std_ulogic
              - addr_i : in std_ulogic_vector(31 downto 0)
              - rden_i : in std_ulogic
              - wren_i : in std_ulogic
              - data_i : in std_ulogic_vector(31 downto 0)
              - data_o : out std_ulogic_vector(31 downto 0)
              - ack_o : out std_ulogic
              - clkgen_en_o : out std_ulogic
              - clkgen_i : in std_ulogic_vector(7 downto 0)
              - uart_txd_o : out std_ulogic
              - uart_rxd_i : in std_ulogic
              - uart_rts_o : out std_ulogic
              - uart_cts_i : in std_ulogic
              - irq_rxd_o : out std_ulogic
              - irq_txd_o : out std_ulogic
          - Component: neorv32_spi
            Generics:
            Ports:
              - clk_i : in std_ulogic
              - addr_i : in std_ulogic_vector(31 downto 0)
              - rden_i : in std_ulogic
              - wren_i : in std_ulogic
              - data_i : in std_ulogic_vector(31 downto 0)
              - data_o : out std_ulogic_vector(31 downto 0)
              - ack_o : out std_ulogic
              - clkgen_en_o : out std_ulogic
              - clkgen_i : in std_ulogic_vector(7 downto 0)
              - spi_sck_o : out std_ulogic
              - spi_sdo_o : out std_ulogic
              - spi_sdi_i : in std_ulogic
              - spi_csn_o : out std_ulogic_vector(7 downto 0)
              - irq_o : out std_ulogic
          - Component: neorv32_twi
            Generics:
            Ports:
              - clk_i : in std_ulogic
              - addr_i : in std_ulogic_vector(31 downto 0)
              - rden_i : in std_ulogic
              - wren_i : in std_ulogic
              - data_i : in std_ulogic_vector(31 downto 0)
              - data_o : out std_ulogic_vector(31 downto 0)
              - ack_o : out std_ulogic
              - clkgen_en_o : out std_ulogic
              - clkgen_i : in std_ulogic_vector(7 downto 0)
              - twi_sda_io : inout std_logic
              - twi_scl_io : inout std_logic
              - irq_o : out std_ulogic
          - Component: neorv32_pwm
            Generics:
              - NUM_CHANNELS : in natural
            Ports:
              - clk_i : in std_ulogic
              - addr_i : in std_ulogic_vector(31 downto 0)
              - rden_i : in std_ulogic
              - wren_i : in std_ulogic
              - data_i : in std_ulogic_vector(31 downto 0)
              - data_o : out std_ulogic_vector(31 downto 0)
              - ack_o : out std_ulogic
              - clkgen_en_o : out std_ulogic
              - clkgen_i : in std_ulogic_vector(7 downto 0)
              - pwm_o : out std_ulogic_vector(NUM_CHANNELS - 1 downto 0)
          - Component: neorv32_trng
            Generics:
            Ports:
              - clk_i : in std_ulogic
              - addr_i : in std_ulogic_vector(31 downto 0)
              - rden_i : in std_ulogic
              - wren_i : in std_ulogic
              - data_i : in std_ulogic_vector(31 downto 0)
              - data_o : out std_ulogic_vector(31 downto 0)
              - ack_o : out std_ulogic
          - Component: neorv32_wishbone
            Generics:
              - MEM_INT_IMEM_EN : in boolean
              - MEM_INT_IMEM_SIZE : in natural
              - MEM_INT_DMEM_EN : in boolean
              - MEM_INT_DMEM_SIZE : in natural
              - BUS_TIMEOUT : in natural
              - PIPE_MODE : in boolean
              - BIG_ENDIAN : in boolean
              - ASYNC_RX : in boolean
            Ports:
              - clk_i : in std_ulogic
              - rstn_i : in std_ulogic
              - src_i : in std_ulogic
              - addr_i : in std_ulogic_vector(31 downto 0)
              - rden_i : in std_ulogic
              - wren_i : in std_ulogic
              - ben_i : in std_ulogic_vector(3 downto 0)
              - data_i : in std_ulogic_vector(31 downto 0)
              - data_o : out std_ulogic_vector(31 downto 0)
              - lock_i : in std_ulogic
              - ack_o : out std_ulogic
              - err_o : out std_ulogic
              - tmo_o : out std_ulogic
              - priv_i : in std_ulogic_vector(1 downto 0)
              - ext_o : out std_ulogic
              - wb_tag_o : out std_ulogic_vector(2 downto 0)
              - wb_adr_o : out std_ulogic_vector(31 downto 0)
              - wb_dat_i : in std_ulogic_vector(31 downto 0)
              - wb_dat_o : out std_ulogic_vector(31 downto 0)
              - wb_we_o : out std_ulogic
              - wb_sel_o : out std_ulogic_vector(3 downto 0)
              - wb_stb_o : out std_ulogic
              - wb_cyc_o : out std_ulogic
              - wb_lock_o : out std_ulogic
              - wb_ack_i : in std_ulogic
              - wb_err_i : in std_ulogic
          - Component: neorv32_cfs
            Generics:
              - CFS_CONFIG : in std_ulogic_vector(31 downto 0)
              - CFS_IN_SIZE : in positive
              - CFS_OUT_SIZE : in positive
            Ports:
              - clk_i : in std_ulogic
              - rstn_i : in std_ulogic
              - addr_i : in std_ulogic_vector(31 downto 0)
              - rden_i : in std_ulogic
              - wren_i : in std_ulogic
              - data_i : in std_ulogic_vector(31 downto 0)
              - data_o : out std_ulogic_vector(31 downto 0)
              - ack_o : out std_ulogic
              - err_o : out std_ulogic
              - clkgen_en_o : out std_ulogic
              - clkgen_i : in std_ulogic_vector(7 downto 0)
              - irq_o : out std_ulogic
              - cfs_in_i : in std_ulogic_vector(CFS_IN_SIZE - 1 downto 0)
              - cfs_out_o : out std_ulogic_vector(CFS_OUT_SIZE - 1 downto 0)
          - Component: neorv32_neoled
            Generics:
              - FIFO_DEPTH : in natural
            Ports:
              - clk_i : in std_ulogic
              - addr_i : in std_ulogic_vector(31 downto 0)
              - rden_i : in std_ulogic
              - wren_i : in std_ulogic
              - data_i : in std_ulogic_vector(31 downto 0)
              - data_o : out std_ulogic_vector(31 downto 0)
              - ack_o : out std_ulogic
              - clkgen_en_o : out std_ulogic
              - clkgen_i : in std_ulogic_vector(7 downto 0)
              - irq_o : out std_ulogic
              - neoled_o : out std_ulogic
          - Component: neorv32_slink
            Generics:
              - SLINK_NUM_TX : in natural
              - SLINK_NUM_RX : in natural
              - SLINK_TX_FIFO : in natural
              - SLINK_RX_FIFO : in natural
            Ports:
              - clk_i : in std_ulogic
              - addr_i : in std_ulogic_vector(31 downto 0)
              - rden_i : in std_ulogic
              - wren_i : in std_ulogic
              - data_i : in std_ulogic_vector(31 downto 0)
              - data_o : out std_ulogic_vector(31 downto 0)
              - ack_o : out std_ulogic
              - irq_tx_o : out std_ulogic
              - irq_rx_o : out std_ulogic
              - slink_tx_dat_o : out sdata_8x32_t
              - slink_tx_val_o : out std_ulogic_vector(7 downto 0)
              - slink_tx_rdy_i : in std_ulogic_vector(7 downto 0)
              - slink_rx_dat_i : in sdata_8x32_t
              - slink_rx_val_i : in std_ulogic_vector(7 downto 0)
              - slink_rx_rdy_o : out std_ulogic_vector(7 downto 0)
          - Component: neorv32_xirq
            Generics:
              - XIRQ_NUM_CH : in natural
              - XIRQ_TRIGGER_TYPE : in std_ulogic_vector(31 downto 0)
              - XIRQ_TRIGGER_POLARITY : in std_ulogic_vector(31 downto 0)
            Ports:
              - clk_i : in std_ulogic
              - addr_i : in std_ulogic_vector(31 downto 0)
              - rden_i : in std_ulogic
              - wren_i : in std_ulogic
              - data_i : in std_ulogic_vector(31 downto 0)
              - data_o : out std_ulogic_vector(31 downto 0)
              - ack_o : out std_ulogic
              - xirq_i : in std_ulogic_vector(XIRQ_NUM_CH - 1 downto 0)
              - cpu_irq_o : out std_ulogic
          - Component: neorv32_gptmr
            Generics:
            Ports:
              - clk_i : in std_ulogic
              - addr_i : in std_ulogic_vector(31 downto 0)
              - rden_i : in std_ulogic
              - wren_i : in std_ulogic
              - data_i : in std_ulogic_vector(31 downto 0)
              - data_o : out std_ulogic_vector(31 downto 0)
              - ack_o : out std_ulogic
              - clkgen_en_o : out std_ulogic
              - clkgen_i : in std_ulogic_vector(7 downto 0)
              - irq_o : out std_ulogic
          - Component: neorv32_sysinfo
            Generics:
              - CLOCK_FREQUENCY : in natural
              - INT_BOOTLOADER_EN : in boolean
              - CPU_EXTENSION_RISCV_Zfinx : in boolean
              - CPU_EXTENSION_RISCV_Zicsr : in boolean
              - CPU_EXTENSION_RISCV_Zicntr : in boolean
              - CPU_EXTENSION_RISCV_Zihpm : in boolean
              - CPU_EXTENSION_RISCV_Zifencei : in boolean
              - CPU_EXTENSION_RISCV_Zmmul : in boolean
              - CPU_EXTENSION_RISCV_DEBUG : in boolean
              - FAST_MUL_EN : in boolean
              - FAST_SHIFT_EN : in boolean
              - CPU_CNT_WIDTH : in natural
              - PMP_NUM_REGIONS : in natural
              - MEM_INT_IMEM_EN : in boolean
              - MEM_INT_IMEM_SIZE : in natural
              - MEM_INT_DMEM_EN : in boolean
              - MEM_INT_DMEM_SIZE : in natural
              - ICACHE_EN : in boolean
              - ICACHE_NUM_BLOCKS : in natural
              - ICACHE_BLOCK_SIZE : in natural
              - ICACHE_ASSOCIATIVITY : in natural
              - MEM_EXT_EN : in boolean
              - MEM_EXT_BIG_ENDIAN : in boolean
              - ON_CHIP_DEBUGGER_EN : in boolean
              - IO_GPIO_EN : in boolean
              - IO_MTIME_EN : in boolean
              - IO_UART0_EN : in boolean
              - IO_UART1_EN : in boolean
              - IO_SPI_EN : in boolean
              - IO_TWI_EN : in boolean
              - IO_PWM_NUM_CH : in natural
              - IO_WDT_EN : in boolean
              - IO_TRNG_EN : in boolean
              - IO_CFS_EN : in boolean
              - IO_SLINK_EN : in boolean
              - IO_NEOLED_EN : in boolean
              - IO_XIRQ_NUM_CH : in natural
              - IO_GPTMR_EN : in boolean
            Ports:
              - clk_i : in std_ulogic
              - addr_i : in std_ulogic_vector(31 downto 0)
              - rden_i : in std_ulogic
              - data_o : out std_ulogic_vector(31 downto 0)
              - ack_o : out std_ulogic
          - Component: neorv32_fifo
            Generics:
              - FIFO_DEPTH : in natural
              - FIFO_WIDTH : in natural
              - FIFO_RSYNC : in boolean
              - FIFO_SAFE : in boolean
            Ports:
              - clk_i : in std_ulogic
              - rstn_i : in std_ulogic
              - clear_i : in std_ulogic
              - level_o : out std_ulogic_vector(index_size_f(FIFO_DEPTH) downto 0)
              - half_o : out std_ulogic
              - wdata_i : in std_ulogic_vector(FIFO_WIDTH - 1 downto 0)
              - we_i : in std_ulogic
              - free_o : out std_ulogic
              - re_i : in std_ulogic
              - rdata_o : out std_ulogic_vector(FIFO_WIDTH - 1 downto 0)
              - avail_o : out std_ulogic
          - Component: neorv32_debug_dm
            Generics:
            Ports:
              - clk_i : in std_ulogic
              - rstn_i : in std_ulogic
              - dmi_rstn_i : in std_ulogic
              - dmi_req_valid_i : in std_ulogic
              - dmi_req_ready_o : out std_ulogic
              - dmi_req_addr_i : in std_ulogic_vector(6 downto 0)
              - dmi_req_op_i : in std_ulogic
              - dmi_req_data_i : in std_ulogic_vector(31 downto 0)
              - dmi_resp_valid_o : out std_ulogic
              - dmi_resp_ready_i : in std_ulogic
              - dmi_resp_data_o : out std_ulogic_vector(31 downto 0)
              - dmi_resp_err_o : out std_ulogic
              - cpu_addr_i : in std_ulogic_vector(31 downto 0)
              - cpu_rden_i : in std_ulogic
              - cpu_wren_i : in std_ulogic
              - cpu_data_i : in std_ulogic_vector(31 downto 0)
              - cpu_data_o : out std_ulogic_vector(31 downto 0)
              - cpu_ack_o : out std_ulogic
              - cpu_ndmrstn_o : out std_ulogic
              - cpu_halt_req_o : out std_ulogic
          - Component: neorv32_debug_dtm
            Generics:
              - IDCODE_VERSION : in std_ulogic_vector(3 downto 0)
              - IDCODE_PARTID : in std_ulogic_vector(15 downto 0)
              - IDCODE_MANID : in std_ulogic_vector(10 downto 0)
            Ports:
              - clk_i : in std_ulogic
              - rstn_i : in std_ulogic
              - jtag_trst_i : in std_ulogic
              - jtag_tck_i : in std_ulogic
              - jtag_tdi_i : in std_ulogic
              - jtag_tdo_o : out std_ulogic
              - jtag_tms_i : in std_ulogic
              - dmi_rstn_o : out std_ulogic
              - dmi_req_valid_o : out std_ulogic
              - dmi_req_ready_i : in std_ulogic
              - dmi_req_addr_o : out std_ulogic_vector(6 downto 0)
              - dmi_req_op_o : out std_ulogic
              - dmi_req_data_o : out std_ulogic_vector(31 downto 0)
              - dmi_resp_valid_i : in std_ulogic
              - dmi_resp_ready_o : out std_ulogic
              - dmi_resp_data_i : in std_ulogic_vector(31 downto 0)
              - dmi_resp_err_i : in std_ulogic
      PackageBodies:
        - Name: neorv32_package
          Declared:
          - function index_size_f return natural
          - function cond_sel_natural_f return natural
          - function cond_sel_int_f return integer
          - function cond_sel_stdulogicvector_f return std_ulogic_vector
          - function cond_sel_stdulogic_f return std_ulogic
          - function cond_sel_string_f return string
          - function bool_to_ulogic_f return std_ulogic
          - function or_reduce_f return std_ulogic
          - function and_reduce_f return std_ulogic
          - function xor_reduce_f return std_ulogic
          - function to_hexchar_f return character
          - function hexchar_to_stdulogicvector_f return std_ulogic_vector
          - function bit_rev_f return std_ulogic_vector
          - function is_power_of_two_f return boolean
          - function bswap32_f return std_ulogic_vector
          - function char_to_lower_f return character
          - function str_equal_f return boolean
          - function popcount_f return natural
          - function leading_zeros_f return natural
          - function mem32_init_f return mem32_t
      Configurations:
      Contexts:

Teardown

XPASS test_AllVHDLSources[/home/runner/work/extended-tests/extended-tests/NEORV32/rtl/core/mem/neorv32_dmem.cyclone2.vhd] 0:00:00.249429

Started 2021-11-23 15:22:23
Ended 2021-11-23 15:22:24
Duration 0:00:00.249429
Markers
xfail
Fixtures file

Setup

Call

Captured stdout call
================================================================================
                         pyGHDL.dom - Test Application                          
================================================================================
Parsing file '/home/runner/work/extended-tests/extended-tests/NEORV32/rtl/core/mem/neorv32_dmem.cyclone2.vhd'
[NOT IMPLEMENTED] Concurrent (conditional) signal assignment (label: 'None') at line 79
[NOT IMPLEMENTED] Concurrent (conditional) signal assignment (label: 'None') at line 127
libghdl processing time:  327.302 us
DOM translation time:    4617.726 us

Design:
  Libraries:
    - Name: pretty
      Entities:
      Packages:
      Configurations:
      Contexts:
  Documents:
    - Path: '/home/runner/work/extended-tests/extended-tests/NEORV32/rtl/core/mem/neorv32_dmem.cyclone2.vhd':
      Entities:
      Architectures:
        - Name: neorv32_dmem_rtl
          File: neorv32_dmem.cyclone2.vhd
          Position: 42:13
          Entity: neorv32_dmem
          Declared:
            - constant hi_abb_c : natural := 31
            - constant lo_abb_c : natural := index_size_f(DMEM_SIZE)
            - signal acc_en : std_ulogic
            - signal rdata : std_ulogic_vector(31 downto 0)
            - signal rden : std_ulogic
            - signal addr : std_ulogic_vector(index_size_f(DMEM_SIZE / 4) - 1 downto 0)
            - signal addr_ff : std_ulogic_vector(index_size_f(DMEM_SIZE / 4) - 1 downto 0)
            - signal mem_ram_b0 : mem8_t(0 to DMEM_SIZE / 4 - 1)
            - signal mem_ram_b1 : mem8_t(0 to DMEM_SIZE / 4 - 1)
            - signal mem_ram_b2 : mem8_t(0 to DMEM_SIZE / 4 - 1)
            - signal mem_ram_b3 : mem8_t(0 to DMEM_SIZE / 4 - 1)
            - signal mem_ram_b0_rd, mem_ram_b1_rd, mem_ram_b2_rd, mem_ram_b3_rd : std_ulogic_vector(7 downto 0)
          Hierarchy:
            - mem_access: process(...)
            - bus_feedback: process(...)
          Statements:
            ...
            ...
            ...
            ...
            ...
            ...
            ...
            ...
            ...
            ...
      Packages:
      PackageBodies:
      Configurations:
      Contexts:

Teardown

XPASS test_AllVHDLSources[/home/runner/work/extended-tests/extended-tests/NEORV32/rtl/core/neorv32_cpu_cp_shifter.vhd] 0:00:00.250494

Started 2021-11-23 15:22:24
Ended 2021-11-23 15:22:24
Duration 0:00:00.250494
Markers
xfail
Fixtures file

Setup

Call

Captured stdout call
================================================================================
                         pyGHDL.dom - Test Application                          
================================================================================
Parsing file '/home/runner/work/extended-tests/extended-tests/NEORV32/rtl/core/neorv32_cpu_cp_shifter.vhd'
[NOT IMPLEMENTED] Array_Subtype_Definition
[NOT IMPLEMENTED] Concurrent (conditional) signal assignment (label: 'None') at line 124
libghdl processing time:  350.002 us
DOM translation time:    6159.035 us

Design:
  Libraries:
    - Name: pretty
      Entities:
        - neorv32_cpu_cp_shifter(neorv32_cpu_cp_shifter_rtl)
      Packages:
      Configurations:
      Contexts:
  Documents:
    - Path: '/home/runner/work/extended-tests/extended-tests/NEORV32/rtl/core/neorv32_cpu_cp_shifter.vhd':
      Entities:
        - Name: neorv32_cpu_cp_shifter
          File: neorv32_cpu_cp_shifter.vhd
          Position: 46:7
          Generics:
            - FAST_SHIFT_EN : in boolean
          Ports:
            - clk_i : in std_ulogic
            - rstn_i : in std_ulogic
            - ctrl_i : in std_ulogic_vector(ctrl_width_c - 1 downto 0)
            - start_i : in std_ulogic
            - rs1_i : in std_ulogic_vector(data_width_c - 1 downto 0)
            - shamt_i : in std_ulogic_vector(index_size_f(data_width_c) - 1 downto 0)
            - res_o : out std_ulogic_vector(data_width_c - 1 downto 0)
            - valid_o : out std_ulogic
          Declared:
          Statements:
          Architecures:
          - neorv32_cpu_cp_shifter_rtl
      Architectures:
        - Name: neorv32_cpu_cp_shifter_rtl
          File: neorv32_cpu_cp_shifter.vhd
          Position: 65:13
          Entity: neorv32_cpu_cp_shifter
          Declared:
            - type shifter_t is record ..... end record
            - signal shifter : shifter_t
            - type ???? is array(........) of .....
            - signal bs_level : bs_level_t
            - signal bs_result : std_ulogic_vector(data_width_c - 1 downto 0)
          Hierarchy:
            - serial_shifter_sync: if (FAST_SHIFT_EN = false) generate
                - shifter_unit_sync: process(...)
            - serial_shifter_ctrl: if (FAST_SHIFT_EN = false) generate
            - barrel_shifter_async: if (FAST_SHIFT_EN = true) generate
                - shifter_unit_async: process(...)
            - barrel_shifter_sync: if (FAST_SHIFT_EN = true) generate
                - shifter_unit_sync: process(...)
            - barrel_shifter_ctrl: if (FAST_SHIFT_EN = true) generate
          Statements:
            ...
            ...
            ...
            ...
            ...
      Packages:
      PackageBodies:
      Configurations:
      Contexts:

Teardown

XPASS test_AllVHDLSources[/home/runner/work/extended-tests/extended-tests/NEORV32/rtl/core/mem/neorv32_dmem.default.vhd] 0:00:00.245384

Started 2021-11-23 15:22:24
Ended 2021-11-23 15:22:24
Duration 0:00:00.245384
Markers
xfail
Fixtures file

Setup

Call

Captured stdout call
================================================================================
                         pyGHDL.dom - Test Application                          
================================================================================
Parsing file '/home/runner/work/extended-tests/extended-tests/NEORV32/rtl/core/mem/neorv32_dmem.default.vhd'
[NOT IMPLEMENTED] Concurrent (conditional) signal assignment (label: 'None') at line 78
[NOT IMPLEMENTED] Concurrent (conditional) signal assignment (label: 'None') at line 129
libghdl processing time:  352.802 us
DOM translation time:    4133.424 us

Design:
  Libraries:
    - Name: pretty
      Entities:
      Packages:
      Configurations:
      Contexts:
  Documents:
    - Path: '/home/runner/work/extended-tests/extended-tests/NEORV32/rtl/core/mem/neorv32_dmem.default.vhd':
      Entities:
      Architectures:
        - Name: neorv32_dmem_rtl
          File: neorv32_dmem.default.vhd
          Position: 42:13
          Entity: neorv32_dmem
          Declared:
            - constant hi_abb_c : natural := 31
            - constant lo_abb_c : natural := index_size_f(DMEM_SIZE)
            - signal acc_en : std_ulogic
            - signal rdata : std_ulogic_vector(31 downto 0)
            - signal rden : std_ulogic
            - signal addr : std_ulogic_vector(index_size_f(DMEM_SIZE / 4) - 1 downto 0)
            - signal mem_ram_b0 : mem8_t(0 to DMEM_SIZE / 4 - 1)
            - signal mem_ram_b1 : mem8_t(0 to DMEM_SIZE / 4 - 1)
            - signal mem_ram_b2 : mem8_t(0 to DMEM_SIZE / 4 - 1)
            - signal mem_ram_b3 : mem8_t(0 to DMEM_SIZE / 4 - 1)
            - signal mem_ram_b0_rd, mem_ram_b1_rd, mem_ram_b2_rd, mem_ram_b3_rd : std_ulogic_vector(7 downto 0)
          Hierarchy:
            - mem_access: process(...)
            - bus_feedback: process(...)
          Statements:
            ...
            ...
            ...
            ...
            ...
            ...
      Packages:
      PackageBodies:
      Configurations:
      Contexts:

Teardown

XPASS test_AllVHDLSources[/home/runner/work/extended-tests/extended-tests/NEORV32/rtl/core/mem/neorv32_imem.default.vhd] 0:00:00.246374

Started 2021-11-23 15:22:24
Ended 2021-11-23 15:22:24
Duration 0:00:00.246374
Markers
xfail
Fixtures file

Setup

Call

Captured stdout call
================================================================================
                         pyGHDL.dom - Test Application                          
================================================================================
Parsing file '/home/runner/work/extended-tests/extended-tests/NEORV32/rtl/core/mem/neorv32_imem.default.vhd'
[NOT IMPLEMENTED] Concurrent (conditional) signal assignment (label: 'None') at line 102
[NOT IMPLEMENTED] Concurrent (conditional) signal assignment (label: 'None') at line 176
libghdl processing time:  361.102 us
DOM translation time:    5740.033 us

Design:
  Libraries:
    - Name: pretty
      Entities:
      Packages:
      Configurations:
      Contexts:
  Documents:
    - Path: '/home/runner/work/extended-tests/extended-tests/NEORV32/rtl/core/mem/neorv32_imem.default.vhd':
      Entities:
      Architectures:
        - Name: neorv32_imem_rtl
          File: neorv32_imem.default.vhd
          Position: 46:13
          Entity: neorv32_imem
          Declared:
            - constant hi_abb_c : natural := 31
            - constant lo_abb_c : natural := index_size_f(IMEM_SIZE)
            - signal acc_en : std_ulogic
            - signal rdata : std_ulogic_vector(31 downto 0)
            - signal rden : std_ulogic
            - signal addr : std_ulogic_vector(index_size_f(IMEM_SIZE / 4) - 1 downto 0)
            - constant imem_app_size_c : natural := (application_init_image'length) * 4
            - constant mem_rom : mem32_t(0 to IMEM_SIZE / 4 - 1) := mem32_init_f(application_init_image, IMEM_SIZE / 4)
            - signal mem_rom_rd : std_ulogic_vector(31 downto 0)
            - signal mem_ram_b0 : mem8_t(0 to IMEM_SIZE / 4 - 1)
            - signal mem_ram_b1 : mem8_t(0 to IMEM_SIZE / 4 - 1)
            - signal mem_ram_b2 : mem8_t(0 to IMEM_SIZE / 4 - 1)
            - signal mem_ram_b3 : mem8_t(0 to IMEM_SIZE / 4 - 1)
            - signal mem_b0_rd, mem_b1_rd, mem_b2_rd, mem_b3_rd : std_ulogic_vector(7 downto 0)
          Hierarchy:
            - imem_rom: if (IMEM_AS_IROM = true) generate
                - mem_access: process(...)
            - imem_ram: if (IMEM_AS_IROM = false) generate
                - mem_access: process(...)
            - bus_feedback: process(...)
          Statements:
            ...
            ...
            ...
            ...
            ...
            ...
            ...
            ...
      Packages:
      PackageBodies:
      Configurations:
      Contexts:

Teardown

XPASS test_AllVHDLSources[/home/runner/work/extended-tests/extended-tests/NEORV32/rtl/test_setups/neorv32_test_setup_approm.vhd] 0:00:00.240181

Started 2021-11-23 15:22:24
Ended 2021-11-23 15:22:24
Duration 0:00:00.240181
Markers
xfail
Fixtures file

Setup

Call

Captured stdout call
================================================================================
                         pyGHDL.dom - Test Application                          
================================================================================
Parsing file '/home/runner/work/extended-tests/extended-tests/NEORV32/rtl/test_setups/neorv32_test_setup_approm.vhd'
libghdl processing time:  182.101 us
DOM translation time:    1209.307 us

Design:
  Libraries:
    - Name: pretty
      Entities:
        - neorv32_test_setup_approm(neorv32_test_setup_approm_rtl)
      Packages:
      Configurations:
      Contexts:
  Documents:
    - Path: '/home/runner/work/extended-tests/extended-tests/NEORV32/rtl/test_setups/neorv32_test_setup_approm.vhd':
      Entities:
        - Name: neorv32_test_setup_approm
          File: neorv32_test_setup_approm.vhd
          Position: 42:7
          Generics:
            - CLOCK_FREQUENCY : in natural := 100000000
            - MEM_INT_IMEM_SIZE : in natural := 16 * 1024
            - MEM_INT_DMEM_SIZE : in natural := 8 * 1024
          Ports:
            - clk_i : in std_ulogic
            - rstn_i : in std_ulogic
            - gpio_o : out std_ulogic_vector(7 downto 0)
          Declared:
          Statements:
          Architecures:
          - neorv32_test_setup_approm_rtl
      Architectures:
        - Name: neorv32_test_setup_approm_rtl
          File: neorv32_test_setup_approm.vhd
          Position: 58:13
          Entity: neorv32_test_setup_approm
          Declared:
            - signal con_gpio_o : std_ulogic_vector(63 downto 0)
          Hierarchy:
            - neorv32_top_inst: component neorv32_top
          Statements:
            ...
            ...
      Packages:
      PackageBodies:
      Configurations:
      Contexts:

Teardown

XPASS test_AllVHDLSources[/home/runner/work/extended-tests/extended-tests/NEORV32/rtl/core/mem/neorv32_imem.cyclone2.vhd] 0:00:00.251617

Started 2021-11-23 15:22:24
Ended 2021-11-23 15:22:24
Duration 0:00:00.251617
Markers
xfail
Fixtures file

Setup

Call

Captured stdout call
================================================================================
                         pyGHDL.dom - Test Application                          
================================================================================
Parsing file '/home/runner/work/extended-tests/extended-tests/NEORV32/rtl/core/mem/neorv32_imem.cyclone2.vhd'
[NOT IMPLEMENTED] Concurrent (conditional) signal assignment (label: 'None') at line 103
[NOT IMPLEMENTED] Concurrent (conditional) signal assignment (label: 'None') at line 173
libghdl processing time:  441.202 us
DOM translation time:    6168.936 us

Design:
  Libraries:
    - Name: pretty
      Entities:
      Packages:
      Configurations:
      Contexts:
  Documents:
    - Path: '/home/runner/work/extended-tests/extended-tests/NEORV32/rtl/core/mem/neorv32_imem.cyclone2.vhd':
      Entities:
      Architectures:
        - Name: neorv32_imem_rtl
          File: neorv32_imem.cyclone2.vhd
          Position: 46:13
          Entity: neorv32_imem
          Declared:
            - constant hi_abb_c : natural := 31
            - constant lo_abb_c : natural := index_size_f(IMEM_SIZE)
            - signal acc_en : std_ulogic
            - signal rdata : std_ulogic_vector(31 downto 0)
            - signal rden : std_ulogic
            - signal addr : std_ulogic_vector(index_size_f(IMEM_SIZE / 4) - 1 downto 0)
            - signal addr_ff : std_ulogic_vector(index_size_f(IMEM_SIZE / 4) - 1 downto 0)
            - constant imem_app_size_c : natural := (application_init_image'length) * 4
            - constant mem_rom : mem32_t(0 to IMEM_SIZE / 4 - 1) := mem32_init_f(application_init_image, IMEM_SIZE / 4)
            - signal mem_rom_rd : std_ulogic_vector(31 downto 0)
            - signal mem_ram_b0 : mem8_t(0 to IMEM_SIZE / 4 - 1)
            - signal mem_ram_b1 : mem8_t(0 to IMEM_SIZE / 4 - 1)
            - signal mem_ram_b2 : mem8_t(0 to IMEM_SIZE / 4 - 1)
            - signal mem_ram_b3 : mem8_t(0 to IMEM_SIZE / 4 - 1)
            - signal mem_b0_rd, mem_b1_rd, mem_b2_rd, mem_b3_rd : std_ulogic_vector(7 downto 0)
          Hierarchy:
            - imem_rom: if (IMEM_AS_IROM = true) generate
                - mem_access: process(...)
            - imem_ram: if (IMEM_AS_IROM = false) generate
                - mem_access: process(...)
            - bus_feedback: process(...)
          Statements:
            ...
            ...
            ...
            ...
            ...
            ...
            ...
            ...
      Packages:
      PackageBodies:
      Configurations:
      Contexts:

Teardown

XPASS test_AllVHDLSources[/home/runner/work/extended-tests/extended-tests/NEORV32/sim/neorv32_tb.vhd] 0:00:00.275186

Started 2021-11-23 15:22:24
Ended 2021-11-23 15:22:24
Duration 0:00:00.275186
Markers
xfail
Fixtures file

Setup

Call

Captured stdout call
================================================================================
                         pyGHDL.dom - Test Application                          
================================================================================
Parsing file '/home/runner/work/extended-tests/extended-tests/NEORV32/sim/neorv32_tb.vhd'
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Array_Subtype_Definition
[NOT IMPLEMENTED] Concurrent (conditional) signal assignment (label: 'None') at line 516
[NOT IMPLEMENTED] Concurrent (conditional) signal assignment (label: 'None') at line 517
[NOT IMPLEMENTED] Concurrent (conditional) signal assignment (label: 'None') at line 518
[NOT IMPLEMENTED] Concurrent (conditional) signal assignment (label: 'None') at line 519
libghdl processing time:  1436.108 us
DOM translation time:    21007.021 us

Design:
  Libraries:
    - Name: pretty
      Entities:
        - neorv32_tb(neorv32_tb_rtl)
      Packages:
      Configurations:
      Contexts:
  Documents:
    - Path: '/home/runner/work/extended-tests/extended-tests/NEORV32/sim/neorv32_tb.vhd':
      Entities:
        - Name: neorv32_tb
          File: neorv32_tb.vhd
          Position: 59:7
          Generics:
            - runner_cfg : in string := runner_cfg_default
            - ci_mode : in boolean := false
          Ports:
          Declared:
          Statements:
          Architecures:
          - neorv32_tb_rtl
      Architectures:
        - Name: neorv32_tb_rtl
          File: neorv32_tb.vhd
          Position: 64:13
          Entity: neorv32_tb
          Declared:
            - constant ext_imem_c : boolean := false
            - constant ext_dmem_c : boolean := false
            - constant imem_size_c : natural := 16 * 1024
            - constant dmem_size_c : natural := 8 * 1024
            - constant f_clock_c : natural := 100000000
            - constant baud0_rate_c : natural := 19200
            - constant baud1_rate_c : natural := 19200
            - constant ext_mem_a_base_addr_c : std_ulogic_vector(31 downto 0) := None
            - constant ext_mem_a_size_c : natural := imem_size_c
            - constant ext_mem_a_latency_c : natural := 8
            - constant ext_mem_b_base_addr_c : std_ulogic_vector(31 downto 0) := None
            - constant ext_mem_b_size_c : natural := dmem_size_c
            - constant ext_mem_b_latency_c : natural := 8
            - constant ext_mem_c_base_addr_c : std_ulogic_vector(31 downto 0) := None
            - constant ext_mem_c_size_c : natural := 64
            - constant ext_mem_c_latency_c : natural := 3
            - constant irq_trigger_base_addr_c : std_ulogic_vector(31 downto 0) := None
            - constant int_imem_c : boolean := not ext_imem_c
            - constant int_dmem_c : boolean := not ext_dmem_c
            - constant uart0_baud_val_c : real := real(f_clock_c) / real(baud0_rate_c)
            - constant uart1_baud_val_c : real := real(f_clock_c) / real(baud1_rate_c)
            - constant t_clock_c : time := (1 sec) / f_clock_c
            - signal clk_gen, rst_gen : std_ulogic := 0
            - signal uart0_txd : std_ulogic
            - signal uart0_cts : std_ulogic
            - signal uart1_txd : std_ulogic
            - signal uart1_cts : std_ulogic
            - signal gpio : std_ulogic_vector(63 downto 0)
            - signal twi_scl, twi_sda : std_logic
            - signal spi_data : std_ulogic
            - signal msi_ring, mei_ring : std_ulogic
            - type wishbone_t is record ..... end record
            - signal wb_cpu, wb_mem_a, wb_mem_b, wb_mem_c, wb_irq : wishbone_t
            - type ???? is array(........) of .....
            - signal ext_mem_c_atomic_reservation : std_ulogic := 0
            - signal ext_ram_c : mem32_t(0 to ext_mem_c_size_c / 4 - 1)
            - type ext_mem_t is record ..... end record
            - signal ext_mem_a, ext_mem_b, ext_mem_c : ext_mem_t
            - signal slink_dat : sdata_8x32_t
            - signal slink_val : std_ulogic_vector(7 downto 0)
            - signal slink_rdy : std_ulogic_vector(7 downto 0)
            - signal slink_transmitter_dat, slink_receiver_dat : sdata_8x32_t
            - signal slink_transmitter_val, slink_receiver_val : std_ulogic_vector(7 downto 0)
            - signal slink_transmitter_rdy, slink_receiver_rdy : std_ulogic_vector(7 downto 0)
            - constant uart0_rx_logger : logger_t := get_logger("UART0.RX")
            - constant uart1_rx_logger : logger_t := get_logger("UART1.RX")
            - constant uart0_rx_handle : uart_rx_t := new_uart_rx(uart0_baud_val_c, uart0_rx_logger)
            - constant uart1_rx_handle : uart_rx_t := new_uart_rx(uart1_baud_val_c, uart1_rx_logger)
            - type axi_stream_master_vec_t is array(........) of .....
            - type axi_stream_slave_vec_t is array(........) of .....
            - function init_slink_transmitters return axi_stream_master_vec_t
            - function init_slink_receivers return axi_stream_slave_vec_t
            - constant slink_transmitters : axi_stream_master_vec_t := init_slink_transmitters
            - constant slink_receivers : axi_stream_slave_vec_t := init_slink_receivers
          Hierarchy:
            - test_runner: process(...)
            - None: test_runner_watchdog(...)
            - neorv32_top_inst: component neorv32_top
            - uart0_checker: entity work.uart_rx
            - uart1_checker: entity work.uart_rx
            - slink_transmitters_gen: for idx in slink_transmitters'range generate
                - slink_transmitter: entity vunit_lib.axi_stream_master
            - slink_receivers_gen: for idx in slink_receivers'range generate
                - slink_receiver: entity vunit_lib.axi_stream_slave
            - temporary_connection: for idx in slink_transmitters'range generate
            - generate_ext_imem: if ext_imem_c generate
                - ext_mem_a_access: process(...)
            - generate_ext_imem_false: if (ext_imem_c = false) generate
            - ext_mem_b_access: process(...)
            - ext_mem_c_access: process(...)
            - irq_trigger: process(...)
          Statements:
            ...
            ...
            ...
            ...
            ...
            ...
            ...
            ...
            ...
            ...
            ...
            ...
            ...
            ...
            ...
            ...
            ...
            ...
            ...
            ...
            ...
            ...
            ...
            ...
            ...
            ...
            ...
            ...
            ...
            ...
            ...
            ...
            ...
            ...
            ...
            ...
            ...
            ...
            ...
            ...
            ...
            ...
            ...
            ...
            ...
            ...
            ...
      Packages:
      PackageBodies:
      Configurations:
      Contexts:

Teardown

XPASS test_AllVHDLSources[/home/runner/work/extended-tests/extended-tests/NEORV32/rtl/test_setups/neorv32_test_setup_bootloader.vhd] 0:00:00.242460

Started 2021-11-23 15:22:24
Ended 2021-11-23 15:22:25
Duration 0:00:00.242460
Markers
xfail
Fixtures file

Setup

Call

Captured stdout call
================================================================================
                         pyGHDL.dom - Test Application                          
================================================================================
Parsing file '/home/runner/work/extended-tests/extended-tests/NEORV32/rtl/test_setups/neorv32_test_setup_bootloader.vhd'
libghdl processing time:  204.701 us
DOM translation time:    1456.809 us

Design:
  Libraries:
    - Name: pretty
      Entities:
        - neorv32_test_setup_bootloader(neorv32_test_setup_bootloader_rtl)
      Packages:
      Configurations:
      Contexts:
  Documents:
    - Path: '/home/runner/work/extended-tests/extended-tests/NEORV32/rtl/test_setups/neorv32_test_setup_bootloader.vhd':
      Entities:
        - Name: neorv32_test_setup_bootloader
          File: neorv32_test_setup_bootloader.vhd
          Position: 42:7
          Generics:
            - CLOCK_FREQUENCY : in natural := 100000000
            - MEM_INT_IMEM_SIZE : in natural := 16 * 1024
            - MEM_INT_DMEM_SIZE : in natural := 8 * 1024
          Ports:
            - clk_i : in std_ulogic
            - rstn_i : in std_ulogic
            - gpio_o : out std_ulogic_vector(7 downto 0)
            - uart0_txd_o : out std_ulogic
            - uart0_rxd_i : in std_ulogic
          Declared:
          Statements:
          Architecures:
          - neorv32_test_setup_bootloader_rtl
      Architectures:
        - Name: neorv32_test_setup_bootloader_rtl
          File: neorv32_test_setup_bootloader.vhd
          Position: 61:13
          Entity: neorv32_test_setup_bootloader
          Declared:
            - signal con_gpio_o : std_ulogic_vector(63 downto 0)
          Hierarchy:
            - neorv32_top_inst: component neorv32_top
          Statements:
            ...
            ...
      Packages:
      PackageBodies:
      Configurations:
      Contexts:

Teardown

XFAIL test_AllVHDLSources[/home/runner/work/extended-tests/extended-tests/NEORV32/sim/uart_rx.vhd] 0:00:00.245088

Started 2021-11-23 15:22:24
Ended 2021-11-23 15:22:25
Duration 0:00:00.245088
Markers
xfail
Fixtures file

Setup

Call 

[gw1] linux -- Python 3.9.8 /opt/hostedtoolcache/Python/3.9.8/x64/bin/python

file = '/home/runner/work/extended-tests/extended-tests/NEORV32/sim/uart_rx.vhd'

    @mark.parametrize(
    	"file",
    	getVHDLSources()
    )
    @mark.xfail
    def test_AllVHDLSources(file):
>   	check_call(['ghdl-dom', 'pretty', '-f', str(file)], stderr=STDOUT)

TestDOM.py:25: 
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ 

popenargs = (['ghdl-dom', 'pretty', '-f', '/home/runner/work/extended-tests/extended-tests/NEORV32/sim/uart_rx.vhd'],)
kwargs = {'stderr': -2}, retcode = 6
cmd = ['ghdl-dom', 'pretty', '-f', '/home/runner/work/extended-tests/extended-tests/NEORV32/sim/uart_rx.vhd']

    def check_call(*popenargs, **kwargs):
        """Run command with arguments.  Wait for command to complete.  If
        the exit code was zero then return, otherwise raise
        CalledProcessError.  The CalledProcessError object will have the
        return code in the returncode attribute.
    
        The arguments are the same as for the call function.  Example:
    
        check_call(["ls", "-l"])
        """
        retcode = call(*popenargs, **kwargs)
        if retcode:
            cmd = kwargs.get("args")
            if cmd is None:
                cmd = popenargs[0]
>           raise CalledProcessError(retcode, cmd)
E           subprocess.CalledProcessError: Command '['ghdl-dom', 'pretty', '-f', '/home/runner/work/extended-tests/extended-tests/NEORV32/sim/uart_rx.vhd']' returned non-zero exit status 6.

/opt/hostedtoolcache/Python/3.9.8/x64/lib/python3.9/subprocess.py:373: CalledProcessError
Captured stdout call
================================================================================
                         pyGHDL.dom - Test Application                          
================================================================================
Parsing file '/home/runner/work/extended-tests/extended-tests/NEORV32/sim/uart_rx.vhd'
[NOT IMPLEMENTED] Variable assignment (label: 'None') at line 47
DOM: Unknown statement of kind 'While_Loop_Statement' in elsif branch 'None' at /home/runner/work/extended-tests/extended-tests/NEORV32/sim/uart_rx.vhd:58:6.

Teardown

XPASS test_AllVHDLSources[/home/runner/work/extended-tests/extended-tests/NEORV32/sim/uart_rx_pkg.vhd] 0:00:00.241274

Started 2021-11-23 15:22:25
Ended 2021-11-23 15:22:25
Duration 0:00:00.241274
Markers
xfail
Fixtures file

Setup

Call

Captured stdout call
================================================================================
                         pyGHDL.dom - Test Application                          
================================================================================
Parsing file '/home/runner/work/extended-tests/extended-tests/NEORV32/sim/uart_rx_pkg.vhd'
[NOT IMPLEMENTED] function declaration without body
[NOT IMPLEMENTED] function declaration without body
[NOT IMPLEMENTED] procedure declaration without body
libghdl processing time:  178.801 us
DOM translation time:    997.605 us

Design:
  Libraries:
    - Name: pretty
      Entities:
      Packages:
        - uart_rx_pkg
      Configurations:
      Contexts:
  Documents:
    - Path: '/home/runner/work/extended-tests/extended-tests/NEORV32/sim/uart_rx_pkg.vhd':
      Entities:
      Architectures:
      Packages:
        - Name: uart_rx_pkg
          File: uart_rx_pkg.vhd
          Position: 6:8
          Declared:
          - constant check_uart_msg : msg_type_t := new_msg_type("check_uart")
          - type uart_rx_t is record ..... end record
      PackageBodies:
        - Name: uart_rx_pkg
          Declared:
          - constant uart_rx_logger : logger_t := get_logger("neorv32_lib:uart_rx_pkg")
          - function new_uart_rx return uart_rx_t
          - function as_sync return sync_handle_t
          - procedure check_uart
      Configurations:
      Contexts:

Teardown

XPASS test_AllVHDLSources[/home/runner/work/extended-tests/extended-tests/NEORV32/sim/simple/uart_rx.simple.vhd] 0:00:00.252337

Started 2021-11-23 15:22:25
Ended 2021-11-23 15:22:25
Duration 0:00:00.252337
Markers
xfail
Fixtures file

Setup

Call

Captured stdout call
================================================================================
                         pyGHDL.dom - Test Application                          
================================================================================
Parsing file '/home/runner/work/extended-tests/extended-tests/NEORV32/sim/simple/uart_rx.simple.vhd'
[NOT IMPLEMENTED] Variable assignment (label: 'None') at line 54
libghdl processing time:  196.601 us
DOM translation time:    3268.519 us

Design:
  Libraries:
    - Name: pretty
      Entities:
        - uart_rx_simple(a)
      Packages:
      Configurations:
      Contexts:
  Documents:
    - Path: '/home/runner/work/extended-tests/extended-tests/NEORV32/sim/simple/uart_rx.simple.vhd':
      Entities:
        - Name: uart_rx_simple
          File: uart_rx.simple.vhd
          Position: 8:7
          Generics:
            - name : in string
            - uart_baud_val_c : in real
          Ports:
            - clk : in std_ulogic
            - uart_txd : in std_ulogic
          Declared:
          Statements:
          Architecures:
          - a
      Architectures:
        - Name: a
          File: uart_rx.simple.vhd
          Position: 19:13
          Entity: uart_rx_simple
          Declared:
            - signal uart_rx_sync : std_ulogic_vector(4 downto 0) := (others => 1)
            - signal uart_rx_busy : std_ulogic := 0
            - signal uart_rx_sreg : std_ulogic_vector(8 downto 0) := (others => 0)
            - signal uart_rx_baud_cnt : real
            - signal uart_rx_bitcnt : natural
            - File file_uart_tx_out : text
          Hierarchy:
            - uart_rx_console: process(...)
          Statements:
            ...
      Packages:
      PackageBodies:
      Configurations:
      Contexts:

Teardown

XPASS test_AllVHDLSources[/home/runner/work/extended-tests/extended-tests/NEORV32/sim/simple/neorv32_tb.simple.vhd] 0:00:00.261665

Started 2021-11-23 15:22:25
Ended 2021-11-23 15:22:25
Duration 0:00:00.261665
Markers
xfail
Fixtures file

Setup

Call

Captured stdout call
================================================================================
                         pyGHDL.dom - Test Application                          
================================================================================
Parsing file '/home/runner/work/extended-tests/extended-tests/NEORV32/sim/simple/neorv32_tb.simple.vhd'
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Array_Subtype_Definition
[NOT IMPLEMENTED] Concurrent (conditional) signal assignment (label: 'None') at line 385
[NOT IMPLEMENTED] Concurrent (conditional) signal assignment (label: 'None') at line 386
[NOT IMPLEMENTED] Concurrent (conditional) signal assignment (label: 'None') at line 387
[NOT IMPLEMENTED] Concurrent (conditional) signal assignment (label: 'None') at line 388
libghdl processing time:  1062.706 us
DOM translation time:    15721.691 us

Design:
  Libraries:
    - Name: pretty
      Entities:
        - neorv32_tb_simple(neorv32_tb_simple_rtl)
      Packages:
      Configurations:
      Contexts:
  Documents:
    - Path: '/home/runner/work/extended-tests/extended-tests/NEORV32/sim/simple/neorv32_tb.simple.vhd':
      Entities:
        - Name: neorv32_tb_simple
          File: neorv32_tb.simple.vhd
          Position: 49:7
          Generics:
            - CPU_EXTENSION_RISCV_A : in boolean := true
            - CPU_EXTENSION_RISCV_B : in boolean := true
            - CPU_EXTENSION_RISCV_C : in boolean := true
            - CPU_EXTENSION_RISCV_E : in boolean := false
            - CPU_EXTENSION_RISCV_M : in boolean := true
            - CPU_EXTENSION_RISCV_U : in boolean := true
            - CPU_EXTENSION_RISCV_Zicsr : in boolean := true
            - CPU_EXTENSION_RISCV_Zifencei : in boolean := true
            - EXT_IMEM_C : in boolean := false
            - MEM_INT_IMEM_SIZE : in natural := 16 * 1024
          Ports:
          Declared:
          Statements:
          Architecures:
          - neorv32_tb_simple_rtl
      Architectures:
        - Name: neorv32_tb_simple_rtl
          File: neorv32_tb.simple.vhd
          Position: 64:13
          Entity: neorv32_tb_simple
          Declared:
            - constant ext_dmem_c : boolean := false
            - constant dmem_size_c : natural := 8 * 1024
            - constant f_clock_c : natural := 100000000
            - constant baud0_rate_c : natural := 19200
            - constant baud1_rate_c : natural := 19200
            - constant ext_mem_a_base_addr_c : std_ulogic_vector(31 downto 0) := None
            - constant ext_mem_a_size_c : natural := MEM_INT_IMEM_SIZE
            - constant ext_mem_a_latency_c : natural := 8
            - constant ext_mem_b_base_addr_c : std_ulogic_vector(31 downto 0) := None
            - constant ext_mem_b_size_c : natural := dmem_size_c
            - constant ext_mem_b_latency_c : natural := 8
            - constant ext_mem_c_base_addr_c : std_ulogic_vector(31 downto 0) := None
            - constant ext_mem_c_size_c : natural := 64
            - constant ext_mem_c_latency_c : natural := 3
            - constant irq_trigger_base_addr_c : std_ulogic_vector(31 downto 0) := None
            - constant int_imem_c : boolean := not EXT_IMEM_C
            - constant int_dmem_c : boolean := not ext_dmem_c
            - constant uart0_baud_val_c : real := real(f_clock_c) / real(baud0_rate_c)
            - constant uart1_baud_val_c : real := real(f_clock_c) / real(baud1_rate_c)
            - constant t_clock_c : time := (1 sec) / f_clock_c
            - signal clk_gen, rst_gen : std_ulogic := 0
            - File file_uart0_tx_out : text
            - signal uart0_txd : std_ulogic
            - signal uart0_cts : std_ulogic
            - signal uart1_txd : std_ulogic
            - signal uart1_cts : std_ulogic
            - signal gpio : std_ulogic_vector(63 downto 0)
            - signal twi_scl, twi_sda : std_logic
            - signal spi_data : std_ulogic
            - signal msi_ring, mei_ring : std_ulogic
            - type wishbone_t is record ..... end record
            - signal wb_cpu, wb_mem_a, wb_mem_b, wb_mem_c, wb_irq : wishbone_t
            - type ???? is array(........) of .....
            - signal ext_mem_c_atomic_reservation : std_ulogic := 0
            - signal ext_ram_c : mem32_t(0 to ext_mem_c_size_c / 4 - 1)
            - type ext_mem_t is record ..... end record
            - signal ext_mem_a, ext_mem_b, ext_mem_c : ext_mem_t
            - signal slink_dat : sdata_8x32_t
            - signal slink_val : std_ulogic_vector(7 downto 0)
            - signal slink_rdy : std_ulogic_vector(7 downto 0)
          Hierarchy:
            - neorv32_top_inst: component neorv32_top
            - uart0_checker: entity work.uart_rx_simple
            - uart1_checker: entity work.uart_rx_simple
            - generate_ext_imem: if (EXT_IMEM_C = true) generate
                - ext_mem_a_access: process(...)
            - generate_ext_imem_false: if (EXT_IMEM_C = false) generate
            - ext_mem_b_access: process(...)
            - ext_mem_c_access: process(...)
            - irq_trigger: process(...)
          Statements:
            ...
            ...
            ...
            ...
            ...
            ...
            ...
            ...
            ...
            ...
            ...
            ...
            ...
            ...
            ...
            ...
            ...
            ...
            ...
            ...
            ...
            ...
            ...
            ...
            ...
            ...
            ...
            ...
            ...
            ...
            ...
            ...
            ...
            ...
            ...
            ...
            ...
            ...
            ...
            ...
            ...
            ...
      Packages:
      PackageBodies:
      Configurations:
      Contexts:

Teardown

XPASS test_AllVHDLSources[/home/runner/work/extended-tests/extended-tests/NEORV32/sim/simple/neorv32_imem.iram.simple.vhd] 0:00:00.253459

Started 2021-11-23 15:22:25
Ended 2021-11-23 15:22:25
Duration 0:00:00.253459
Markers
xfail
Fixtures file

Setup

Call

Captured stdout call
================================================================================
                         pyGHDL.dom - Test Application                          
================================================================================
Parsing file '/home/runner/work/extended-tests/extended-tests/NEORV32/sim/simple/neorv32_imem.iram.simple.vhd'
[NOT IMPLEMENTED] Concurrent (conditional) signal assignment (label: 'None') at line 84
[NOT IMPLEMENTED] Concurrent (conditional) signal assignment (label: 'None') at line 133
libghdl processing time:  389.202 us
DOM translation time:    5106.830 us

Design:
  Libraries:
    - Name: pretty
      Entities:
      Packages:
      Configurations:
      Contexts:
  Documents:
    - Path: '/home/runner/work/extended-tests/extended-tests/NEORV32/sim/simple/neorv32_imem.iram.simple.vhd':
      Entities:
      Architectures:
        - Name: neorv32_imem_rtl
          File: neorv32_imem.iram.simple.vhd
          Position: 46:13
          Entity: neorv32_imem
          Declared:
            - constant hi_abb_c : natural := 31
            - constant lo_abb_c : natural := index_size_f(IMEM_SIZE)
            - signal acc_en : std_ulogic
            - signal rdata : std_ulogic_vector(31 downto 0)
            - signal rden : std_ulogic
            - signal addr : std_ulogic_vector(index_size_f(IMEM_SIZE / 4) - 1 downto 0)
            - constant imem_app_size_c : natural := (application_init_image'length) * 4
            - signal mem_ram : mem32_t(0 to IMEM_SIZE / 4 - 1) := mem32_init_f(application_init_image, IMEM_SIZE / 4)
            - signal mem_ram_rd : std_ulogic_vector(31 downto 0)
          Hierarchy:
            - mem_access: process(...)
            - bus_feedback: process(...)
          Statements:
            ...
            ...
            ...
            ...
            ...
            ...
      Packages:
      PackageBodies:
      Configurations:
      Contexts:

Teardown

XPASS test_AllVHDLSources[/home/runner/work/extended-tests/extended-tests/NEORV32/sim/simple/neorv32_imem.simple.vhd] 0:00:00.258997

Started 2021-11-23 15:22:25
Ended 2021-11-23 15:22:25
Duration 0:00:00.258997
Markers
xfail
Fixtures file

Setup

Call

Captured stdout call
================================================================================
                         pyGHDL.dom - Test Application                          
================================================================================
Parsing file '/home/runner/work/extended-tests/extended-tests/NEORV32/sim/simple/neorv32_imem.simple.vhd'
[NOT IMPLEMENTED] Concurrent (conditional) signal assignment (label: 'None') at line 68
[NOT IMPLEMENTED] Variable assignment (label: 'None') at line 81
[NOT IMPLEMENTED] Concurrent (conditional) signal assignment (label: 'None') at line 92
libghdl processing time:  202.201 us
DOM translation time:    2242.313 us

Design:
  Libraries:
    - Name: pretty
      Entities:
      Packages:
      Configurations:
      Contexts:
  Documents:
    - Path: '/home/runner/work/extended-tests/extended-tests/NEORV32/sim/simple/neorv32_imem.simple.vhd':
      Entities:
      Architectures:
        - Name: neorv32_imem_rtl
          File: neorv32_imem.simple.vhd
          Position: 47:13
          Entity: neorv32_imem
          Declared:
            - constant hi_abb_c : natural := 31
            - constant lo_abb_c : natural := index_size_f(IMEM_SIZE)
            - signal acc_en : std_ulogic
            - signal rdata : std_ulogic_vector(31 downto 0)
            - signal rden : std_ulogic
            - signal addr : std_ulogic_vector(index_size_f(IMEM_SIZE / 4) - 1 downto 0)
          Hierarchy:
            - imem_file_access: process(...)
          Statements:
            ...
            ...
            ...
      Packages:
      PackageBodies:
      Configurations:
      Contexts:

Teardown

XFAIL test_AllVHDLSources[/home/runner/work/extended-tests/extended-tests/ghdl-yosys-plugin/testsuite/formal/gates/test_pmux.vhd] 0:00:00.251883

Started 2021-11-23 15:22:25
Ended 2021-11-23 15:22:26
Duration 0:00:00.251883
Markers
xfail
Fixtures file

Setup

Call 

[gw1] linux -- Python 3.9.8 /opt/hostedtoolcache/Python/3.9.8/x64/bin/python

file = '/home/runner/work/extended-tests/extended-tests/ghdl-yosys-plugin/testsuite/formal/gates/test_pmux.vhd'

    @mark.parametrize(
    	"file",
    	getVHDLSources()
    )
    @mark.xfail
    def test_AllVHDLSources(file):
>   	check_call(['ghdl-dom', 'pretty', '-f', str(file)], stderr=STDOUT)

TestDOM.py:25: 
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ 

popenargs = (['ghdl-dom', 'pretty', '-f', '/home/runner/work/extended-tests/extended-tests/ghdl-yosys-plugin/testsuite/formal/gates/test_pmux.vhd'],)
kwargs = {'stderr': -2}, retcode = 1
cmd = ['ghdl-dom', 'pretty', '-f', '/home/runner/work/extended-tests/extended-tests/ghdl-yosys-plugin/testsuite/formal/gates/test_pmux.vhd']

    def check_call(*popenargs, **kwargs):
        """Run command with arguments.  Wait for command to complete.  If
        the exit code was zero then return, otherwise raise
        CalledProcessError.  The CalledProcessError object will have the
        return code in the returncode attribute.
    
        The arguments are the same as for the call function.  Example:
    
        check_call(["ls", "-l"])
        """
        retcode = call(*popenargs, **kwargs)
        if retcode:
            cmd = kwargs.get("args")
            if cmd is None:
                cmd = popenargs[0]
>           raise CalledProcessError(retcode, cmd)
E           subprocess.CalledProcessError: Command '['ghdl-dom', 'pretty', '-f', '/home/runner/work/extended-tests/extended-tests/ghdl-yosys-plugin/testsuite/formal/gates/test_pmux.vhd']' returned non-zero exit status 1.

/opt/hostedtoolcache/Python/3.9.8/x64/lib/python3.9/subprocess.py:373: CalledProcessError
Captured stdout call
================================================================================
                         pyGHDL.dom - Test Application                          
================================================================================
Parsing file '/home/runner/work/extended-tests/extended-tests/ghdl-yosys-plugin/testsuite/formal/gates/test_pmux.vhd'

raised SYSTEM.ASSERTIONS.ASSERT_FAILURE : no field Label

Teardown

XFAIL test_AllVHDLSources[/home/runner/work/extended-tests/extended-tests/ghdl-yosys-plugin/testsuite/formal/ram/wbr_ram.vhd] 0:00:00.235591

Started 2021-11-23 15:22:25
Ended 2021-11-23 15:22:26
Duration 0:00:00.235591
Markers
xfail
Fixtures file

Setup

Call 

[gw0] linux -- Python 3.9.8 /opt/hostedtoolcache/Python/3.9.8/x64/bin/python

file = '/home/runner/work/extended-tests/extended-tests/ghdl-yosys-plugin/testsuite/formal/ram/wbr_ram.vhd'

    @mark.parametrize(
    	"file",
    	getVHDLSources()
    )
    @mark.xfail
    def test_AllVHDLSources(file):
>   	check_call(['ghdl-dom', 'pretty', '-f', str(file)], stderr=STDOUT)

TestDOM.py:25: 
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ 

popenargs = (['ghdl-dom', 'pretty', '-f', '/home/runner/work/extended-tests/extended-tests/ghdl-yosys-plugin/testsuite/formal/ram/wbr_ram.vhd'],)
kwargs = {'stderr': -2}, retcode = 1
cmd = ['ghdl-dom', 'pretty', '-f', '/home/runner/work/extended-tests/extended-tests/ghdl-yosys-plugin/testsuite/formal/ram/wbr_ram.vhd']

    def check_call(*popenargs, **kwargs):
        """Run command with arguments.  Wait for command to complete.  If
        the exit code was zero then return, otherwise raise
        CalledProcessError.  The CalledProcessError object will have the
        return code in the returncode attribute.
    
        The arguments are the same as for the call function.  Example:
    
        check_call(["ls", "-l"])
        """
        retcode = call(*popenargs, **kwargs)
        if retcode:
            cmd = kwargs.get("args")
            if cmd is None:
                cmd = popenargs[0]
>           raise CalledProcessError(retcode, cmd)
E           subprocess.CalledProcessError: Command '['ghdl-dom', 'pretty', '-f', '/home/runner/work/extended-tests/extended-tests/ghdl-yosys-plugin/testsuite/formal/ram/wbr_ram.vhd']' returned non-zero exit status 1.

/opt/hostedtoolcache/Python/3.9.8/x64/lib/python3.9/subprocess.py:373: CalledProcessError
Captured stdout call
================================================================================
                         pyGHDL.dom - Test Application                          
================================================================================
Parsing file '/home/runner/work/extended-tests/extended-tests/ghdl-yosys-plugin/testsuite/formal/ram/wbr_ram.vhd'
[NOT IMPLEMENTED] Array_Subtype_Definition
[NOT IMPLEMENTED] Variable assignment (label: 'None') at line 26

raised SYSTEM.ASSERTIONS.ASSERT_FAILURE : no field Label

Teardown

XFAIL test_AllVHDLSources[/home/runner/work/extended-tests/extended-tests/ghdl-yosys-plugin/testsuite/formal/gates/test_lsr.vhd] 0:00:00.239261

Started 2021-11-23 15:22:26
Ended 2021-11-23 15:22:26
Duration 0:00:00.239261
Markers
xfail
Fixtures file

Setup

Call 

[gw1] linux -- Python 3.9.8 /opt/hostedtoolcache/Python/3.9.8/x64/bin/python

file = '/home/runner/work/extended-tests/extended-tests/ghdl-yosys-plugin/testsuite/formal/gates/test_lsr.vhd'

    @mark.parametrize(
    	"file",
    	getVHDLSources()
    )
    @mark.xfail
    def test_AllVHDLSources(file):
>   	check_call(['ghdl-dom', 'pretty', '-f', str(file)], stderr=STDOUT)

TestDOM.py:25: 
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ 

popenargs = (['ghdl-dom', 'pretty', '-f', '/home/runner/work/extended-tests/extended-tests/ghdl-yosys-plugin/testsuite/formal/gates/test_lsr.vhd'],)
kwargs = {'stderr': -2}, retcode = 1
cmd = ['ghdl-dom', 'pretty', '-f', '/home/runner/work/extended-tests/extended-tests/ghdl-yosys-plugin/testsuite/formal/gates/test_lsr.vhd']

    def check_call(*popenargs, **kwargs):
        """Run command with arguments.  Wait for command to complete.  If
        the exit code was zero then return, otherwise raise
        CalledProcessError.  The CalledProcessError object will have the
        return code in the returncode attribute.
    
        The arguments are the same as for the call function.  Example:
    
        check_call(["ls", "-l"])
        """
        retcode = call(*popenargs, **kwargs)
        if retcode:
            cmd = kwargs.get("args")
            if cmd is None:
                cmd = popenargs[0]
>           raise CalledProcessError(retcode, cmd)
E           subprocess.CalledProcessError: Command '['ghdl-dom', 'pretty', '-f', '/home/runner/work/extended-tests/extended-tests/ghdl-yosys-plugin/testsuite/formal/gates/test_lsr.vhd']' returned non-zero exit status 1.

/opt/hostedtoolcache/Python/3.9.8/x64/lib/python3.9/subprocess.py:373: CalledProcessError
Captured stdout call
================================================================================
                         pyGHDL.dom - Test Application                          
================================================================================
Parsing file '/home/runner/work/extended-tests/extended-tests/ghdl-yosys-plugin/testsuite/formal/gates/test_lsr.vhd'
[NOT IMPLEMENTED] Bit String Literal not supported yet

raised SYSTEM.ASSERTIONS.ASSERT_FAILURE : no field Label

Teardown

XFAIL test_AllVHDLSources[/home/runner/work/extended-tests/extended-tests/ghdl-yosys-plugin/testsuite/formal/gates/test_mod_rem.vhd] 0:00:00.240022

Started 2021-11-23 15:22:26
Ended 2021-11-23 15:22:26
Duration 0:00:00.240022
Markers
xfail
Fixtures file

Setup

Call 

[gw0] linux -- Python 3.9.8 /opt/hostedtoolcache/Python/3.9.8/x64/bin/python

file = '/home/runner/work/extended-tests/extended-tests/ghdl-yosys-plugin/testsuite/formal/gates/test_mod_rem.vhd'

    @mark.parametrize(
    	"file",
    	getVHDLSources()
    )
    @mark.xfail
    def test_AllVHDLSources(file):
>   	check_call(['ghdl-dom', 'pretty', '-f', str(file)], stderr=STDOUT)

TestDOM.py:25: 
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ 

popenargs = (['ghdl-dom', 'pretty', '-f', '/home/runner/work/extended-tests/extended-tests/ghdl-yosys-plugin/testsuite/formal/gates/test_mod_rem.vhd'],)
kwargs = {'stderr': -2}, retcode = 1
cmd = ['ghdl-dom', 'pretty', '-f', '/home/runner/work/extended-tests/extended-tests/ghdl-yosys-plugin/testsuite/formal/gates/test_mod_rem.vhd']

    def check_call(*popenargs, **kwargs):
        """Run command with arguments.  Wait for command to complete.  If
        the exit code was zero then return, otherwise raise
        CalledProcessError.  The CalledProcessError object will have the
        return code in the returncode attribute.
    
        The arguments are the same as for the call function.  Example:
    
        check_call(["ls", "-l"])
        """
        retcode = call(*popenargs, **kwargs)
        if retcode:
            cmd = kwargs.get("args")
            if cmd is None:
                cmd = popenargs[0]
>           raise CalledProcessError(retcode, cmd)
E           subprocess.CalledProcessError: Command '['ghdl-dom', 'pretty', '-f', '/home/runner/work/extended-tests/extended-tests/ghdl-yosys-plugin/testsuite/formal/gates/test_mod_rem.vhd']' returned non-zero exit status 1.

/opt/hostedtoolcache/Python/3.9.8/x64/lib/python3.9/subprocess.py:373: CalledProcessError
Captured stdout call
================================================================================
                         pyGHDL.dom - Test Application                          
================================================================================
Parsing file '/home/runner/work/extended-tests/extended-tests/ghdl-yosys-plugin/testsuite/formal/gates/test_mod_rem.vhd'

raised SYSTEM.ASSERTIONS.ASSERT_FAILURE : no field Label

Teardown

XFAIL test_AllVHDLSources[/home/runner/work/extended-tests/extended-tests/ghdl-yosys-plugin/testsuite/formal/gates/test_lsl.vhd] 0:00:00.235631

Started 2021-11-23 15:22:26
Ended 2021-11-23 15:22:26
Duration 0:00:00.235631
Markers
xfail
Fixtures file

Setup

Call 

[gw1] linux -- Python 3.9.8 /opt/hostedtoolcache/Python/3.9.8/x64/bin/python

file = '/home/runner/work/extended-tests/extended-tests/ghdl-yosys-plugin/testsuite/formal/gates/test_lsl.vhd'

    @mark.parametrize(
    	"file",
    	getVHDLSources()
    )
    @mark.xfail
    def test_AllVHDLSources(file):
>   	check_call(['ghdl-dom', 'pretty', '-f', str(file)], stderr=STDOUT)

TestDOM.py:25: 
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ 

popenargs = (['ghdl-dom', 'pretty', '-f', '/home/runner/work/extended-tests/extended-tests/ghdl-yosys-plugin/testsuite/formal/gates/test_lsl.vhd'],)
kwargs = {'stderr': -2}, retcode = 1
cmd = ['ghdl-dom', 'pretty', '-f', '/home/runner/work/extended-tests/extended-tests/ghdl-yosys-plugin/testsuite/formal/gates/test_lsl.vhd']

    def check_call(*popenargs, **kwargs):
        """Run command with arguments.  Wait for command to complete.  If
        the exit code was zero then return, otherwise raise
        CalledProcessError.  The CalledProcessError object will have the
        return code in the returncode attribute.
    
        The arguments are the same as for the call function.  Example:
    
        check_call(["ls", "-l"])
        """
        retcode = call(*popenargs, **kwargs)
        if retcode:
            cmd = kwargs.get("args")
            if cmd is None:
                cmd = popenargs[0]
>           raise CalledProcessError(retcode, cmd)
E           subprocess.CalledProcessError: Command '['ghdl-dom', 'pretty', '-f', '/home/runner/work/extended-tests/extended-tests/ghdl-yosys-plugin/testsuite/formal/gates/test_lsl.vhd']' returned non-zero exit status 1.

/opt/hostedtoolcache/Python/3.9.8/x64/lib/python3.9/subprocess.py:373: CalledProcessError
Captured stdout call
================================================================================
                         pyGHDL.dom - Test Application                          
================================================================================
Parsing file '/home/runner/work/extended-tests/extended-tests/ghdl-yosys-plugin/testsuite/formal/gates/test_lsl.vhd'
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet

raised SYSTEM.ASSERTIONS.ASSERT_FAILURE : no field Label

Teardown

XFAIL test_AllVHDLSources[/home/runner/work/extended-tests/extended-tests/ghdl-yosys-plugin/testsuite/formal/gates/test_asr.vhd] 0:00:00.228624

Started 2021-11-23 15:22:26
Ended 2021-11-23 15:22:26
Duration 0:00:00.228624
Markers
xfail
Fixtures file

Setup

Call 

[gw0] linux -- Python 3.9.8 /opt/hostedtoolcache/Python/3.9.8/x64/bin/python

file = '/home/runner/work/extended-tests/extended-tests/ghdl-yosys-plugin/testsuite/formal/gates/test_asr.vhd'

    @mark.parametrize(
    	"file",
    	getVHDLSources()
    )
    @mark.xfail
    def test_AllVHDLSources(file):
>   	check_call(['ghdl-dom', 'pretty', '-f', str(file)], stderr=STDOUT)

TestDOM.py:25: 
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ 

popenargs = (['ghdl-dom', 'pretty', '-f', '/home/runner/work/extended-tests/extended-tests/ghdl-yosys-plugin/testsuite/formal/gates/test_asr.vhd'],)
kwargs = {'stderr': -2}, retcode = 1
cmd = ['ghdl-dom', 'pretty', '-f', '/home/runner/work/extended-tests/extended-tests/ghdl-yosys-plugin/testsuite/formal/gates/test_asr.vhd']

    def check_call(*popenargs, **kwargs):
        """Run command with arguments.  Wait for command to complete.  If
        the exit code was zero then return, otherwise raise
        CalledProcessError.  The CalledProcessError object will have the
        return code in the returncode attribute.
    
        The arguments are the same as for the call function.  Example:
    
        check_call(["ls", "-l"])
        """
        retcode = call(*popenargs, **kwargs)
        if retcode:
            cmd = kwargs.get("args")
            if cmd is None:
                cmd = popenargs[0]
>           raise CalledProcessError(retcode, cmd)
E           subprocess.CalledProcessError: Command '['ghdl-dom', 'pretty', '-f', '/home/runner/work/extended-tests/extended-tests/ghdl-yosys-plugin/testsuite/formal/gates/test_asr.vhd']' returned non-zero exit status 1.

/opt/hostedtoolcache/Python/3.9.8/x64/lib/python3.9/subprocess.py:373: CalledProcessError
Captured stdout call
================================================================================
                         pyGHDL.dom - Test Application                          
================================================================================
Parsing file '/home/runner/work/extended-tests/extended-tests/ghdl-yosys-plugin/testsuite/formal/gates/test_asr.vhd'
[NOT IMPLEMENTED] Bit String Literal not supported yet

raised SYSTEM.ASSERTIONS.ASSERT_FAILURE : no field Label

Teardown

XFAIL test_AllVHDLSources[/home/runner/work/extended-tests/extended-tests/ghdl-yosys-plugin/testsuite/formal/gates/test_minmax.vhd] 0:00:00.233514

Started 2021-11-23 15:22:26
Ended 2021-11-23 15:22:26
Duration 0:00:00.233514
Markers
xfail
Fixtures file

Setup

Call 

[gw1] linux -- Python 3.9.8 /opt/hostedtoolcache/Python/3.9.8/x64/bin/python

file = '/home/runner/work/extended-tests/extended-tests/ghdl-yosys-plugin/testsuite/formal/gates/test_minmax.vhd'

    @mark.parametrize(
    	"file",
    	getVHDLSources()
    )
    @mark.xfail
    def test_AllVHDLSources(file):
>   	check_call(['ghdl-dom', 'pretty', '-f', str(file)], stderr=STDOUT)

TestDOM.py:25: 
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ 

popenargs = (['ghdl-dom', 'pretty', '-f', '/home/runner/work/extended-tests/extended-tests/ghdl-yosys-plugin/testsuite/formal/gates/test_minmax.vhd'],)
kwargs = {'stderr': -2}, retcode = 1
cmd = ['ghdl-dom', 'pretty', '-f', '/home/runner/work/extended-tests/extended-tests/ghdl-yosys-plugin/testsuite/formal/gates/test_minmax.vhd']

    def check_call(*popenargs, **kwargs):
        """Run command with arguments.  Wait for command to complete.  If
        the exit code was zero then return, otherwise raise
        CalledProcessError.  The CalledProcessError object will have the
        return code in the returncode attribute.
    
        The arguments are the same as for the call function.  Example:
    
        check_call(["ls", "-l"])
        """
        retcode = call(*popenargs, **kwargs)
        if retcode:
            cmd = kwargs.get("args")
            if cmd is None:
                cmd = popenargs[0]
>           raise CalledProcessError(retcode, cmd)
E           subprocess.CalledProcessError: Command '['ghdl-dom', 'pretty', '-f', '/home/runner/work/extended-tests/extended-tests/ghdl-yosys-plugin/testsuite/formal/gates/test_minmax.vhd']' returned non-zero exit status 1.

/opt/hostedtoolcache/Python/3.9.8/x64/lib/python3.9/subprocess.py:373: CalledProcessError
Captured stdout call
================================================================================
                         pyGHDL.dom - Test Application                          
================================================================================
Parsing file '/home/runner/work/extended-tests/extended-tests/ghdl-yosys-plugin/testsuite/formal/gates/test_minmax.vhd'

raised SYSTEM.ASSERTIONS.ASSERT_FAILURE : no field Label

Teardown

XFAIL test_AllVHDLSources[/home/runner/work/extended-tests/extended-tests/ghdl-yosys-plugin/testsuite/formal/gates/test_abs.vhd] 0:00:00.226129

Started 2021-11-23 15:22:26
Ended 2021-11-23 15:22:26
Duration 0:00:00.226129
Markers
xfail
Fixtures file

Setup

Call 

[gw0] linux -- Python 3.9.8 /opt/hostedtoolcache/Python/3.9.8/x64/bin/python

file = '/home/runner/work/extended-tests/extended-tests/ghdl-yosys-plugin/testsuite/formal/gates/test_abs.vhd'

    @mark.parametrize(
    	"file",
    	getVHDLSources()
    )
    @mark.xfail
    def test_AllVHDLSources(file):
>   	check_call(['ghdl-dom', 'pretty', '-f', str(file)], stderr=STDOUT)

TestDOM.py:25: 
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ 

popenargs = (['ghdl-dom', 'pretty', '-f', '/home/runner/work/extended-tests/extended-tests/ghdl-yosys-plugin/testsuite/formal/gates/test_abs.vhd'],)
kwargs = {'stderr': -2}, retcode = 1
cmd = ['ghdl-dom', 'pretty', '-f', '/home/runner/work/extended-tests/extended-tests/ghdl-yosys-plugin/testsuite/formal/gates/test_abs.vhd']

    def check_call(*popenargs, **kwargs):
        """Run command with arguments.  Wait for command to complete.  If
        the exit code was zero then return, otherwise raise
        CalledProcessError.  The CalledProcessError object will have the
        return code in the returncode attribute.
    
        The arguments are the same as for the call function.  Example:
    
        check_call(["ls", "-l"])
        """
        retcode = call(*popenargs, **kwargs)
        if retcode:
            cmd = kwargs.get("args")
            if cmd is None:
                cmd = popenargs[0]
>           raise CalledProcessError(retcode, cmd)
E           subprocess.CalledProcessError: Command '['ghdl-dom', 'pretty', '-f', '/home/runner/work/extended-tests/extended-tests/ghdl-yosys-plugin/testsuite/formal/gates/test_abs.vhd']' returned non-zero exit status 1.

/opt/hostedtoolcache/Python/3.9.8/x64/lib/python3.9/subprocess.py:373: CalledProcessError
Captured stdout call
================================================================================
                         pyGHDL.dom - Test Application                          
================================================================================
Parsing file '/home/runner/work/extended-tests/extended-tests/ghdl-yosys-plugin/testsuite/formal/gates/test_abs.vhd'

raised SYSTEM.ASSERTIONS.ASSERT_FAILURE : no field Label

Teardown

XPASS test_AllVHDLSources[/home/runner/work/extended-tests/extended-tests/ghdl-yosys-plugin/testsuite/ghdl-issues/issue1307/hdmi_design.vhd] 0:00:00.255636

Started 2021-11-23 15:22:26
Ended 2021-11-23 15:22:27
Duration 0:00:00.255636
Markers
xfail
Fixtures file

Setup

Call

Captured stdout call
================================================================================
                         pyGHDL.dom - Test Application                          
================================================================================
Parsing file '/home/runner/work/extended-tests/extended-tests/ghdl-yosys-plugin/testsuite/ghdl-issues/issue1307/hdmi_design.vhd'
libghdl processing time:  456.003 us
DOM translation time:    5650.433 us

Design:
  Libraries:
    - Name: pretty
      Entities:
        - hdmi_design(Behavioral)
      Packages:
      Configurations:
      Contexts:
  Documents:
    - Path: '/home/runner/work/extended-tests/extended-tests/ghdl-yosys-plugin/testsuite/ghdl-issues/issue1307/hdmi_design.vhd':
      Entities:
        - Name: hdmi_design
          File: hdmi_design.vhd
          Position: 4:7
          Generics:
          Ports:
            - clk100 : in STD_LOGIC
            - led : out std_logic_vector(7 downto 0) := (others => 0)
            - sw : in std_logic_vector(7 downto 0) := (others => 0)
            - debug_pmod : out std_logic_vector(7 downto 0) := (others => 0)
            - hdmi_rx_cec : inout std_logic
            - hdmi_rx_hpa : out std_logic
            - hdmi_rx_scl : in std_logic
            - hdmi_rx_sda : inout std_logic
            - hdmi_rx_txen : out std_logic
            - hdmi_rx_clk_n : in std_logic
            - hdmi_rx_clk_p : in std_logic
            - hdmi_rx_n : in std_logic_vector(2 downto 0)
            - hdmi_rx_p : in std_logic_vector(2 downto 0)
            - hdmi_tx_cec : inout std_logic
            - hdmi_tx_clk_n : out std_logic
            - hdmi_tx_clk_p : out std_logic
            - hdmi_tx_hpd : in std_logic
            - hdmi_tx_rscl : inout std_logic
            - hdmi_tx_rsda : inout std_logic
            - hdmi_tx_p : out std_logic_vector(2 downto 0)
            - hdmi_tx_n : out std_logic_vector(2 downto 0)
            - rs232_tx : out std_logic
          Declared:
          Statements:
          Architecures:
          - Behavioral
      Architectures:
        - Name: Behavioral
          File: hdmi_design.vhd
          Position: 37:13
          Entity: hdmi_design
          Declared:
            - Component: hdmi_io
              Generics:
              Ports:
                - clk100 : in STD_LOGIC
                - clock_locked : out std_logic
                - data_synced : out std_logic
                - debug : out std_logic_vector(7 downto 0)
                - hdmi_rx_cec : inout std_logic
                - hdmi_rx_hpa : out std_logic
                - hdmi_rx_scl : in std_logic
                - hdmi_rx_sda : inout std_logic
                - hdmi_rx_txen : out std_logic
                - hdmi_rx_clk_n : in std_logic
                - hdmi_rx_clk_p : in std_logic
                - hdmi_rx_n : in std_logic_vector(2 downto 0)
                - hdmi_rx_p : in std_logic_vector(2 downto 0)
                - hdmi_tx_cec : inout std_logic
                - hdmi_tx_clk_n : out std_logic
                - hdmi_tx_clk_p : out std_logic
                - hdmi_tx_hpd : in std_logic
                - hdmi_tx_rscl : inout std_logic
                - hdmi_tx_rsda : inout std_logic
                - hdmi_tx_p : out std_logic_vector(2 downto 0)
                - hdmi_tx_n : out std_logic_vector(2 downto 0)
                - pixel_clk : out std_logic
                - in_hdmi_detected : out std_logic
                - in_blank : out std_logic
                - in_hsync : out std_logic
                - in_vsync : out std_logic
                - in_red : out std_logic_vector(7 downto 0)
                - in_green : out std_logic_vector(7 downto 0)
                - in_blue : out std_logic_vector(7 downto 0)
                - is_interlaced : out std_logic
                - is_second_field : out std_logic
                - audio_channel : out std_logic_vector(2 downto 0)
                - audio_de : out std_logic
                - audio_sample : out std_logic_vector(23 downto 0)
                - out_blank : in std_logic
                - out_hsync : in std_logic
                - out_vsync : in std_logic
                - out_red : in std_logic_vector(7 downto 0)
                - out_green : in std_logic_vector(7 downto 0)
                - out_blue : in std_logic_vector(7 downto 0)
                - symbol_sync : out std_logic
                - symbol_ch0 : out std_logic_vector(9 downto 0)
                - symbol_ch1 : out std_logic_vector(9 downto 0)
                - symbol_ch2 : out std_logic_vector(9 downto 0)
            - signal symbol_sync : std_logic
            - signal symbol_ch0 : std_logic_vector(9 downto 0)
            - signal symbol_ch1 : std_logic_vector(9 downto 0)
            - signal symbol_ch2 : std_logic_vector(9 downto 0)
            - signal pixel_clk : std_logic
            - signal in_blank : std_logic
            - signal in_hsync : std_logic
            - signal in_vsync : std_logic
            - signal in_red : std_logic_vector(7 downto 0)
            - signal in_green : std_logic_vector(7 downto 0)
            - signal in_blue : std_logic_vector(7 downto 0)
            - signal is_interlaced : std_logic
            - signal is_second_field : std_logic
            - signal out_blank : std_logic
            - signal out_hsync : std_logic
            - signal out_vsync : std_logic
            - signal out_red : std_logic_vector(7 downto 0)
            - signal out_green : std_logic_vector(7 downto 0)
            - signal out_blue : std_logic_vector(7 downto 0)
            - signal audio_channel : std_logic_vector(2 downto 0)
            - signal audio_de : std_logic
            - signal audio_sample : std_logic_vector(23 downto 0)
            - signal debug : std_logic_vector(7 downto 0)
          Hierarchy:
            - i_hdmi_io: component hdmi_io
          Statements:
            ...
      Packages:
      PackageBodies:
      Configurations:
      Contexts:

Teardown

XPASS test_AllVHDLSources[/home/runner/work/extended-tests/extended-tests/ghdl-yosys-plugin/testsuite/ghdl-issues/issue1309/axis_squarer.vhd] 0:00:00.260827

Started 2021-11-23 15:22:26
Ended 2021-11-23 15:22:27
Duration 0:00:00.260827
Markers
xfail
Fixtures file

Setup

Call

Captured stdout call
================================================================================
                         pyGHDL.dom - Test Application                          
================================================================================
Parsing file '/home/runner/work/extended-tests/extended-tests/ghdl-yosys-plugin/testsuite/ghdl-issues/issue1309/axis_squarer.vhd'
libghdl processing time:  191.201 us
DOM translation time:    3333.720 us

Design:
  Libraries:
    - Name: pretty
      Entities:
        - axis_squarer(Behavioral)
      Packages:
      Configurations:
      Contexts:
  Documents:
    - Path: '/home/runner/work/extended-tests/extended-tests/ghdl-yosys-plugin/testsuite/ghdl-issues/issue1309/axis_squarer.vhd':
      Entities:
        - Name: axis_squarer
          File: axis_squarer.vhd
          Position: 34:7
          Generics:
          Ports:
            - clk : in STD_LOGIC
            - aresetn : in STD_LOGIC
            - s_axis_tdata : in STD_LOGIC_VECTOR(31 downto 0)
            - s_axis_tlast : in STD_LOGIC
            - s_axis_tvalid : in STD_LOGIC
            - s_axis_tready : out STD_LOGIC
            - m_axis_tdata : out STD_LOGIC_VECTOR(31 downto 0)
            - m_axis_tlast : out STD_LOGIC
            - m_axis_tvalid : out STD_LOGIC
            - m_axis_tready : in STD_LOGIC
          Declared:
          Statements:
          Architecures:
          - Behavioral
      Architectures:
        - Name: Behavioral
          File: axis_squarer.vhd
          Position: 48:13
          Entity: axis_squarer
          Declared:
            - signal idle_counter : UNSIGNED(7 downto 0) := (others => 0)
            - signal counter_start_long : UNSIGNED(3 downto 0) := (others => 0)
            - type FSM_STATES is (........)
            - signal fsm : FSM_STATES := IDLE
          Hierarchy:
            - fsm_main: process(...)
            - fsm_axis_handshake_outputs: process(...)
          Statements:
            ...
            ...
      Packages:
      PackageBodies:
      Configurations:
      Contexts:

Teardown

XPASS test_AllVHDLSources[/home/runner/work/extended-tests/extended-tests/ghdl-yosys-plugin/testsuite/ghdl-issues/issue1307/conversion_to_RGB.vhd] 0:00:00.257144

Started 2021-11-23 15:22:27
Ended 2021-11-23 15:22:27
Duration 0:00:00.257144
Markers
xfail
Fixtures file

Setup

Call

Captured stdout call
================================================================================
                         pyGHDL.dom - Test Application                          
================================================================================
Parsing file '/home/runner/work/extended-tests/extended-tests/ghdl-yosys-plugin/testsuite/ghdl-issues/issue1307/conversion_to_RGB.vhd'
libghdl processing time:  88.900 us
DOM translation time:    934.705 us

Design:
  Libraries:
    - Name: pretty
      Entities:
        - conversion_to_RGB(Behavioral)
      Packages:
      Configurations:
      Contexts:
  Documents:
    - Path: '/home/runner/work/extended-tests/extended-tests/ghdl-yosys-plugin/testsuite/ghdl-issues/issue1307/conversion_to_RGB.vhd':
      Entities:
        - Name: conversion_to_RGB
          File: conversion_to_RGB.vhd
          Position: 5:7
          Generics:
          Ports:
            - clk : in std_Logic
            - in_V : in std_logic_vector(11 downto 0)
            - in_W : in std_logic_vector(11 downto 0)
            - out_G : out std_logic_vector(11 downto 0)
            - out_R : out std_logic_vector(11 downto 0)
          Declared:
          Statements:
          Architecures:
          - Behavioral
      Architectures:
        - Name: Behavioral
          File: conversion_to_RGB.vhd
          Position: 14:13
          Entity: conversion_to_RGB
          Declared:
          Hierarchy:
            - clk_proc: process(...)
          Statements:
            ...
      Packages:
      PackageBodies:
      Configurations:
      Contexts:

Teardown

XPASS test_AllVHDLSources[/home/runner/work/extended-tests/extended-tests/ghdl-yosys-plugin/testsuite/ghdl-issues/issue1307/hdmi_io.vhd] 0:00:00.266065

Started 2021-11-23 15:22:27
Ended 2021-11-23 15:22:27
Duration 0:00:00.266065
Markers
xfail
Fixtures file

Setup

Call

Captured stdout call
================================================================================
                         pyGHDL.dom - Test Application                          
================================================================================
Parsing file '/home/runner/work/extended-tests/extended-tests/ghdl-yosys-plugin/testsuite/ghdl-issues/issue1307/hdmi_io.vhd'
libghdl processing time:  268.601 us
DOM translation time:    3138.518 us

Design:
  Libraries:
    - Name: pretty
      Entities:
        - hdmi_io(Behavioral)
      Packages:
      Configurations:
      Contexts:
  Documents:
    - Path: '/home/runner/work/extended-tests/extended-tests/ghdl-yosys-plugin/testsuite/ghdl-issues/issue1307/hdmi_io.vhd':
      Entities:
        - Name: hdmi_io
          File: hdmi_io.vhd
          Position: 4:7
          Generics:
          Ports:
            - clk100 : in STD_LOGIC
            - clock_locked : out std_logic
            - data_synced : out std_logic
            - debug : out std_logic_vector(7 downto 0)
            - hdmi_rx_cec : inout std_logic
            - hdmi_rx_hpa : out std_logic
            - hdmi_rx_scl : in std_logic
            - hdmi_rx_sda : inout std_logic
            - hdmi_rx_txen : out std_logic
            - hdmi_rx_clk_n : in std_logic
            - hdmi_rx_clk_p : in std_logic
            - hdmi_rx_n : in std_logic_vector(2 downto 0)
            - hdmi_rx_p : in std_logic_vector(2 downto 0)
            - hdmi_tx_cec : inout std_logic
            - hdmi_tx_clk_n : out std_logic
            - hdmi_tx_clk_p : out std_logic
            - hdmi_tx_hpd : in std_logic
            - hdmi_tx_rscl : inout std_logic
            - hdmi_tx_rsda : inout std_logic
            - hdmi_tx_p : out std_logic_vector(2 downto 0)
            - hdmi_tx_n : out std_logic_vector(2 downto 0)
            - pixel_clk : out std_logic
            - in_hdmi_detected : out std_logic
            - in_blank : out std_logic
            - in_hsync : out std_logic
            - in_vsync : out std_logic
            - in_red : out std_logic_vector(7 downto 0)
            - in_green : out std_logic_vector(7 downto 0)
            - in_blue : out std_logic_vector(7 downto 0)
            - is_interlaced : out std_logic
            - is_second_field : out std_logic
            - out_blank : in std_logic
            - out_hsync : in std_logic
            - out_vsync : in std_logic
            - out_red : in std_logic_vector(7 downto 0)
            - out_green : in std_logic_vector(7 downto 0)
            - out_blue : in std_logic_vector(7 downto 0)
            - audio_channel : out std_logic_vector(2 downto 0)
            - audio_de : out std_logic
            - audio_sample : out std_logic_vector(23 downto 0)
            - symbol_sync : out std_logic
            - symbol_ch0 : out std_logic_vector(9 downto 0)
            - symbol_ch1 : out std_logic_vector(9 downto 0)
            - symbol_ch2 : out std_logic_vector(9 downto 0)
          Declared:
          Statements:
          Architecures:
          - Behavioral
      Architectures:
        - Name: Behavioral
          File: hdmi_io.vhd
          Position: 79:13
          Entity: hdmi_io
          Declared:
            - signal fourfourfour_V : std_logic_vector(11 downto 0)
            - signal fourfourfour_W : std_logic_vector(11 downto 0)
            - Component: conversion_to_RGB
              Generics:
              Ports:
                - clk : in std_Logic
                - in_V : in std_logic_vector(11 downto 0)
                - in_W : in std_logic_vector(11 downto 0)
                - out_R : out std_logic_vector(11 downto 0)
                - out_G : out std_logic_vector(11 downto 0)
            - signal rgb_R : std_logic_vector(11 downto 0)
            - signal rgb_G : std_logic_vector(11 downto 0)
          Hierarchy:
            - i_conversion_to_rgb: component conversion_to_RGB
          Statements:
            ...
            ...
            ...
      Packages:
      PackageBodies:
      Configurations:
      Contexts:

Teardown

XPASS test_AllVHDLSources[/home/runner/work/extended-tests/extended-tests/ghdl-yosys-plugin/examples/icestick/uart/hdl/uart_tx.vhd] 0:00:00.258977

Started 2021-11-23 15:22:27
Ended 2021-11-23 15:22:27
Duration 0:00:00.258977
Markers
xfail
Fixtures file

Setup

Call

Captured stdout call
================================================================================
                         pyGHDL.dom - Test Application                          
================================================================================
Parsing file '/home/runner/work/extended-tests/extended-tests/ghdl-yosys-plugin/examples/icestick/uart/hdl/uart_tx.vhd'
[NOT IMPLEMENTED] Concurrent (conditional) signal assignment (label: 'None') at line 60
libghdl processing time:  157.001 us
DOM translation time:    2539.714 us

PP: Unhandled subtype kind 'ConstrainedScalarSubtypeSymbol' for signal 'int_cycle_cnt'.

Teardown

XPASS test_AllVHDLSources[/home/runner/work/extended-tests/extended-tests/ghdl-yosys-plugin/examples/icestick/uart/hdl/uart_top.vhd] 0:00:00.255171

Started 2021-11-23 15:22:27
Ended 2021-11-23 15:22:27
Duration 0:00:00.255171
Markers
xfail
Fixtures file

Setup

Call

Captured stdout call
================================================================================
                         pyGHDL.dom - Test Application                          
================================================================================
Parsing file '/home/runner/work/extended-tests/extended-tests/ghdl-yosys-plugin/examples/icestick/uart/hdl/uart_top.vhd'
libghdl processing time:  118.601 us
DOM translation time:    1262.107 us

Design:
  Libraries:
    - Name: pretty
      Entities:
        - uart_top(behavioral)
      Packages:
      Configurations:
      Contexts:
  Documents:
    - Path: '/home/runner/work/extended-tests/extended-tests/ghdl-yosys-plugin/examples/icestick/uart/hdl/uart_top.vhd':
      Entities:
        - Name: uart_top
          File: uart_top.vhd
          Position: 4:7
          Generics:
            - C_BITS : in integer := 8
          Ports:
            - isl_clk : in std_logic
            - isl_data_n : in std_logic
            - osl_data_n : out std_logic
            - osl_ready : out std_logic
          Declared:
          Statements:
          Architecures:
          - behavioral
      Architectures:
        - Name: behavioral
          File: uart_top.vhd
          Position: 16:13
          Entity: uart_top
          Declared:
            - constant C_QUARTZ_FREQ : integer := 12000000
            - constant C_BAUDRATE : integer := 115200
            - constant C_CYCLES_PER_BIT : integer := C_QUARTZ_FREQ / C_BAUDRATE
            - signal sl_valid_out_tx : std_logic := 0
            - signal slv_data_out_tx : std_logic_vector(C_BITS - 1 downto 0) := (others => 0)
          Hierarchy:
            - i_uart_rx: entity work.uart_rx
            - i_uart_tx: entity work.uart_tx
          Statements:
            ...
            ...
      Packages:
      PackageBodies:
      Configurations:
      Contexts:

Teardown

XPASS test_AllVHDLSources[/home/runner/work/extended-tests/extended-tests/ghdl-yosys-plugin/examples/ecp5_versa/pll_mac.vhd] 0:00:00.255561

Started 2021-11-23 15:22:27
Ended 2021-11-23 15:22:27
Duration 0:00:00.255561
Markers
xfail
Fixtures file

Setup

Call

Captured stdout call
================================================================================
                         pyGHDL.dom - Test Application                          
================================================================================
Parsing file '/home/runner/work/extended-tests/extended-tests/ghdl-yosys-plugin/examples/ecp5_versa/pll_mac.vhd'
libghdl processing time:  214.901 us
DOM translation time:    3185.919 us

Design:
  Libraries:
    - Name: pretty
      Entities:
        - pll_mac(Structure)
      Packages:
      Configurations:
      Contexts:
  Documents:
    - Path: '/home/runner/work/extended-tests/extended-tests/ghdl-yosys-plugin/examples/ecp5_versa/pll_mac.vhd':
      Entities:
        - Name: pll_mac
          File: pll_mac.vhd
          Position: 12:7
          Generics:
          Ports:
            - CLKI : in std_logic
            - CLKOP : out std_logic
            - CLKOS : out std_logic
            - CLKOS2 : out std_logic
            - CLKOS3 : out std_logic
            - LOCK : out std_logic
          Declared:
          Statements:
          Architecures:
          - Structure
      Architectures:
        - Name: Structure
          File: pll_mac.vhd
          Position: 22:13
          Entity: pll_mac
          Declared:
            - signal REFCLK : std_logic
            - signal CLKOS3_t : std_logic
            - signal CLKOS2_t : std_logic
            - signal CLKOS_t : std_logic
            - signal CLKOP_t : std_logic
            - signal scuba_vhi : std_logic
            - signal scuba_vlo : std_logic
            - attribute FREQUENCY_PIN_CLKOS3 : string
            - attribute FREQUENCY_PIN_CLKOS2 : string
            - attribute FREQUENCY_PIN_CLKOS : string
            - attribute FREQUENCY_PIN_CLKOP : string
            - attribute FREQUENCY_PIN_CLKI : string
            - attribute ICP_CURRENT : string
            - attribute LPF_RESISTOR : string
            - attribute FREQUENCY_PIN_CLKOS3 of ???? : ???? is ????
            - attribute FREQUENCY_PIN_CLKOS2 of ???? : ???? is ????
            - attribute FREQUENCY_PIN_CLKOS of ???? : ???? is ????
            - attribute FREQUENCY_PIN_CLKOP of ???? : ???? is ????
            - attribute FREQUENCY_PIN_CLKI of ???? : ???? is ????
            - attribute ICP_CURRENT of ???? : ???? is ????
            - attribute LPF_RESISTOR of ???? : ???? is ????
            - attribute syn_keep : boolean
            - attribute NGD_DRC_MASK : integer
            - attribute NGD_DRC_MASK of ???? : ???? is ????
          Hierarchy:
            - scuba_vhi_inst: component VHI
            - scuba_vlo_inst: component VLO
            - pllinst_0: component EHXPLLL
          Statements:
            ...
            ...
            ...
            ...
            ...
            ...
            ...
      Packages:
      PackageBodies:
      Configurations:
      Contexts:

Teardown

XPASS test_AllVHDLSources[/home/runner/work/extended-tests/extended-tests/ghdl-yosys-plugin/examples/icestick/uart/hdl/uart_rx.vhd] 0:00:00.263335

Started 2021-11-23 15:22:27
Ended 2021-11-23 15:22:28
Duration 0:00:00.263335
Markers
xfail
Fixtures file

Setup

Call

Captured stdout call
================================================================================
                         pyGHDL.dom - Test Application                          
================================================================================
Parsing file '/home/runner/work/extended-tests/extended-tests/ghdl-yosys-plugin/examples/icestick/uart/hdl/uart_rx.vhd'
libghdl processing time:  184.301 us
DOM translation time:    2556.115 us

PP: Unhandled subtype kind 'ConstrainedScalarSubtypeSymbol' for signal 'int_cycle_cnt'.

Teardown

XPASS test_AllVHDLSources[/home/runner/work/extended-tests/extended-tests/ghdl/testsuite/synth/issue1122/mult_pkg.vhd] 0:00:00.255145

Started 2021-11-23 15:22:27
Ended 2021-11-23 15:22:28
Duration 0:00:00.255145
Markers
xfail
Fixtures file

Setup

Call

Captured stdout call
================================================================================
                         pyGHDL.dom - Test Application                          
================================================================================
Parsing file '/home/runner/work/extended-tests/extended-tests/ghdl/testsuite/synth/issue1122/mult_pkg.vhd'
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Array_Subtype_Definition
[NOT IMPLEMENTED] function declaration without body
libghdl processing time:  312.002 us
DOM translation time:    5486.232 us

Design:
  Libraries:
    - Name: pretty
      Entities:
      Packages:
        - mult_pkg
      Configurations:
      Contexts:
  Documents:
    - Path: '/home/runner/work/extended-tests/extended-tests/ghdl/testsuite/synth/issue1122/mult_pkg.vhd':
      Entities:
      Architectures:
      Packages:
        - Name: mult_pkg
          File: mult_pkg.vhd
          Position: 5:8
          Declared:
          - type mult_state_t is (........)
          - type mult_result_op_t is (........)
          - type mult_sela_t is (........)
          - type mult_size_t is (........)
          - constant P48MAX : std_logic_vector(63 downto 0) := None
          - constant N48MAX : std_logic_vector(63 downto 0) := None
          - constant P32MAX : std_logic_vector(63 downto 0) := None
          - constant N32MAX : std_logic_vector(63 downto 0) := None
          - type mult_codeline_t is record ..... end record
          - type ???? is array(........) of .....
          - constant MULT_CODE : mult_microcode_t := ((NOP, 0, M1, 0, 0, B16, 0, 0, 1), (DMULSL1, 1, M1, 0, 1, B32, 0, 0, 1), (DMULSL2, 1, M1, 1, 1, B32, 1, 1, 1), (NOP, 0, M1, 1, 1, B32, 1, 1, 1), (DMULUL1, 1, M1, 0, 0, B32, 0, 0, 1), (DMULUL2, 1, M1, 1, 0, B32, 1, 1, 1), (NOP, 0, M1, 1, 0, B32, 1, 1, 1), (MACL1, 1, MB, 0, 1, B32, 0, 0, 1), (MACL2, 1, MB, 1, 1, B32, 1, 1, 1), (NOP, 0, MB, 1, 1, B32, 1, 1, 1), (MACW1, 1, M1, 0, 1, B16, 0, 0, 1), (NOP, 0, M1, 0, 1, B16, 1, 1, 1), (MACWS1, 1, M1, 0, 1, B16, 0, 0, 0), (NOP, 0, M1, 0, 1, B16, 0, 1, 0), (MULL1, 1, M1, 0, 1, B32, 0, 0, 0), (MULL2, 1, M1, 1, 1, B32, 0, 1, 0), (NOP, 0, M1, 1, 1, B32, 0, 1, 0), (MULSW1, 1, M1, 0, 1, B16, 0, 0, 0), (NOP, 0, M1, 0, 1, B16, 0, 1, 0), (MULUW1, 1, M1, 0, 0, B16, 0, 0, 0), (NOP, 0, M1, 0, 0, B16, 0, 1, 0))
          - type mult_i_t is record ..... end record
          - type mult_o_t is record ..... end record
          - type mult_reg_t is record ..... end record
          - constant MULT_RESET : mult_reg_t := (state => NOP, result_op => IDENTITY, m1 => (others => 0), m2 => (others => 0), mb => (others => 0), p23 => (others => 0), mach => (others => 0), macl => (others => 0), shift => 0, abh => (others => 0))
          - Component: mult
            Generics:
            Ports:
              - clk : in std_logic
              - rst : in std_logic
              - slot : in std_logic
              - a : in mult_i_t
              - y : out mult_o_t
      PackageBodies:
        - Name: mult_pkg
          Declared:
          - function to_slv return std_logic_vector
      Configurations:
      Contexts:

Teardown

XPASS test_AllVHDLSources[/home/runner/work/extended-tests/extended-tests/ghdl/testsuite/synth/issue1122/mult.vhd] 0:00:00.257573

Started 2021-11-23 15:22:28
Ended 2021-11-23 15:22:28
Duration 0:00:00.257573
Markers
xfail
Fixtures file

Setup

Call

Captured stdout call
================================================================================
                         pyGHDL.dom - Test Application                          
================================================================================
Parsing file '/home/runner/work/extended-tests/extended-tests/ghdl/testsuite/synth/issue1122/mult.vhd'
[NOT IMPLEMENTED] Variable assignment (label: 'None') at line 35
[NOT IMPLEMENTED] Variable assignment (label: 'None') at line 37
[NOT IMPLEMENTED] Variable assignment (label: 'None') at line 41
[NOT IMPLEMENTED] Variable assignment (label: 'None') at line 42
[NOT IMPLEMENTED] Variable assignment (label: 'None') at line 44
[NOT IMPLEMENTED] Variable assignment (label: 'None') at line 45
[NOT IMPLEMENTED] Variable assignment (label: 'None') at line 47
[NOT IMPLEMENTED] Variable assignment (label: 'None') at line 48
[NOT IMPLEMENTED] Variable assignment (label: 'None') at line 49
[NOT IMPLEMENTED] Variable assignment (label: 'None') at line 52
[NOT IMPLEMENTED] Variable assignment (label: 'None') at line 53
[NOT IMPLEMENTED] Variable assignment (label: 'None') at line 54
[NOT IMPLEMENTED] Variable assignment (label: 'None') at line 57
[NOT IMPLEMENTED] Variable assignment (label: 'None') at line 58
[NOT IMPLEMENTED] Variable assignment (label: 'None') at line 59
[NOT IMPLEMENTED] Variable assignment (label: 'None') at line 61
[NOT IMPLEMENTED] Variable assignment (label: 'None') at line 62
[NOT IMPLEMENTED] Variable assignment (label: 'None') at line 63
[NOT IMPLEMENTED] Variable assignment (label: 'None') at line 65
[NOT IMPLEMENTED] Variable assignment (label: 'None') at line 65
[NOT IMPLEMENTED] Variable assignment (label: 'None') at line 66
[NOT IMPLEMENTED] Variable assignment (label: 'None') at line 68
[NOT IMPLEMENTED] Variable assignment (label: 'None') at line 71
[NOT IMPLEMENTED] Variable assignment (label: 'None') at line 72
[NOT IMPLEMENTED] Variable assignment (label: 'None') at line 73
[NOT IMPLEMENTED] Variable assignment (label: 'None') at line 77
[NOT IMPLEMENTED] Variable assignment (label: 'None') at line 80
[NOT IMPLEMENTED] Variable assignment (label: 'None') at line 80
[NOT IMPLEMENTED] Variable assignment (label: 'None') at line 82
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Variable assignment (label: 'None') at line 85
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Variable assignment (label: 'None') at line 86
[NOT IMPLEMENTED] Variable assignment (label: 'None') at line 88
[NOT IMPLEMENTED] Variable assignment (label: 'None') at line 92
[NOT IMPLEMENTED] Variable assignment (label: 'None') at line 94
[NOT IMPLEMENTED] Variable assignment (label: 'None') at line 98
[NOT IMPLEMENTED] Variable assignment (label: 'None') at line 100
[NOT IMPLEMENTED] Variable assignment (label: 'None') at line 105
[NOT IMPLEMENTED] Variable assignment (label: 'None') at line 109
[NOT IMPLEMENTED] Variable assignment (label: 'None') at line 114
[NOT IMPLEMENTED] Variable assignment (label: 'None') at line 120
[NOT IMPLEMENTED] Variable assignment (label: 'None') at line 125
[NOT IMPLEMENTED] Variable assignment (label: 'None') at line 126
[NOT IMPLEMENTED] Variable assignment (label: 'None') at line 129
[NOT IMPLEMENTED] Variable assignment (label: 'None') at line 132
[NOT IMPLEMENTED] Variable assignment (label: 'None') at line 133
[NOT IMPLEMENTED] Variable assignment (label: 'None') at line 134
[NOT IMPLEMENTED] Variable assignment (label: 'None') at line 135
[NOT IMPLEMENTED] Variable assignment (label: 'None') at line 138
[NOT IMPLEMENTED] Variable assignment (label: 'None') at line 139
[NOT IMPLEMENTED] Variable assignment (label: 'None') at line 140
[NOT IMPLEMENTED] Variable assignment (label: 'None') at line 144
[NOT IMPLEMENTED] Variable assignment (label: 'None') at line 145
[NOT IMPLEMENTED] Variable assignment (label: 'None') at line 149
[NOT IMPLEMENTED] Variable assignment (label: 'None') at line 150
[NOT IMPLEMENTED] Variable assignment (label: 'None') at line 153
[NOT IMPLEMENTED] Variable assignment (label: 'None') at line 155
[NOT IMPLEMENTED] Variable assignment (label: 'None') at line 155
libghdl processing time:  761.604 us
DOM translation time:    9607.356 us

Design:
  Libraries:
    - Name: pretty
      Entities:
        - mult(stru)
      Packages:
      Configurations:
      Contexts:
  Documents:
    - Path: '/home/runner/work/extended-tests/extended-tests/ghdl/testsuite/synth/issue1122/mult.vhd':
      Entities:
        - Name: mult
          File: mult.vhd
          Position: 6:7
          Generics:
          Ports:
            - clk : in std_logic
            - rst : in std_logic
            - slot : in std_logic
            - a : in mult_i_t
            - y : out mult_o_t
          Declared:
          Statements:
          Architecures:
          - stru
      Architectures:
        - Name: stru
          File: mult.vhd
          Position: 14:13
          Entity: mult
          Declared:
            - signal this_c : mult_reg_t
            - signal this_r : mult_reg_t := MULT_RESET
          Hierarchy:
            - mult: process(...)
            - mult_r0: process(...)
          Statements:
            ...
            ...
            ...
            ...
      Packages:
      PackageBodies:
      Configurations:
      Contexts:

Teardown

XPASS test_AllVHDLSources[/home/runner/work/extended-tests/extended-tests/ghdl/testsuite/synth/issue1911/neorv32_package.vhd] 0:00:00.250170

Started 2021-11-23 15:22:28
Ended 2021-11-23 15:22:28
Duration 0:00:00.250170
Markers
xfail
Fixtures file

Setup

Call

Captured stdout call
================================================================================
                         pyGHDL.dom - Test Application                          
================================================================================
Parsing file '/home/runner/work/extended-tests/extended-tests/ghdl/testsuite/synth/issue1911/neorv32_package.vhd'
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Array_Subtype_Definition
[NOT IMPLEMENTED] Array_Subtype_Definition
[NOT IMPLEMENTED] Array_Subtype_Definition
[NOT IMPLEMENTED] Array_Subtype_Definition
[NOT IMPLEMENTED] Array_Subtype_Definition
[NOT IMPLEMENTED] function declaration without body
[NOT IMPLEMENTED] function declaration without body
libghdl processing time:  300.202 us
DOM translation time:    1534.209 us

Design:
  Libraries:
    - Name: pretty
      Entities:
      Packages:
        - neorv32_package
      Configurations:
      Contexts:
  Documents:
    - Path: '/home/runner/work/extended-tests/extended-tests/ghdl/testsuite/synth/issue1911/neorv32_package.vhd':
      Entities:
      Architectures:
      Packages:
        - Name: neorv32_package
          File: neorv32_package.vhd
          Position: 39:8
          Declared:
          - constant ispace_base_c : std_ulogic_vector(31 downto 0) := None
          - constant dspace_base_c : std_ulogic_vector(31 downto 0) := None
          - constant dedicated_reset_c : boolean := false
          - constant cp_timeout_en_c : boolean := false
          - constant pmp_num_regions_critical_c : natural := 8
          - constant max_proc_int_response_time_c : natural := 15
          - constant jtag_tap_idcode_version_c : std_ulogic_vector(3 downto 0) := None
          - constant jtag_tap_idcode_partid_c : std_ulogic_vector(15 downto 0) := None
          - constant jtag_tap_idcode_manid_c : std_ulogic_vector(10 downto 0) := "00000000000"
          - constant data_width_c : natural := 32
          - constant hw_version_c : std_ulogic_vector(31 downto 0) := None
          - constant archid_c : natural := 19
          - type ???? is array(........) of .....
          - type ???? is array(........) of .....
          - type ???? is array(........) of .....
          - type ???? is array(........) of .....
          - type ???? is array(........) of .....
          - type mem32_t is array(........) of .....
          - type mem8_t is array(........) of .....
      PackageBodies:
        - Name: neorv32_package
          Declared:
          - function index_size_f return natural
          - function is_power_of_two_f return boolean
      Configurations:
      Contexts:

Teardown

XPASS test_AllVHDLSources[/home/runner/work/extended-tests/extended-tests/ghdl/testsuite/synth/issue1911/neorv32_fifo.vhd] 0:00:00.251455

Started 2021-11-23 15:22:28
Ended 2021-11-23 15:22:28
Duration 0:00:00.251455
Markers
xfail
Fixtures file

Setup

Call

Captured stdout call
================================================================================
                         pyGHDL.dom - Test Application                          
================================================================================
Parsing file '/home/runner/work/extended-tests/extended-tests/ghdl/testsuite/synth/issue1911/neorv32_fifo.vhd'
[NOT IMPLEMENTED] Array_Subtype_Definition
[NOT IMPLEMENTED] Concurrent (conditional) signal assignment (label: 'None') at line 99
[NOT IMPLEMENTED] Concurrent (conditional) signal assignment (label: 'None') at line 100
[NOT IMPLEMENTED] Concurrent (conditional) signal assignment (label: 'None') at line 127
[NOT IMPLEMENTED] Concurrent (conditional) signal assignment (label: 'None') at line 128
[NOT IMPLEMENTED] Concurrent (conditional) signal assignment (label: 'None') at line 129
[NOT IMPLEMENTED] Concurrent (conditional) signal assignment (label: 'None') at line 133
[NOT IMPLEMENTED] Concurrent (conditional) signal assignment (label: 'None') at line 169
libghdl processing time:  483.103 us
DOM translation time:    5565.832 us

Design:
  Libraries:
    - Name: pretty
      Entities:
        - neorv32_fifo(neorv32_fifo_rtl)
      Packages:
      Configurations:
      Contexts:
  Documents:
    - Path: '/home/runner/work/extended-tests/extended-tests/ghdl/testsuite/synth/issue1911/neorv32_fifo.vhd':
      Entities:
        - Name: neorv32_fifo
          File: neorv32_fifo.vhd
          Position: 42:7
          Generics:
            - FIFO_DEPTH : in natural
            - FIFO_WIDTH : in natural
            - FIFO_RSYNC : in boolean
            - FIFO_SAFE : in boolean
          Ports:
            - clk_i : in std_ulogic
            - rstn_i : in std_ulogic
            - clear_i : in std_ulogic
            - level_o : out std_ulogic_vector(index_size_f(FIFO_DEPTH) downto 0)
            - half_o : out std_ulogic
            - wdata_i : in std_ulogic_vector(FIFO_WIDTH - 1 downto 0)
            - we_i : in std_ulogic
            - free_o : out std_ulogic
            - re_i : in std_ulogic
            - rdata_o : out std_ulogic_vector(FIFO_WIDTH - 1 downto 0)
            - avail_o : out std_ulogic
          Declared:
          Statements:
          Architecures:
          - neorv32_fifo_rtl
      Architectures:
        - Name: neorv32_fifo_rtl
          File: neorv32_fifo.vhd
          Position: 67:13
          Entity: neorv32_fifo
          Declared:
            - type ???? is array(........) of .....
            - type fifo_t is record ..... end record
            - signal fifo : fifo_t
            - signal level_diff : std_ulogic_vector(index_size_f(FIFO_DEPTH) downto 0)
          Hierarchy:
            - fifo_control: process(...)
            - fifo_half_level: if (FIFO_DEPTH > 1) generate
            - fifo_half_level_simple: if (FIFO_DEPTH = 1) generate
            - fifo_memory_write: process(...)
            - fifo_read_async: if (FIFO_RSYNC = false) generate
            - fifo_read_sync: if (FIFO_RSYNC = true) generate
                - fifo_memory_read: process(...)
          Statements:
            ...
            ...
            ...
            ...
            ...
            ...
            ...
            ...
            ...
            ...
            ...
            ...
            ...
            ...
      Packages:
      PackageBodies:
      Configurations:
      Contexts:

Teardown

XPASS test_AllVHDLSources[/home/runner/work/extended-tests/extended-tests/ghdl/testsuite/synth/issue1307/hdmi_design.vhd] 0:00:00.258759

Started 2021-11-23 15:22:28
Ended 2021-11-23 15:22:28
Duration 0:00:00.258759
Markers
xfail
Fixtures file

Setup

Call

Captured stdout call
================================================================================
                         pyGHDL.dom - Test Application                          
================================================================================
Parsing file '/home/runner/work/extended-tests/extended-tests/ghdl/testsuite/synth/issue1307/hdmi_design.vhd'
libghdl processing time:  508.503 us
DOM translation time:    5600.332 us

Design:
  Libraries:
    - Name: pretty
      Entities:
        - hdmi_design(Behavioral)
      Packages:
      Configurations:
      Contexts:
  Documents:
    - Path: '/home/runner/work/extended-tests/extended-tests/ghdl/testsuite/synth/issue1307/hdmi_design.vhd':
      Entities:
        - Name: hdmi_design
          File: hdmi_design.vhd
          Position: 4:7
          Generics:
          Ports:
            - clk100 : in STD_LOGIC
            - led : out std_logic_vector(7 downto 0) := (others => 0)
            - sw : in std_logic_vector(7 downto 0) := (others => 0)
            - debug_pmod : out std_logic_vector(7 downto 0) := (others => 0)
            - hdmi_rx_cec : inout std_logic
            - hdmi_rx_hpa : out std_logic
            - hdmi_rx_scl : in std_logic
            - hdmi_rx_sda : inout std_logic
            - hdmi_rx_txen : out std_logic
            - hdmi_rx_clk_n : in std_logic
            - hdmi_rx_clk_p : in std_logic
            - hdmi_rx_n : in std_logic_vector(2 downto 0)
            - hdmi_rx_p : in std_logic_vector(2 downto 0)
            - hdmi_tx_cec : inout std_logic
            - hdmi_tx_clk_n : out std_logic
            - hdmi_tx_clk_p : out std_logic
            - hdmi_tx_hpd : in std_logic
            - hdmi_tx_rscl : inout std_logic
            - hdmi_tx_rsda : inout std_logic
            - hdmi_tx_p : out std_logic_vector(2 downto 0)
            - hdmi_tx_n : out std_logic_vector(2 downto 0)
            - rs232_tx : out std_logic
          Declared:
          Statements:
          Architecures:
          - Behavioral
      Architectures:
        - Name: Behavioral
          File: hdmi_design.vhd
          Position: 37:13
          Entity: hdmi_design
          Declared:
            - Component: hdmi_io
              Generics:
              Ports:
                - clk100 : in STD_LOGIC
                - clock_locked : out std_logic
                - data_synced : out std_logic
                - debug : out std_logic_vector(7 downto 0)
                - hdmi_rx_cec : inout std_logic
                - hdmi_rx_hpa : out std_logic
                - hdmi_rx_scl : in std_logic
                - hdmi_rx_sda : inout std_logic
                - hdmi_rx_txen : out std_logic
                - hdmi_rx_clk_n : in std_logic
                - hdmi_rx_clk_p : in std_logic
                - hdmi_rx_n : in std_logic_vector(2 downto 0)
                - hdmi_rx_p : in std_logic_vector(2 downto 0)
                - hdmi_tx_cec : inout std_logic
                - hdmi_tx_clk_n : out std_logic
                - hdmi_tx_clk_p : out std_logic
                - hdmi_tx_hpd : in std_logic
                - hdmi_tx_rscl : inout std_logic
                - hdmi_tx_rsda : inout std_logic
                - hdmi_tx_p : out std_logic_vector(2 downto 0)
                - hdmi_tx_n : out std_logic_vector(2 downto 0)
                - pixel_clk : out std_logic
                - in_hdmi_detected : out std_logic
                - in_blank : out std_logic
                - in_hsync : out std_logic
                - in_vsync : out std_logic
                - in_red : out std_logic_vector(7 downto 0)
                - in_green : out std_logic_vector(7 downto 0)
                - in_blue : out std_logic_vector(7 downto 0)
                - is_interlaced : out std_logic
                - is_second_field : out std_logic
                - audio_channel : out std_logic_vector(2 downto 0)
                - audio_de : out std_logic
                - audio_sample : out std_logic_vector(23 downto 0)
                - out_blank : in std_logic
                - out_hsync : in std_logic
                - out_vsync : in std_logic
                - out_red : in std_logic_vector(7 downto 0)
                - out_green : in std_logic_vector(7 downto 0)
                - out_blue : in std_logic_vector(7 downto 0)
                - symbol_sync : out std_logic
                - symbol_ch0 : out std_logic_vector(9 downto 0)
                - symbol_ch1 : out std_logic_vector(9 downto 0)
                - symbol_ch2 : out std_logic_vector(9 downto 0)
            - signal symbol_sync : std_logic
            - signal symbol_ch0 : std_logic_vector(9 downto 0)
            - signal symbol_ch1 : std_logic_vector(9 downto 0)
            - signal symbol_ch2 : std_logic_vector(9 downto 0)
            - Component: pixel_processing
              Generics:
              Ports:
                - clk : in STD_LOGIC
                - switches : in std_logic_vector(7 downto 0)
                - in_blank : in std_logic
                - in_hsync : in std_logic
                - in_vsync : in std_logic
                - in_red : in std_logic_vector(7 downto 0)
                - in_green : in std_logic_vector(7 downto 0)
                - in_blue : in std_logic_vector(7 downto 0)
                - is_interlaced : in std_logic
                - is_second_field : in std_logic
                - out_blank : out std_logic
                - out_hsync : out std_logic
                - out_vsync : out std_logic
                - out_red : out std_logic_vector(7 downto 0)
                - out_green : out std_logic_vector(7 downto 0)
                - out_blue : out std_logic_vector(7 downto 0)
                - audio_channel : in std_logic_vector(2 downto 0)
                - audio_de : in std_logic
                - audio_sample : in std_logic_vector(23 downto 0)
            - Component: symbol_dump
              Generics:
              Ports:
                - clk : in std_logic
                - clk100 : in std_logic
                - symbol_sync : in std_logic
                - symbol_ch0 : in std_logic_vector(9 downto 0)
                - symbol_ch1 : in std_logic_vector(9 downto 0)
                - symbol_ch2 : in std_logic_vector(9 downto 0)
                - rs232_tx : out std_logic
            - signal pixel_clk : std_logic
            - signal in_blank : std_logic
            - signal in_hsync : std_logic
            - signal in_vsync : std_logic
            - signal in_red : std_logic_vector(7 downto 0)
            - signal in_green : std_logic_vector(7 downto 0)
            - signal in_blue : std_logic_vector(7 downto 0)
            - signal is_interlaced : std_logic
            - signal is_second_field : std_logic
            - signal out_blank : std_logic
            - signal out_hsync : std_logic
            - signal out_vsync : std_logic
            - signal out_red : std_logic_vector(7 downto 0)
            - signal out_green : std_logic_vector(7 downto 0)
            - signal out_blue : std_logic_vector(7 downto 0)
            - signal audio_channel : std_logic_vector(2 downto 0)
            - signal audio_de : std_logic
            - signal audio_sample : std_logic_vector(23 downto 0)
            - signal debug : std_logic_vector(7 downto 0)
          Hierarchy:
            - i_processing: component pixel_processing
          Statements:
            ...
      Packages:
      PackageBodies:
      Configurations:
      Contexts:

Teardown

XPASS test_AllVHDLSources[/home/runner/work/extended-tests/extended-tests/ghdl/testsuite/synth/issue1307/line_delay.vhd] 0:00:00.341937

Started 2021-11-23 15:22:28
Ended 2021-11-23 15:22:28
Duration 0:00:00.341937
Markers
xfail
Fixtures file

Setup

Call

Captured stdout call
================================================================================
                         pyGHDL.dom - Test Application                          
================================================================================
Parsing file '/home/runner/work/extended-tests/extended-tests/ghdl/testsuite/synth/issue1307/line_delay.vhd'
[NOT IMPLEMENTED] Array_Subtype_Definition
[NOT IMPLEMENTED] Variable assignment (label: 'None') at line 39
libghdl processing time:  203.401 us
DOM translation time:    2244.513 us

Design:
  Libraries:
    - Name: pretty
      Entities:
        - line_delay(Behavioral)
      Packages:
      Configurations:
      Contexts:
  Documents:
    - Path: '/home/runner/work/extended-tests/extended-tests/ghdl/testsuite/synth/issue1307/line_delay.vhd':
      Entities:
        - Name: line_delay
          File: line_delay.vhd
          Position: 5:7
          Generics:
          Ports:
            - clk : in STD_LOGIC
            - in_blank : in std_logic
            - in_hsync : in std_logic
            - in_vsync : in std_logic
            - in_red : in std_logic_vector(7 downto 0)
            - in_green : in std_logic_vector(7 downto 0)
            - in_blue : in std_logic_vector(7 downto 0)
            - out_blank : out std_logic
            - out_hsync : out std_logic
            - out_vsync : out std_logic
            - out_red : out std_logic_vector(7 downto 0)
            - out_green : out std_logic_vector(7 downto 0)
            - out_blue : out std_logic_vector(7 downto 0)
          Declared:
          Statements:
          Architecures:
          - Behavioral
      Architectures:
        - Name: Behavioral
          File: line_delay.vhd
          Position: 28:13
          Entity: line_delay
          Declared:
            - type ???? is array(........) of .....
            - signal mem_4 : mem_block := (others => (others => 0))
            - signal wr_addr : unsigned(8 downto 0) := (others => 1)
            - signal mid_3 : std_logic_vector(26 downto 0) := (others => 0)
          Hierarchy:
            - None: process(...)
          Statements:
            ...
      Packages:
      PackageBodies:
      Configurations:
      Contexts:

Teardown

XPASS test_AllVHDLSources[/home/runner/work/extended-tests/extended-tests/ghdl/testsuite/synth/issue1307/edge_enhance.vhd] 0:00:00.310014

Started 2021-11-23 15:22:28
Ended 2021-11-23 15:22:29
Duration 0:00:00.310014
Markers
xfail
Fixtures file

Setup

Call

Captured stdout call
================================================================================
                         pyGHDL.dom - Test Application                          
================================================================================
Parsing file '/home/runner/work/extended-tests/extended-tests/ghdl/testsuite/synth/issue1307/edge_enhance.vhd'
[NOT IMPLEMENTED] Array_Subtype_Definition
[NOT IMPLEMENTED] Array_Subtype_Definition
libghdl processing time:  334.101 us
DOM translation time:    4749.728 us

Design:
  Libraries:
    - Name: pretty
      Entities:
        - edge_enhance(Behavioral)
      Packages:
      Configurations:
      Contexts:
  Documents:
    - Path: '/home/runner/work/extended-tests/extended-tests/ghdl/testsuite/synth/issue1307/edge_enhance.vhd':
      Entities:
        - Name: edge_enhance
          File: edge_enhance.vhd
          Position: 5:7
          Generics:
          Ports:
            - clk : in STD_LOGIC
            - enable_feature : in std_logic
            - in_blank : in std_logic
            - in_hsync : in std_logic
            - in_vsync : in std_logic
            - in_red : in std_logic_vector(7 downto 0)
            - in_green : in std_logic_vector(7 downto 0)
            - in_blue : in std_logic_vector(7 downto 0)
            - out_blank : out std_logic
            - out_hsync : out std_logic
            - out_vsync : out std_logic
            - out_red : out std_logic_vector(7 downto 0)
            - out_green : out std_logic_vector(7 downto 0)
            - out_blue : out std_logic_vector(7 downto 0)
          Declared:
          Statements:
          Architecures:
          - Behavioral
      Architectures:
        - Name: Behavioral
          File: edge_enhance.vhd
          Position: 28:13
          Entity: edge_enhance
          Declared:
            - Component: line_delay
              Generics:
              Ports:
                - clk : in STD_LOGIC
                - in_blank : in std_logic
                - in_hsync : in std_logic
                - in_vsync : in std_logic
                - in_red : in std_logic_vector(7 downto 0)
                - in_green : in std_logic_vector(7 downto 0)
                - in_blue : in std_logic_vector(7 downto 0)
                - out_blank : out std_logic
                - out_hsync : out std_logic
                - out_vsync : out std_logic
                - out_red : out std_logic_vector(7 downto 0)
                - out_green : out std_logic_vector(7 downto 0)
                - out_blue : out std_logic_vector(7 downto 0)
            - type ???? is array(........) of .....
            - type ???? is array(........) of .....
            - signal blanks : a_bits
            - signal hsyncs : a_bits
            - signal vsyncs : a_bits
            - signal reds : a_component
            - signal greens : a_component
            - signal blues : a_component
            - signal sobel_1_blue : unsigned(12 downto 0) := (others => 0)
            - signal sobel_1_blue_x : unsigned(11 downto 0) := (others => 0)
            - signal sobel_1_blue_y : unsigned(11 downto 0) := (others => 0)
            - signal sobel_3_blue : unsigned(12 downto 0) := (others => 0)
            - signal sobel_2_blue_x : unsigned(11 downto 0) := (others => 0)
            - signal sobel_2_blue_y : unsigned(11 downto 0) := (others => 0)
            - signal sobel_1_green_left : unsigned(11 downto 0) := (others => 0)
            - signal sobel_1_green_right : unsigned(11 downto 0) := (others => 0)
            - signal sobel_1_blue_left : unsigned(11 downto 0) := (others => 0)
            - signal sobel_1_blue_right : unsigned(11 downto 0) := (others => 0)
            - signal test : std_logic_vector(7 downto 0) := (others => 0)
            - signal test2 : std_logic_vector(7 downto 0) := (others => 0)
          Hierarchy:
            - i_line_delay_2: component line_delay
            - None: process(...)
          Statements:
            ...
            ...
      Packages:
      PackageBodies:
      Configurations:
      Contexts:

Teardown

XPASS test_AllVHDLSources[/home/runner/work/extended-tests/extended-tests/ghdl/testsuite/synth/issue1307/pixel_processing.vhd] 0:00:00.331216

Started 2021-11-23 15:22:28
Ended 2021-11-23 15:22:29
Duration 0:00:00.331216
Markers
xfail
Fixtures file

Setup

Call

Captured stdout call
================================================================================
                         pyGHDL.dom - Test Application                          
================================================================================
Parsing file '/home/runner/work/extended-tests/extended-tests/ghdl/testsuite/synth/issue1307/pixel_processing.vhd'
libghdl processing time:  260.302 us
DOM translation time:    3987.223 us

Design:
  Libraries:
    - Name: pretty
      Entities:
        - pixel_processing(Behavioral)
      Packages:
      Configurations:
      Contexts:
  Documents:
    - Path: '/home/runner/work/extended-tests/extended-tests/ghdl/testsuite/synth/issue1307/pixel_processing.vhd':
      Entities:
        - Name: pixel_processing
          File: pixel_processing.vhd
          Position: 5:7
          Generics:
          Ports:
            - clk : in STD_LOGIC
            - in_blank : in std_logic
            - in_hsync : in std_logic
            - in_vsync : in std_logic
            - in_red : in std_logic_vector(7 downto 0)
            - in_green : in std_logic_vector(7 downto 0)
            - in_blue : in std_logic_vector(7 downto 0)
            - is_interlaced : in std_logic
            - is_second_field : in std_logic
            - out_blank : out std_logic
            - out_hsync : out std_logic
            - out_vsync : out std_logic
            - out_red : out std_logic_vector(7 downto 0)
            - out_green : out std_logic_vector(7 downto 0)
            - out_blue : out std_logic_vector(7 downto 0)
            - audio_channel : in std_logic_vector(2 downto 0)
            - audio_de : in std_logic
            - audio_sample : in std_logic_vector(23 downto 0)
            - switches : in std_logic_vector(7 downto 0)
          Declared:
          Statements:
          Architecures:
          - Behavioral
      Architectures:
        - Name: Behavioral
          File: pixel_processing.vhd
          Position: 41:13
          Entity: pixel_processing
          Declared:
            - Component: edge_enhance
              Generics:
              Ports:
                - clk : in STD_LOGIC
                - enable_feature : in std_logic
                - in_blank : in std_logic
                - in_hsync : in std_logic
                - in_vsync : in std_logic
                - in_red : in std_logic_vector(7 downto 0)
                - in_green : in std_logic_vector(7 downto 0)
                - in_blue : in std_logic_vector(7 downto 0)
                - out_blank : out std_logic
                - out_hsync : out std_logic
                - out_vsync : out std_logic
                - out_red : out std_logic_vector(7 downto 0)
                - out_green : out std_logic_vector(7 downto 0)
                - out_blue : out std_logic_vector(7 downto 0)
            - Component: guidelines
              Generics:
              Ports:
                - clk : in STD_LOGIC
                - enable_feature : in std_logic
                - in_blank : in std_logic
                - in_hsync : in std_logic
                - in_vsync : in std_logic
                - in_red : in std_logic_vector(7 downto 0)
                - in_green : in std_logic_vector(7 downto 0)
                - in_blue : in std_logic_vector(7 downto 0)
                - is_interlaced : in std_logic
                - is_second_field : in std_logic
                - out_blank : out std_logic
                - out_hsync : out std_logic
                - out_vsync : out std_logic
                - out_red : out std_logic_vector(7 downto 0)
                - out_green : out std_logic_vector(7 downto 0)
                - out_blue : out std_logic_vector(7 downto 0)
            - signal b_blank : std_logic
            - signal b_hsync : std_logic
            - signal b_vsync : std_logic
            - signal b_red : std_logic_vector(7 downto 0)
            - signal b_green : std_logic_vector(7 downto 0)
            - signal b_blue : std_logic_vector(7 downto 0)
            - signal c_blank : std_logic
            - signal c_hsync : std_logic
            - signal c_vsync : std_logic
            - signal c_red : std_logic_vector(7 downto 0)
            - signal c_green : std_logic_vector(7 downto 0)
            - signal c_blue : std_logic_vector(7 downto 0)
          Hierarchy:
            - i_edge_enhance: component edge_enhance
          Statements:
            ...
      Packages:
      PackageBodies:
      Configurations:
      Contexts:

Teardown

XPASS test_AllVHDLSources[/home/runner/work/extended-tests/extended-tests/ghdl/testsuite/synth/synth109/asymmetric_ram_2b.vhd] 0:00:00.284606

Started 2021-11-23 15:22:29
Ended 2021-11-23 15:22:29
Duration 0:00:00.284606
Markers
xfail
Fixtures file

Setup

Call

Captured stdout call
================================================================================
                         pyGHDL.dom - Test Application                          
================================================================================
Parsing file '/home/runner/work/extended-tests/extended-tests/ghdl/testsuite/synth/synth109/asymmetric_ram_2b.vhd'
[NOT IMPLEMENTED] Array_Subtype_Definition
[NOT IMPLEMENTED] Variable assignment (label: 'None') at line 96
libghdl processing time:  292.502 us
DOM translation time:    4215.224 us

Design:
  Libraries:
    - Name: pretty
      Entities:
        - asymmetric_ram_2b(behavioral)
      Packages:
      Configurations:
      Contexts:
  Documents:
    - Path: '/home/runner/work/extended-tests/extended-tests/ghdl/testsuite/synth/synth109/asymmetric_ram_2b.vhd':
      Entities:
        - Name: asymmetric_ram_2b
          File: asymmetric_ram_2b.vhd
          Position: 15:7
          Generics:
            - WIDTHA : in integer := 8
            - SIZEA : in integer := 256
            - ADDRWIDTHA : in integer := 8
            - WIDTHB : in integer := 32
            - SIZEB : in integer := 64
            - ADDRWIDTHB : in integer := 6
          Ports:
            - clkA : in std_logic
            - clkB : in std_logic
            - enA : in std_logic
            - enB : in std_logic
            - weA : in std_logic
            - weB : in std_logic
            - addrA : in std_logic_vector(ADDRWIDTHA - 1 downto 0)
            - addrB : in std_logic_vector(ADDRWIDTHB - 1 downto 0)
            - diA : in std_logic_vector(WIDTHA - 1 downto 0)
            - diB : in std_logic_vector(WIDTHB - 1 downto 0)
            - doA : out std_logic_vector(WIDTHA - 1 downto 0)
            - doB : out std_logic_vector(WIDTHB - 1 downto 0)
          Declared:
          Statements:
          Architecures:
          - behavioral
      Architectures:
        - Name: behavioral
          File: asymmetric_ram_2b.vhd
          Position: 43:13
          Entity: asymmetric_ram_2b
          Declared:
            - function max return INTEGER
            - function min return INTEGER
            - function log2 return natural
            - constant minWIDTH : integer := min(WIDTHA, WIDTHB)
            - constant maxWIDTH : integer := max(WIDTHA, WIDTHB)
            - constant maxSIZE : integer := max(SIZEA, SIZEB)
            - constant RATIO : integer := maxWIDTH / minWIDTH
            - type ???? is array(........) of .....
            - shared variable ram : ramType
            - signal readA : std_logic_vector(WIDTHA - 1 downto 0) := (others => 0)
            - signal readB : std_logic_vector(WIDTHB - 1 downto 0) := (others => 0)
            - signal regA : std_logic_vector(WIDTHA - 1 downto 0) := (others => 0)
            - signal regB : std_logic_vector(WIDTHB - 1 downto 0) := (others => 0)
          Hierarchy:
            - None: process(...)
            - None: process(...)
          Statements:
            ...
            ...
            ...
            ...
      Packages:
      PackageBodies:
      Configurations:
      Contexts:

Teardown

XPASS test_AllVHDLSources[/home/runner/work/extended-tests/extended-tests/ghdl/testsuite/synth/synth109/asymmetric_ram_2a.vhd] 0:00:00.258327

Started 2021-11-23 15:22:29
Ended 2021-11-23 15:22:29
Duration 0:00:00.258327
Markers
xfail
Fixtures file

Setup

Call

Captured stdout call
================================================================================
                         pyGHDL.dom - Test Application                          
================================================================================
Parsing file '/home/runner/work/extended-tests/extended-tests/ghdl/testsuite/synth/synth109/asymmetric_ram_2a.vhd'
[NOT IMPLEMENTED] Array_Subtype_Definition
[NOT IMPLEMENTED] Variable assignment (label: 'None') at line 83
[NOT IMPLEMENTED] Variable assignment (label: 'None') at line 96
[NOT IMPLEMENTED] Variable assignment (label: 'None') at line 97
[NOT IMPLEMENTED] Variable assignment (label: 'None') at line 98
[NOT IMPLEMENTED] Variable assignment (label: 'None') at line 99
libghdl processing time:  285.501 us
DOM translation time:    5000.029 us

Design:
  Libraries:
    - Name: pretty
      Entities:
        - asymmetric_ram_2a(behavioral)
      Packages:
      Configurations:
      Contexts:
  Documents:
    - Path: '/home/runner/work/extended-tests/extended-tests/ghdl/testsuite/synth/synth109/asymmetric_ram_2a.vhd':
      Entities:
        - Name: asymmetric_ram_2a
          File: asymmetric_ram_2a.vhd
          Position: 14:7
          Generics:
            - WIDTHA : in integer := 8
            - SIZEA : in integer := 256
            - ADDRWIDTHA : in integer := 8
            - WIDTHB : in integer := 32
            - SIZEB : in integer := 64
            - ADDRWIDTHB : in integer := 6
          Ports:
            - clkA : in std_logic
            - clkB : in std_logic
            - enA : in std_logic
            - enB : in std_logic
            - weA : in std_logic
            - weB : in std_logic
            - addrA : in std_logic_vector(ADDRWIDTHA - 1 downto 0)
            - addrB : in std_logic_vector(ADDRWIDTHB - 1 downto 0)
            - diA : in std_logic_vector(WIDTHA - 1 downto 0)
            - diB : in std_logic_vector(WIDTHB - 1 downto 0)
            - doA : out std_logic_vector(WIDTHA - 1 downto 0)
            - doB : out std_logic_vector(WIDTHB - 1 downto 0)
          Declared:
          Statements:
          Architecures:
          - behavioral
      Architectures:
        - Name: behavioral
          File: asymmetric_ram_2a.vhd
          Position: 42:13
          Entity: asymmetric_ram_2a
          Declared:
            - function max return INTEGER
            - function min return INTEGER
            - constant minWIDTH : integer := min(WIDTHA, WIDTHB)
            - constant maxWIDTH : integer := max(WIDTHA, WIDTHB)
            - constant maxSIZE : integer := max(SIZEA, SIZEB)
            - constant RATIO : integer := maxWIDTH / minWIDTH
            - type ???? is array(........) of .....
            - shared variable ram : ramType
            - signal readA : std_logic_vector(WIDTHA - 1 downto 0) := (others => 0)
            - signal readB : std_logic_vector(WIDTHB - 1 downto 0) := (others => 0)
            - signal regA : std_logic_vector(WIDTHA - 1 downto 0) := (others => 0)
            - signal regB : std_logic_vector(WIDTHB - 1 downto 0) := (others => 0)
          Hierarchy:
            - None: process(...)
            - None: process(...)
          Statements:
            ...
            ...
            ...
            ...
      Packages:
      PackageBodies:
      Configurations:
      Contexts:

Teardown

XPASS test_AllVHDLSources[/home/runner/work/extended-tests/extended-tests/ghdl/testsuite/synth/issue1244/ram_protected_sharedvar.vhd] 0:00:00.261897

Started 2021-11-23 15:22:29
Ended 2021-11-23 15:22:29
Duration 0:00:00.261897
Markers
xfail
Fixtures file

Setup

Call

Captured stdout call
================================================================================
                         pyGHDL.dom - Test Application                          
================================================================================
Parsing file '/home/runner/work/extended-tests/extended-tests/ghdl/testsuite/synth/issue1244/ram_protected_sharedvar.vhd'
[NOT IMPLEMENTED] Array_Subtype_Definition
libghdl processing time:  250.602 us
DOM translation time:    3109.818 us

Design:
  Libraries:
    - Name: pretty
      Entities:
        - ram_protected_sharedvar(behavioral)
      Packages:
        - ram_pkg
      Configurations:
      Contexts:
  Documents:
    - Path: '/home/runner/work/extended-tests/extended-tests/ghdl/testsuite/synth/issue1244/ram_protected_sharedvar.vhd':
      Entities:
        - Name: ram_protected_sharedvar
          File: ram_protected_sharedvar.vhd
          Position: 67:7
          Generics:
            - DATA_WIDTH : in integer := 16
            - ADDR_WIDTH : in integer := 7
          Ports:
            - clka : in std_logic
            - clkb : in std_logic
            - ena : in std_logic
            - enb : in std_logic
            - wea : in std_logic
            - web : in std_logic
            - addra : in std_logic_vector(ADDR_WIDTH - 1 downto 0)
            - addrb : in std_logic_vector(ADDR_WIDTH - 1 downto 0)
            - dia : in std_logic_vector(DATA_WIDTH - 1 downto 0)
            - dib : in std_logic_vector(DATA_WIDTH - 1 downto 0)
            - doa : out std_logic_vector(DATA_WIDTH - 1 downto 0)
            - dob : out std_logic_vector(DATA_WIDTH - 1 downto 0)
          Declared:
          Statements:
          Architecures:
          - behavioral
      Architectures:
        - Name: behavioral
          File: ram_protected_sharedvar.vhd
          Position: 89:13
          Entity: ram_protected_sharedvar
          Declared:
            - shared variable RAM : ram_type
          Hierarchy:
            - None: process(...)
            - None: process(...)
          Statements:
            ...
            ...
      Packages:
        - Name: ram_pkg
          File: ram_protected_sharedvar.vhd
          Position: 13:8
          Declared:
          - subtype data_type is ?????
          - type ram_type is protected ..... end protected
      PackageBodies:
        - Name: ram_pkg
          Declared:
          - type ???? is array(........) of .....
          - type ram_type is protected body ..... end protected body
      Configurations:
      Contexts:

Teardown

XPASS test_AllVHDLSources[/home/runner/work/extended-tests/extended-tests/ghdl/testsuite/synth/synth111/rams_sdp_3d.vhd] 0:00:00.265673

Started 2021-11-23 15:22:29
Ended 2021-11-23 15:22:29
Duration 0:00:00.265673
Markers
xfail
Fixtures file

Setup

Call

Captured stdout call
================================================================================
                         pyGHDL.dom - Test Application                          
================================================================================
Parsing file '/home/runner/work/extended-tests/extended-tests/ghdl/testsuite/synth/synth111/rams_sdp_3d.vhd'
libghdl processing time:  266.101 us
DOM translation time:    1829.510 us

Design:
  Libraries:
    - Name: pretty
      Entities:
        - rams_sdp_3d(arch)
      Packages:
        - mypack
      Configurations:
      Contexts:
  Documents:
    - Path: '/home/runner/work/extended-tests/extended-tests/ghdl/testsuite/synth/synth111/rams_sdp_3d.vhd':
      Entities:
        - Name: rams_sdp_3d
          File: rams_sdp_3d.vhd
          Position: 16:7
          Generics:
            - NUM_RAMS : in integer := 2
            - A_WID : in integer := 10
            - D_WID : in integer := 32
          Ports:
            - clka : in std_logic
            - clkb : in std_logic
            - wea : in std_logic_vector(NUM_RAMS - 1 downto 0)
            - ena : in std_logic_vector(NUM_RAMS - 1 downto 0)
            - enb : in std_logic_vector(NUM_RAMS - 1 downto 0)
            - addra : in myarray_t(NUM_RAMS - 1 downto 0)
            - addrb : in myarray_t(NUM_RAMS - 1 downto 0)
            - dina : in myarray_t(NUM_RAMS - 1 downto 0)
            - doutb : out myarray_t(NUM_RAMS - 1 downto 0)
          Declared:
          Statements:
          Architecures:
          - arch
      Architectures:
        - Name: arch
          File: rams_sdp_3d.vhd
          Position: 34:13
          Entity: rams_sdp_3d
          Declared:
            - signal mem : mem_t(NUM_RAMS - 1 downto 0)
          Hierarchy:
            - None: process(...)
            - None: process(...)
          Statements:
            ...
            ...
      Packages:
        - Name: mypack
          File: rams_sdp_3d.vhd
          Position: 7:8
          Declared:
          - type myarray_t is array(........) of .....
          - type mem_t is array(........) of .....
      PackageBodies:
      Configurations:
      Contexts:

Teardown

XPASS test_AllVHDLSources[/home/runner/work/extended-tests/extended-tests/ghdl/testsuite/gna/ticket19/psl_test_cover3.vhd] 0:00:00.264832

Started 2021-11-23 15:22:29
Ended 2021-11-23 15:22:29
Duration 0:00:00.264832
Markers
xfail
Fixtures file

Setup